175 #define RIEBL_MAGIC_ADDR	((unsigned long *)(((char *)MEM) + 0xee8a))
176 #define RIEBL_HWADDR_ADDR	((unsigned char *)(((char *)MEM) + 0xee8e))
177 #define RIEBL_IVEC_ADDR		((unsigned short *)(((char *)MEM) + 0xfffe))
233 #define	MEM		lp->mem  macro
241 #define	PKTBUF_ADDR(head)	(((unsigned char *)(MEM)) + (head)->base)
533 	MEM = (struct lance_memory *)memaddr;  in lance_probe1()
601 				((((unsigned short *)MEM)[i*2] & 0x0f) << 4) |  in lance_probe1()
602 				((((unsigned short *)MEM)[i*2+1] & 0x0f));  in lance_probe1()
615 	MEM->init.mode = 0x0000;		/* Disable Rx and Tx. */  in lance_probe1()
617 		MEM->init.hwaddr[i] = dev->dev_addr[i^1]; /* <- 16 bit swap! */  in lance_probe1()
618 	MEM->init.filter[0] = 0x00000000;  in lance_probe1()
619 	MEM->init.filter[1] = 0x00000000;  in lance_probe1()
620 	MEM->init.rx_ring.adr_lo = offsetof( struct lance_memory, rx_head );  in lance_probe1()
621 	MEM->init.rx_ring.adr_hi = 0;  in lance_probe1()
622 	MEM->init.rx_ring.len    = RX_RING_LEN_BITS;  in lance_probe1()
623 	MEM->init.tx_ring.adr_lo = offsetof( struct lance_memory, tx_head );  in lance_probe1()
624 	MEM->init.tx_ring.adr_hi = 0;  in lance_probe1()
625 	MEM->init.tx_ring.len    = TX_RING_LEN_BITS;  in lance_probe1()
710 		MEM->tx_head[i].base = offset;  in lance_init_ring()
711 		MEM->tx_head[i].flag = TMD1_OWN_HOST;  in lance_init_ring()
712  		MEM->tx_head[i].base_hi = 0;  in lance_init_ring()
713 		MEM->tx_head[i].length = 0;  in lance_init_ring()
714 		MEM->tx_head[i].misc = 0;  in lance_init_ring()
720 		MEM->rx_head[i].base = offset;  in lance_init_ring()
721 		MEM->rx_head[i].flag = TMD1_OWN_CHIP;  in lance_init_ring()
722 		MEM->rx_head[i].base_hi = 0;  in lance_init_ring()
723 		MEM->rx_head[i].buf_length = -PKT_BUF_SZ;  in lance_init_ring()
724 		MEM->rx_head[i].msg_length = 0;  in lance_init_ring()
756 							  i, MEM->rx_head[i].base,  in lance_tx_timeout()
757 							  -MEM->rx_head[i].buf_length,  in lance_tx_timeout()
758 							  MEM->rx_head[i].msg_length ));  in lance_tx_timeout()
761 							  i, MEM->tx_head[i].base,  in lance_tx_timeout()
762 							  -MEM->tx_head[i].length,  in lance_tx_timeout()
763 							  MEM->tx_head[i].misc ));  in lance_tx_timeout()
818 	head  = &(MEM->tx_head[entry]);  in lance_start_xmit()
840 	if ((MEM->tx_head[(entry+1) & TX_RING_MOD_MASK].flag & TMD1_OWN) ==  in lance_start_xmit()
889 				int status = MEM->tx_head[entry].flag;  in lance_interrupt()
894 				MEM->tx_head[entry].flag = 0;  in lance_interrupt()
898 					int err_status = MEM->tx_head[entry].misc;  in lance_interrupt()
971 				  MEM->rx_head[entry].flag ));  in lance_rx()
974 	while( (MEM->rx_head[entry].flag & RMD1_OWN) == RMD1_OWN_HOST ) {  in lance_rx()
975 		struct lance_rx_head *head = &(MEM->rx_head[entry]);  in lance_rx()
1005 						if (MEM->rx_head[(entry+i) & RX_RING_MOD_MASK].flag &  in lance_rx()
1140 		MEM->init.hwaddr[i] = dev->dev_addr[i^1]; /* <- 16 bit swap! */  in lance_set_mac_address()