Lines Matching refs:mmr
320 unsigned long mmr = 0; in gru_chiplet_cpu_to_mmr() local
334 mmr = UVH_GR0_TLB_INT0_CONFIG + in gru_chiplet_cpu_to_mmr()
337 mmr = UVH_GR1_TLB_INT0_CONFIG + in gru_chiplet_cpu_to_mmr()
344 return mmr; in gru_chiplet_cpu_to_mmr()
366 unsigned long mmr; in gru_chiplet_setup_tlb_irq() local
370 mmr = gru_chiplet_cpu_to_mmr(chiplet, cpu, &core); in gru_chiplet_setup_tlb_irq()
371 if (mmr == 0) in gru_chiplet_setup_tlb_irq()
397 unsigned long mmr; in gru_chiplet_teardown_tlb_irq() local
403 mmr = gru_chiplet_cpu_to_mmr(chiplet, cpu, &core); in gru_chiplet_teardown_tlb_irq()
404 if (mmr == 0) in gru_chiplet_teardown_tlb_irq()
416 unsigned long mmr; in gru_chiplet_setup_tlb_irq() local
420 mmr = gru_chiplet_cpu_to_mmr(chiplet, cpu, &core); in gru_chiplet_setup_tlb_irq()
421 if (mmr == 0) in gru_chiplet_setup_tlb_irq()
424 irq = uv_setup_irq(irq_name, cpu, blade, mmr, UV_AFFINITY_CPU); in gru_chiplet_setup_tlb_irq()
445 unsigned long mmr; in gru_chiplet_teardown_tlb_irq() local
447 mmr = gru_chiplet_cpu_to_mmr(chiplet, cpu, &core); in gru_chiplet_teardown_tlb_irq()
448 if (mmr) { in gru_chiplet_teardown_tlb_irq()