155 					     ASIC3_OFFSET(INTR, P_INT_STAT));  in asic3_irq_demux()
384 	asic3_write_register(asic, ASIC3_OFFSET(CLOCK, SEL),  in asic3_irq_probe()
400 	asic3_write_register(asic, ASIC3_OFFSET(INTR, INT_MASK),  in asic3_irq_probe()
594 		cdex = asic3_read_register(asic, ASIC3_OFFSET(CLOCK, CDEX));  in asic3_clk_enable()
596 		asic3_write_register(asic, ASIC3_OFFSET(CLOCK, CDEX), cdex);  in asic3_clk_enable()
612 		cdex = asic3_read_register(asic, ASIC3_OFFSET(CLOCK, CDEX));  in asic3_clk_disable()
614 		asic3_write_register(asic, ASIC3_OFFSET(CLOCK, CDEX), cdex);  in asic3_clk_disable()
648 	asic3_set_register(asic, ASIC3_OFFSET(EXTCF, RESET),  in ds1wm_enable()
651 	asic3_set_register(asic, ASIC3_OFFSET(EXTCF, RESET),  in ds1wm_enable()
654 	asic3_set_register(asic, ASIC3_OFFSET(EXTCF, SELECT),  in ds1wm_enable()
665 	asic3_set_register(asic, ASIC3_OFFSET(EXTCF, SELECT),  in ds1wm_disable()
722 	asic3_set_register(asic, ASIC3_OFFSET(SDHWCTRL, SDCONF),  in asic3_mmc_enable()
724 	asic3_set_register(asic, ASIC3_OFFSET(SDHWCTRL, SDCONF),  in asic3_mmc_enable()
726 	asic3_set_register(asic, ASIC3_OFFSET(SDHWCTRL, SDCONF),  in asic3_mmc_enable()
728 	asic3_set_register(asic, ASIC3_OFFSET(SDHWCTRL, SDCONF),  in asic3_mmc_enable()
739 	asic3_write_register(asic, ASIC3_OFFSET(CLOCK, SEL),  in asic3_mmc_enable()
746 	asic3_set_register(asic, ASIC3_OFFSET(EXTCF, SELECT),  in asic3_mmc_enable()
750 	asic3_set_register(asic, ASIC3_OFFSET(SDHWCTRL, SDCONF),  in asic3_mmc_enable()
765 	asic3_set_register(asic, ASIC3_OFFSET(SDHWCTRL, SDCONF),  in asic3_mmc_disable()
801 	asic3_set_register(asic, ASIC3_OFFSET(EXTCF, SELECT),  in asic3_mfd_probe()
878 	asic3_write_register(asic, ASIC3_OFFSET(CLOCK, SEL), clksel);  in asic3_probe()
936 	asic3_write_register(asic, ASIC3_OFFSET(CLOCK, SEL), 0);  in asic3_remove()