134 	mt352_write(fe, clock_config,   sizeof(clock_config));  in mt352_pinnacle_init()
136 	mt352_write(fe, reset,          sizeof(reset));  in mt352_pinnacle_init()
137 	mt352_write(fe, adc_ctl_1_cfg,  sizeof(adc_ctl_1_cfg));  in mt352_pinnacle_init()
138 	mt352_write(fe, agc_cfg,        sizeof(agc_cfg));  in mt352_pinnacle_init()
139 	mt352_write(fe, capt_range_cfg, sizeof(capt_range_cfg));  in mt352_pinnacle_init()
140 	mt352_write(fe, gpp_ctl_cfg,    sizeof(gpp_ctl_cfg));  in mt352_pinnacle_init()
142 	mt352_write(fe, fsm_ctl_cfg,    sizeof(fsm_ctl_cfg));  in mt352_pinnacle_init()
143 	mt352_write(fe, scan_ctl_cfg,   sizeof(scan_ctl_cfg));  in mt352_pinnacle_init()
144 	mt352_write(fe, irq_cfg,        sizeof(irq_cfg));  in mt352_pinnacle_init()
157 	mt352_write(fe, clock_config,   sizeof(clock_config));  in mt352_aver777_init()
159 	mt352_write(fe, reset,          sizeof(reset));  in mt352_aver777_init()
160 	mt352_write(fe, adc_ctl_1_cfg,  sizeof(adc_ctl_1_cfg));  in mt352_aver777_init()
161 	mt352_write(fe, agc_cfg,        sizeof(agc_cfg));  in mt352_aver777_init()
162 	mt352_write(fe, capt_range_cfg, sizeof(capt_range_cfg));  in mt352_aver777_init()
175 	mt352_write(fe, clock_config,   sizeof(clock_config));  in mt352_avermedia_xc3028_init()
177 	mt352_write(fe, reset,          sizeof(reset));  in mt352_avermedia_xc3028_init()
178 	mt352_write(fe, adc_ctl_1_cfg,  sizeof(adc_ctl_1_cfg));  in mt352_avermedia_xc3028_init()
179 	mt352_write(fe, agc_cfg,        sizeof(agc_cfg));  in mt352_avermedia_xc3028_init()
180 	mt352_write(fe, capt_range_cfg, sizeof(capt_range_cfg));  in mt352_avermedia_xc3028_init()