47 	struct rdc321x_gpio *gpch;  in rdc_gpio_get_value()  local
51 	gpch = container_of(chip, struct rdc321x_gpio, chip);  in rdc_gpio_get_value()
52 	reg = gpio < 32 ? gpch->reg1_data_base : gpch->reg2_data_base;  in rdc_gpio_get_value()
54 	spin_lock(&gpch->lock);  in rdc_gpio_get_value()
55 	pci_write_config_dword(gpch->sb_pdev, reg,  in rdc_gpio_get_value()
56 					gpch->data_reg[gpio < 32 ? 0 : 1]);  in rdc_gpio_get_value()
57 	pci_read_config_dword(gpch->sb_pdev, reg, &value);  in rdc_gpio_get_value()
58 	spin_unlock(&gpch->lock);  in rdc_gpio_get_value()
66 	struct rdc321x_gpio *gpch;  in rdc_gpio_set_value_impl()  local
69 	gpch = container_of(chip, struct rdc321x_gpio, chip);  in rdc_gpio_set_value_impl()
72 		gpch->data_reg[reg] |= 1 << (gpio & 0x1f);  in rdc_gpio_set_value_impl()
74 		gpch->data_reg[reg] &= ~(1 << (gpio & 0x1f));  in rdc_gpio_set_value_impl()
76 	pci_write_config_dword(gpch->sb_pdev,  in rdc_gpio_set_value_impl()
77 			reg ? gpch->reg2_data_base : gpch->reg1_data_base,  in rdc_gpio_set_value_impl()
78 			gpch->data_reg[reg]);  in rdc_gpio_set_value_impl()
85 	struct rdc321x_gpio *gpch;  in rdc_gpio_set_value()  local
87 	gpch = container_of(chip, struct rdc321x_gpio, chip);  in rdc_gpio_set_value()
88 	spin_lock(&gpch->lock);  in rdc_gpio_set_value()
90 	spin_unlock(&gpch->lock);  in rdc_gpio_set_value()
96 	struct rdc321x_gpio *gpch;  in rdc_gpio_config()  local
100 	gpch = container_of(chip, struct rdc321x_gpio, chip);  in rdc_gpio_config()
102 	spin_lock(&gpch->lock);  in rdc_gpio_config()
103 	err = pci_read_config_dword(gpch->sb_pdev, gpio < 32 ?  in rdc_gpio_config()
104 			gpch->reg1_ctrl_base : gpch->reg2_ctrl_base, &reg);  in rdc_gpio_config()
110 	err = pci_write_config_dword(gpch->sb_pdev, gpio < 32 ?  in rdc_gpio_config()
111 			gpch->reg1_ctrl_base : gpch->reg2_ctrl_base, reg);  in rdc_gpio_config()
118 	spin_unlock(&gpch->lock);  in rdc_gpio_config()