163 void __iomem *pcic_regs;  variable
313 	pcic->pcic_regs = ioremap(regs[0].phys_addr, regs[0].reg_size);  in pcic_probe()
314 	if (!pcic->pcic_regs) {  in pcic_probe()
360 		pcic_regs = pcic->pcic_regs;  in pcic_probe()
417 	       pcic->pcic_regs+PCI_DVMA_CONTROL);  in pcic_init()
424 	writel(0xF0000000UL, pcic->pcic_regs+PCI_SIZE_0);  in pcic_init()
426 	       pcic->pcic_regs+PCI_BASE_ADDRESS_0);  in pcic_init()
553 		ivec = readw(pcic->pcic_regs+PCI_INT_SELECT_LO);  in pcic_fill_irq()
556 		ivec = readw(pcic->pcic_regs+PCI_INT_SELECT_HI);  in pcic_fill_irq()
577 			ivec = readw(pcic->pcic_regs+PCI_INT_SELECT_HI);  in pcic_fill_irq()
580 			writew(ivec, pcic->pcic_regs+PCI_INT_SELECT_HI);  in pcic_fill_irq()
582 			ivec = readw(pcic->pcic_regs+PCI_INT_SELECT_LO);  in pcic_fill_irq()
585 			writew(ivec, pcic->pcic_regs+PCI_INT_SELECT_LO);  in pcic_fill_irq()
680 		ivec = readw(pcic->pcic_regs+PCI_INT_SELECT_LO);  in pcic_pin_to_irq()
683 		ivec = readw(pcic->pcic_regs+PCI_INT_SELECT_HI);  in pcic_pin_to_irq()
698 	pcic_timer_dummy = readl(pcic0.pcic_regs+PCI_SYS_LIMIT);  in pcic_clear_clock_irq()
721 	    readl(pcic0.pcic_regs+PCI_SYS_COUNTER) & ~PCI_SYS_COUNTER_OVERFLOW;  in pci_gettimeoffset()
737 	writel (TICK_TIMER_LIMIT, pcic->pcic_regs+PCI_SYS_LIMIT);  in pci_time_init()
739 	v = readb(pcic->pcic_regs+PCI_COUNTER_IRQ);  in pci_time_init()
742 		pcic->pcic_regs+PCI_COUNTER_IRQ);  in pci_time_init()
755 	writeb(0, pcic->pcic_regs+PCI_SYS_STATUS);
812 	writel(mask, pcic0.pcic_regs+PCI_SYS_INT_TARGET_MASK_SET);  in pcic_disable_irq()
822 	writel(mask, pcic0.pcic_regs+PCI_SYS_INT_TARGET_MASK_CLEAR);  in pcic_enable_irq()
836 	writel(get_irqmask(pil), pcic0.pcic_regs+PCI_SYS_INT_TARGET_MASK_SET);  in pcic_disable_pil_irq()
841 	writel(get_irqmask(pil), pcic0.pcic_regs+PCI_SYS_INT_TARGET_MASK_CLEAR);  in pcic_enable_pil_irq()