Lines Matching refs:g2
12 sethi %hi(cheetah_fast_ecc), %g2
13 jmpl %g2 + %lo(cheetah_fast_ecc), %g0
25 sethi %hi(cheetah_fast_ecc), %g2
26 jmpl %g2 + %lo(cheetah_fast_ecc), %g0
38 sethi %hi(cheetah_cee), %g2
39 jmpl %g2 + %lo(cheetah_cee), %g0
51 sethi %hi(cheetah_cee), %g2
52 jmpl %g2 + %lo(cheetah_cee), %g0
64 sethi %hi(cheetah_deferred_trap), %g2
65 jmpl %g2 + %lo(cheetah_deferred_trap), %g0
77 sethi %hi(cheetah_deferred_trap), %g2
78 jmpl %g2 + %lo(cheetah_deferred_trap), %g0
104 rdpr %pil, %g2
146 rdpr %pil, %g2
182 mov 1, %g2 ! Setup TSTATE checking loop
184 1: wrpr %g2, %tl ! Set trap level to check
189 add %g2, 1, %g2 ! Next trap level
190 cmp %g2, %g1 ! Hit them all yet?
195 sethi %hi(dcache_parity_tl1_occurred), %g2
196 lduw [%g2 + %lo(dcache_parity_tl1_occurred)], %g1
198 stw %g1, [%g2 + %lo(dcache_parity_tl1_occurred)]
201 mov (1 << 5), %g2 ! D-cache line size
202 sub %g1, %g2, %g1 ! Move down 1 cacheline
207 sub %g2, 8, %g3 ! 64-bit data word within line
214 subcc %g1, %g2, %g1 ! Next cacheline
235 mov 1, %g2 ! Setup TSTATE checking loop
237 1: wrpr %g2, %tl ! Set trap level to check
242 add %g2, 1, %g2 ! Next trap level
243 cmp %g2, %g1 ! Hit them all yet?
248 sethi %hi(icache_parity_tl1_occurred), %g2
249 lduw [%g2 + %lo(icache_parity_tl1_occurred)], %g1
251 stw %g1, [%g2 + %lo(icache_parity_tl1_occurred)]
254 mov (1 << 5), %g2 ! I-cache line size
255 sub %g1, %g2, %g1
259 subcc %g1, %g2, %g1
282 mov (1 << 5), %g2 ! D-cache line size
283 sub %g1, %g2, %g1
286 subcc %g1, %g2, %g1
310 sllx %g1, 63, %g2
311 or %g4, %g2, %g4
314 BRANCH_IF_JALAPENO(g2,g3,50f)
315 ldxa [%g0] ASI_SAFARI_CONFIG, %g2
316 srlx %g2, 17, %g2
318 and %g2, 0x3ff, %g2
320 50: ldxa [%g0] ASI_JBUS_CONFIG, %g2
321 srlx %g2, 17, %g2
322 and %g2, 0x1f, %g2
324 60: sllx %g2, 9, %g2
330 add %g3, %g2, %g3
345 set 0x3ff8, %g2 /* DC_addr mask */
346 and %g5, %g2, %g2 /* DC_addr bits of AFAR */
350 10: ldxa [%g2] ASI_DCACHE_TAG, %g7
356 stx %g2, [%g1 + 0x20]
361 ldxa [%g2] ASI_DCACHE_UTAG, %g7
364 ldxa [%g2] ASI_DCACHE_SNOOP_TAG, %g7
368 12: ldxa [%g2 + %g3] ASI_DCACHE_DATA, %g7
379 add %g2, %g7, %g2
380 srlx %g2, 14, %g7
388 20: set 0x1fe0, %g2 /* IC_addr mask */
389 and %g5, %g2, %g2 /* IC_addr bits of AFAR */
390 sllx %g2, 1, %g2 /* IC_addr[13:6]==VA[12:5] */
394 21: ldxa [%g2] ASI_IC_TAG, %g7
401 stx %g2, [%g1 + 0x40]
403 add %g2, (1 << 3), %g2
404 ldxa [%g2] ASI_IC_TAG, %g7
405 add %g2, (1 << 3), %g2
407 ldxa [%g2] ASI_IC_TAG, %g7
408 add %g2, (1 << 3), %g2
410 ldxa [%g2] ASI_IC_TAG, %g7
412 sub %g2, (3 << 3), %g2
413 ldxa [%g2] ASI_IC_STAG, %g7
416 srlx %g2, 2, %g2
418 22: ldxa [%g2 + %g3] ASI_IC_INSTR, %g7
429 add %g2, %g7, %g2
430 srlx %g2, 14, %g7
438 30: andn %g5, (32 - 1), %g2
439 stx %g2, [%g1 + 0x20]
440 ldxa [%g2] ASI_EC_TAG_DATA, %g7
442 ldxa [%g2] ASI_EC_R, %g0
453 rdpr %tt, %g2
454 cmp %g2, 0x70
456 cmp %g2, 0x63
477 ldxa [%g0] ASI_ESTATE_ERROR_EN, %g2
478 andn %g2, ESTATE_ERROR_NCEEN | ESTATE_ERROR_CEEN, %g2
479 stxa %g2, [%g0] ASI_ESTATE_ERROR_EN
494 rdpr %pil, %g2
513 ldxa [%g0] ASI_ESTATE_ERROR_EN, %g2
514 andn %g2, ESTATE_ERROR_CEEN, %g2
515 stxa %g2, [%g0] ASI_ESTATE_ERROR_EN
530 rdpr %pil, %g2
549 ldxa [%g0] ASI_ESTATE_ERROR_EN, %g2
550 andn %g2, ESTATE_ERROR_NCEEN | ESTATE_ERROR_CEEN, %g2
551 stxa %g2, [%g0] ASI_ESTATE_ERROR_EN
566 rdpr %pil, %g2