Lines Matching refs:r21
189 movi MMUIR_FIRST, r21
192 putcfg r21, 0, ZERO /* Clear MMUIR[n].PTEH.V */
193 addi r21, MMUIR_STEP, r21
194 bne r21, r22, tr1
198 movi MMUDR_FIRST, r21
201 putcfg r21, 0, ZERO /* Clear MMUDR[n].PTEH.V */
202 addi r21, MMUDR_STEP, r21
203 bne r21, r22, tr1
206 movi MMUIR_FIRST, r21
209 putcfg r21, 1, r22 /* Set MMUIR[0].PTEL */
212 putcfg r21, 0, r22 /* Set MMUIR[0].PTEH */
215 movi MMUDR_FIRST, r21
218 putcfg r21, 1, r22 /* Set MMUDR[0].PTEL */
221 putcfg r21, 0, r22 /* Set MMUDR[0].PTEH */
226 addi r21, MMUDR_STEP, r21
229 putcfg r21, 1, r22 /* PTEL first */
232 putcfg r21, 0, r22 /* PTEH last */
238 movi ICCR_BASE, r21
241 putcfg r21, ICCR_REG0, r22
242 putcfg r21, ICCR_REG1, r23
245 movi OCCR_BASE, r21
248 putcfg r21, OCCR_REG0, r22
249 putcfg r21, OCCR_REG1, r23
257 getcon SR, r21
259 or r21, r22, r21
260 putcon r21, SSR
300 getcon SR, r21
302 and r21, r22, r22
305 xor r21, r22, r21
306 shlri r21, 15, r21 /* Supposedly 0/1 */
307 st.q r31, 0 , r21 /* Set fpu_in_use */
309 movi 0, r21
310 st.q r31, 0 , r21 /* Set fpu_in_use */
312 or r21, ZERO, r31 /* Set FPU flag at last */