Lines Matching refs:C
112 #define C(x) PERF_COUNT_HW_CACHE_##x macro
119 [ C(L1D) ] = {
120 [ C(OP_READ) ] = {
121 [ C(RESULT_ACCESS) ] = 0x0031,
122 [ C(RESULT_MISS) ] = 0x0032,
124 [ C(OP_WRITE) ] = {
125 [ C(RESULT_ACCESS) ] = 0x0039,
126 [ C(RESULT_MISS) ] = 0x003a,
128 [ C(OP_PREFETCH) ] = {
129 [ C(RESULT_ACCESS) ] = 0,
130 [ C(RESULT_MISS) ] = 0,
134 [ C(L1I) ] = {
135 [ C(OP_READ) ] = {
136 [ C(RESULT_ACCESS) ] = 0x0029,
137 [ C(RESULT_MISS) ] = 0x002a,
139 [ C(OP_WRITE) ] = {
140 [ C(RESULT_ACCESS) ] = -1,
141 [ C(RESULT_MISS) ] = -1,
143 [ C(OP_PREFETCH) ] = {
144 [ C(RESULT_ACCESS) ] = 0,
145 [ C(RESULT_MISS) ] = 0,
149 [ C(LL) ] = {
150 [ C(OP_READ) ] = {
151 [ C(RESULT_ACCESS) ] = 0x0030,
152 [ C(RESULT_MISS) ] = 0,
154 [ C(OP_WRITE) ] = {
155 [ C(RESULT_ACCESS) ] = 0x0038,
156 [ C(RESULT_MISS) ] = 0,
158 [ C(OP_PREFETCH) ] = {
159 [ C(RESULT_ACCESS) ] = 0,
160 [ C(RESULT_MISS) ] = 0,
164 [ C(DTLB) ] = {
165 [ C(OP_READ) ] = {
166 [ C(RESULT_ACCESS) ] = 0x0222,
167 [ C(RESULT_MISS) ] = 0x0220,
169 [ C(OP_WRITE) ] = {
170 [ C(RESULT_ACCESS) ] = 0,
171 [ C(RESULT_MISS) ] = 0,
173 [ C(OP_PREFETCH) ] = {
174 [ C(RESULT_ACCESS) ] = 0,
175 [ C(RESULT_MISS) ] = 0,
179 [ C(ITLB) ] = {
180 [ C(OP_READ) ] = {
181 [ C(RESULT_ACCESS) ] = 0,
182 [ C(RESULT_MISS) ] = 0x02a0,
184 [ C(OP_WRITE) ] = {
185 [ C(RESULT_ACCESS) ] = -1,
186 [ C(RESULT_MISS) ] = -1,
188 [ C(OP_PREFETCH) ] = {
189 [ C(RESULT_ACCESS) ] = -1,
190 [ C(RESULT_MISS) ] = -1,
194 [ C(BPU) ] = {
195 [ C(OP_READ) ] = {
196 [ C(RESULT_ACCESS) ] = -1,
197 [ C(RESULT_MISS) ] = -1,
199 [ C(OP_WRITE) ] = {
200 [ C(RESULT_ACCESS) ] = -1,
201 [ C(RESULT_MISS) ] = -1,
203 [ C(OP_PREFETCH) ] = {
204 [ C(RESULT_ACCESS) ] = -1,
205 [ C(RESULT_MISS) ] = -1,