Lines Matching refs:X_MASK
1673 #define X_MASK XRC (0x3f, 0x3ff, 1) macro
1679 #define XRA_MASK (X_MASK | RA_MASK)
1682 #define XRB_MASK (X_MASK | RB_MASK)
1685 #define XRT_MASK (X_MASK | RT_MASK)
1691 #define XRARB_MASK (X_MASK | RA_MASK | RB_MASK)
1697 #define XRTRA_MASK (X_MASK | RT_MASK | RA_MASK)
1706 #define XCMP_MASK (X_MASK | (((unsigned long)1) << 22))
1714 #define XTO_MASK (X_MASK | TO_MASK)
1718 #define XTLB_MASK (X_MASK | SH_MASK)
1727 #define XEH_MASK (X_MASK & ~((unsigned long )1))
1793 #define XFXFXM_MASK (X_MASK | (1 << 11) | (1 << 20))
1803 #define XSPR_MASK (X_MASK | SPR_MASK)
1934 { "attn", X(0,256), X_MASK, POWER4, { 0 } },
2030 { "mulchw", XRC(4,168,0), X_MASK, PPC405|PPC440, { RT, RA, RB } },
2031 { "mulchw.", XRC(4,168,1), X_MASK, PPC405|PPC440, { RT, RA, RB } },
2032 { "mulchwu", XRC(4,136,0), X_MASK, PPC405|PPC440, { RT, RA, RB } },
2033 { "mulchwu.", XRC(4,136,1), X_MASK, PPC405|PPC440, { RT, RA, RB } },
2034 { "mulhhw", XRC(4,40,0), X_MASK, PPC405|PPC440, { RT, RA, RB } },
2035 { "mulhhw.", XRC(4,40,1), X_MASK, PPC405|PPC440, { RT, RA, RB } },
2036 { "mulhhwu", XRC(4,8,0), X_MASK, PPC405|PPC440, { RT, RA, RB } },
2037 { "mulhhwu.", XRC(4,8,1), X_MASK, PPC405|PPC440, { RT, RA, RB } },
2038 { "mullhw", XRC(4,424,0), X_MASK, PPC405|PPC440, { RT, RA, RB } },
2039 { "mullhw.", XRC(4,424,1), X_MASK, PPC405|PPC440, { RT, RA, RB } },
2040 { "mullhwu", XRC(4,392,0), X_MASK, PPC405|PPC440, { RT, RA, RB } },
2041 { "mullhwu.", XRC(4,392,1), X_MASK, PPC405|PPC440, { RT, RA, RB } },
3352 { "tw", X(31,4), X_MASK, PPCCOM, { TO, RA, RB } },
3353 { "t", X(31,4), X_MASK, PWRCOM, { TO, RA, RB } },
3383 { "isellt", X(31,15), X_MASK, PPCISEL, { RT, RA, RB } },
3384 { "iselgt", X(31,47), X_MASK, PPCISEL, { RT, RA, RB } },
3385 { "iseleq", X(31,79), X_MASK, PPCISEL, { RT, RA, RB } },
3394 { "ldx", X(31,21), X_MASK, PPC64, { RT, RA0, RB } },
3396 { "icbt", X(31,22), X_MASK, BOOKE|PPCE300, { CT, RA, RB } },
3399 { "lwzx", X(31,23), X_MASK, PPCCOM, { RT, RA0, RB } },
3400 { "lx", X(31,23), X_MASK, PWRCOM, { RT, RA, RB } },
3402 { "slw", XRC(31,24,0), X_MASK, PPCCOM, { RA, RS, RB } },
3403 { "sl", XRC(31,24,0), X_MASK, PWRCOM, { RA, RS, RB } },
3404 { "slw.", XRC(31,24,1), X_MASK, PPCCOM, { RA, RS, RB } },
3405 { "sl.", XRC(31,24,1), X_MASK, PWRCOM, { RA, RS, RB } },
3412 { "sld", XRC(31,27,0), X_MASK, PPC64, { RA, RS, RB } },
3413 { "sld.", XRC(31,27,1), X_MASK, PPC64, { RA, RS, RB } },
3415 { "and", XRC(31,28,0), X_MASK, COM, { RA, RS, RB } },
3416 { "and.", XRC(31,28,1), X_MASK, COM, { RA, RS, RB } },
3418 { "maskg", XRC(31,29,0), X_MASK, M601, { RA, RS, RB } },
3419 { "maskg.", XRC(31,29,1), X_MASK, M601, { RA, RS, RB } },
3421 { "icbte", X(31,30), X_MASK, BOOKE64, { CT, RA, RB } },
3423 { "lwzxe", X(31,31), X_MASK, BOOKE64, { RT, RA0, RB } },
3439 { "ldux", X(31,53), X_MASK, PPC64, { RT, RAL, RB } },
3443 { "lwzux", X(31,55), X_MASK, PPCCOM, { RT, RAL, RB } },
3444 { "lux", X(31,55), X_MASK, PWRCOM, { RT, RA, RB } },
3448 { "lwzuxe", X(31,63), X_MASK, BOOKE64, { RT, RAL, RB } },
3453 { "andc", XRC(31,60,0), X_MASK, COM, { RA, RS, RB } },
3454 { "andc.", XRC(31,60,1), X_MASK, COM, { RA, RS, RB } },
3470 { "td", X(31,68), X_MASK, PPC64, { TO, RA, RB } },
3478 { "dlmzb", XRC(31,78,0), X_MASK, PPC403|PPC440, { RA, RS, RB } },
3479 { "dlmzb.", XRC(31,78,1), X_MASK, PPC403|PPC440, { RA, RS, RB } },
3490 { "lbzx", X(31,87), X_MASK, COM, { RT, RA0, RB } },
3494 { "lbzxe", X(31,95), X_MASK, BOOKE64, { RT, RA0, RB } },
3510 { "lbzux", X(31,119), X_MASK, COM, { RT, RAL, RB } },
3514 { "not", XRC(31,124,0), X_MASK, COM, { RA, RS, RBS } },
3515 { "nor", XRC(31,124,0), X_MASK, COM, { RA, RS, RB } },
3516 { "not.", XRC(31,124,1), X_MASK, COM, { RA, RS, RBS } },
3517 { "nor.", XRC(31,124,1), X_MASK, COM, { RA, RS, RB } },
3519 { "lwarxe", X(31,126), X_MASK, BOOKE64, { RT, RA0, RB } },
3521 { "lbzuxe", X(31,127), X_MASK, BOOKE64, { RT, RAL, RB } },
3525 { "dcbtstls",X(31,134), X_MASK, PPCCHLK, { CT, RA, RB }},
3545 { "dcbtstlse",X(31,142),X_MASK, PPCCHLK64, { CT, RA, RB }},
3553 { "stdx", X(31,149), X_MASK, PPC64, { RS, RA0, RB } },
3555 { "stwcx.", XRC(31,150,1), X_MASK, PPC, { RS, RA0, RB } },
3557 { "stwx", X(31,151), X_MASK, PPCCOM, { RS, RA0, RB } },
3558 { "stx", X(31,151), X_MASK, PWRCOM, { RS, RA, RB } },
3560 { "stwcxe.", XRC(31,158,1), X_MASK, BOOKE64, { RS, RA0, RB } },
3562 { "stwxe", X(31,159), X_MASK, BOOKE64, { RS, RA0, RB } },
3564 { "slq", XRC(31,152,0), X_MASK, M601, { RA, RS, RB } },
3565 { "slq.", XRC(31,152,1), X_MASK, M601, { RA, RS, RB } },
3567 { "sle", XRC(31,153,0), X_MASK, M601, { RA, RS, RB } },
3568 { "sle.", XRC(31,153,1), X_MASK, M601, { RA, RS, RB } },
3574 { "dcbtls", X(31,166), X_MASK, PPCCHLK, { CT, RA, RB }},
3575 { "dcbtlse", X(31,174), X_MASK, PPCCHLK64, { CT, RA, RB }},
3579 { "stdux", X(31,181), X_MASK, PPC64, { RS, RAS, RB } },
3581 { "stwux", X(31,183), X_MASK, PPCCOM, { RS, RAS, RB } },
3582 { "stux", X(31,183), X_MASK, PWRCOM, { RS, RA0, RB } },
3584 { "sliq", XRC(31,184,0), X_MASK, M601, { RA, RS, SH } },
3585 { "sliq.", XRC(31,184,1), X_MASK, M601, { RA, RS, SH } },
3589 { "stwuxe", X(31,191), X_MASK, BOOKE64, { RS, RAS, RB } },
3611 { "stdcx.", XRC(31,214,1), X_MASK, PPC64, { RS, RA0, RB } },
3613 { "stbx", X(31,215), X_MASK, COM, { RS, RA0, RB } },
3615 { "sllq", XRC(31,216,0), X_MASK, M601, { RA, RS, RB } },
3616 { "sllq.", XRC(31,216,1), X_MASK, M601, { RA, RS, RB } },
3618 { "sleq", XRC(31,217,0), X_MASK, M601, { RA, RS, RB } },
3619 { "sleq.", XRC(31,217,1), X_MASK, M601, { RA, RS, RB } },
3621 { "stbxe", X(31,223), X_MASK, BOOKE64, { RS, RA0, RB } },
3623 { "icblc", X(31,230), X_MASK, PPCCHLK, { CT, RA, RB }},
3657 { "icblce", X(31,238), X_MASK, PPCCHLK64, { CT, RA, RB }},
3661 { "dcbtst", X(31,246), X_MASK, PPC, { CT, RA, RB } },
3663 { "stbux", X(31,247), X_MASK, COM, { RS, RAS, RB } },
3665 { "slliq", XRC(31,248,0), X_MASK, M601, { RA, RS, SH } },
3666 { "slliq.", XRC(31,248,1), X_MASK, M601, { RA, RS, SH } },
3668 { "dcbtste", X(31,253), X_MASK, BOOKE64, { CT, RA, RB } },
3670 { "stbuxe", X(31,255), X_MASK, BOOKE64, { RS, RAS, RB } },
3672 { "mfdcrx", X(31,259), X_MASK, BOOKE, { RS, RA } },
3690 { "mfapidi", X(31,275), X_MASK, BOOKE, { RT, RA } },
3692 { "lscbx", XRC(31,277,0), X_MASK, M601, { RT, RA, RB } },
3693 { "lscbx.", XRC(31,277,1), X_MASK, M601, { RT, RA, RB } },
3695 { "dcbt", X(31,278), X_MASK, PPC, { CT, RA, RB } },
3697 { "lhzx", X(31,279), X_MASK, COM, { RT, RA0, RB } },
3699 { "eqv", XRC(31,284,0), X_MASK, COM, { RA, RS, RB } },
3700 { "eqv.", XRC(31,284,1), X_MASK, COM, { RA, RS, RB } },
3702 { "dcbte", X(31,286), X_MASK, BOOKE64, { CT, RA, RB } },
3704 { "lhzxe", X(31,287), X_MASK, BOOKE64, { RT, RA0, RB } },
3709 { "eciwx", X(31,310), X_MASK, PPC, { RT, RA, RB } },
3711 { "lhzux", X(31,311), X_MASK, COM, { RT, RAL, RB } },
3713 { "xor", XRC(31,316,0), X_MASK, COM, { RA, RS, RB } },
3714 { "xor.", XRC(31,316,1), X_MASK, COM, { RA, RS, RB } },
3716 { "lhzuxe", X(31,319), X_MASK, BOOKE64, { RT, RAL, RB } },
3752 { "mfdcr", X(31,323), X_MASK, PPC403 | BOOKE, { RT, SPR } },
3759 { "mfpmr", X(31,334), X_MASK, PPCPMR, { RT, PMR }},
3804 { "mftb", X(31,371), X_MASK, CLASSIC, { RT, TBR } },
3948 { "mfspr", X(31,339), X_MASK, COM, { RT, SPR } },
3950 { "lwax", X(31,341), X_MASK, PPC64, { RT, RA0, RB } },
3955 { "lhax", X(31,343), X_MASK, COM, { RT, RA0, RB } },
3957 { "lhaxe", X(31,351), X_MASK, BOOKE64, { RT, RA0, RB } },
3976 { "lwaux", X(31,373), X_MASK, PPC64, { RT, RAL, RB } },
3978 { "lhaux", X(31,375), X_MASK, COM, { RT, RAL, RB } },
3980 { "lhauxe", X(31,383), X_MASK, BOOKE64, { RT, RAL, RB } },
3982 { "mtdcrx", X(31,387), X_MASK, BOOKE, { RA, RS } },
3984 { "dcblc", X(31,390), X_MASK, PPCCHLK, { CT, RA, RB }},
3992 { "dcblce", X(31,398), X_MASK, PPCCHLK64, { CT, RA, RB }},
3996 { "sthx", X(31,407), X_MASK, COM, { RS, RA0, RB } },
3998 { "cmpb", X(31,508), X_MASK, POWER6, { RA, RS, RB } },
4000 { "lfqx", X(31,791), X_MASK, POWER2, { FRT, RA, RB } },
4002 { "lfdpx", X(31,791), X_MASK, POWER6, { FRT, RA, RB } },
4004 { "lfqux", X(31,823), X_MASK, POWER2, { FRT, RA, RB } },
4006 { "stfqx", X(31,919), X_MASK, POWER2, { FRS, RA, RB } },
4008 { "stfdpx", X(31,919), X_MASK, POWER6, { FRS, RA, RB } },
4010 { "stfqux", X(31,951), X_MASK, POWER2, { FRS, RA, RB } },
4012 { "orc", XRC(31,412,0), X_MASK, COM, { RA, RS, RB } },
4013 { "orc.", XRC(31,412,1), X_MASK, COM, { RA, RS, RB } },
4018 { "sthxe", X(31,415), X_MASK, BOOKE64, { RS, RA0, RB } },
4022 { "ecowx", X(31,438), X_MASK, PPC, { RT, RA, RB } },
4024 { "sthux", X(31,439), X_MASK, COM, { RS, RAS, RB } },
4026 { "sthuxe", X(31,447), X_MASK, BOOKE64, { RS, RAS, RB } },
4028 { "mr", XRC(31,444,0), X_MASK, COM, { RA, RS, RBS } },
4029 { "or", XRC(31,444,0), X_MASK, COM, { RA, RS, RB } },
4030 { "mr.", XRC(31,444,1), X_MASK, COM, { RA, RS, RBS } },
4031 { "or.", XRC(31,444,1), X_MASK, COM, { RA, RS, RB } },
4067 { "mtdcr", X(31,451), X_MASK, PPC403 | BOOKE, { SPR, RS } },
4237 { "mtspr", X(31,467), X_MASK, COM, { SPR, RS } },
4241 { "nand", XRC(31,476,0), X_MASK, COM, { RA, RS, RB } },
4242 { "nand.", XRC(31,476,1), X_MASK, COM, { RA, RS, RB } },
4246 { "dcread", X(31,486), X_MASK, PPC403|PPC440, { RT, RA, RB }},
4248 { "mtpmr", X(31,462), X_MASK, PPCPMR, { PMR, RS }},
4250 { "icbtls", X(31,486), X_MASK, PPCCHLK, { CT, RA, RB }},
4272 { "icbtlse", X(31,494), X_MASK, PPCCHLK64, { CT, RA, RB }},
4278 { "stdcxe.", XRC(31,511,1), X_MASK, BOOKE64, { RS, RA, RB } },
4282 { "bblels", X(31,518), X_MASK, PPCBRLK, { 0 }},
4287 { "ldbrx", X(31,532), X_MASK, CELL, { RT, RA0, RB } },
4289 { "lswx", X(31,533), X_MASK, PPCCOM, { RT, RA0, RB } },
4290 { "lsx", X(31,533), X_MASK, PWRCOM, { RT, RA, RB } },
4292 { "lwbrx", X(31,534), X_MASK, PPCCOM, { RT, RA0, RB } },
4293 { "lbrx", X(31,534), X_MASK, PWRCOM, { RT, RA, RB } },
4295 { "lfsx", X(31,535), X_MASK, COM, { FRT, RA0, RB } },
4297 { "srw", XRC(31,536,0), X_MASK, PPCCOM, { RA, RS, RB } },
4298 { "sr", XRC(31,536,0), X_MASK, PWRCOM, { RA, RS, RB } },
4299 { "srw.", XRC(31,536,1), X_MASK, PPCCOM, { RA, RS, RB } },
4300 { "sr.", XRC(31,536,1), X_MASK, PWRCOM, { RA, RS, RB } },
4302 { "rrib", XRC(31,537,0), X_MASK, M601, { RA, RS, RB } },
4303 { "rrib.", XRC(31,537,1), X_MASK, M601, { RA, RS, RB } },
4305 { "srd", XRC(31,539,0), X_MASK, PPC64, { RA, RS, RB } },
4306 { "srd.", XRC(31,539,1), X_MASK, PPC64, { RA, RS, RB } },
4308 { "maskir", XRC(31,541,0), X_MASK, M601, { RA, RS, RB } },
4309 { "maskir.", XRC(31,541,1), X_MASK, M601, { RA, RS, RB } },
4311 { "lwbrxe", X(31,542), X_MASK, BOOKE64, { RT, RA0, RB } },
4313 { "lfsxe", X(31,543), X_MASK, BOOKE64, { FRT, RA0, RB } },
4315 { "bbelr", X(31,550), X_MASK, PPCBRLK, { 0 }},
4319 { "lfsux", X(31,567), X_MASK, COM, { FRT, RAS, RB } },
4321 { "lfsuxe", X(31,575), X_MASK, BOOKE64, { FRT, RAS, RB } },
4325 { "lswi", X(31,597), X_MASK, PPCCOM, { RT, RA0, NB } },
4326 { "lsi", X(31,597), X_MASK, PWRCOM, { RT, RA0, NB } },
4334 { "lfdx", X(31,599), X_MASK, COM, { FRT, RA0, RB } },
4336 { "lfdxe", X(31,607), X_MASK, BOOKE64, { FRT, RA0, RB } },
4340 { "mfsri", X(31,627), X_MASK, PWRCOM, { RT, RA, RB } },
4344 { "lfdux", X(31,631), X_MASK, COM, { FRT, RAS, RB } },
4346 { "lfduxe", X(31,639), X_MASK, BOOKE64, { FRT, RAS, RB } },
4350 { "stdbrx", X(31,660), X_MASK, CELL, { RS, RA0, RB } },
4352 { "stswx", X(31,661), X_MASK, PPCCOM, { RS, RA0, RB } },
4353 { "stsx", X(31,661), X_MASK, PWRCOM, { RS, RA0, RB } },
4355 { "stwbrx", X(31,662), X_MASK, PPCCOM, { RS, RA0, RB } },
4356 { "stbrx", X(31,662), X_MASK, PWRCOM, { RS, RA0, RB } },
4358 { "stfsx", X(31,663), X_MASK, COM, { FRS, RA0, RB } },
4360 { "srq", XRC(31,664,0), X_MASK, M601, { RA, RS, RB } },
4361 { "srq.", XRC(31,664,1), X_MASK, M601, { RA, RS, RB } },
4363 { "sre", XRC(31,665,0), X_MASK, M601, { RA, RS, RB } },
4364 { "sre.", XRC(31,665,1), X_MASK, M601, { RA, RS, RB } },
4366 { "stwbrxe", X(31,670), X_MASK, BOOKE64, { RS, RA0, RB } },
4368 { "stfsxe", X(31,671), X_MASK, BOOKE64, { FRS, RA0, RB } },
4370 { "stfsux", X(31,695), X_MASK, COM, { FRS, RAS, RB } },
4372 { "sriq", XRC(31,696,0), X_MASK, M601, { RA, RS, SH } },
4373 { "sriq.", XRC(31,696,1), X_MASK, M601, { RA, RS, SH } },
4375 { "stfsuxe", X(31,703), X_MASK, BOOKE64, { FRS, RAS, RB } },
4377 { "stswi", X(31,725), X_MASK, PPCCOM, { RS, RA0, NB } },
4378 { "stsi", X(31,725), X_MASK, PWRCOM, { RS, RA0, NB } },
4380 { "stfdx", X(31,727), X_MASK, COM, { FRS, RA0, RB } },
4382 { "srlq", XRC(31,728,0), X_MASK, M601, { RA, RS, RB } },
4383 { "srlq.", XRC(31,728,1), X_MASK, M601, { RA, RS, RB } },
4385 { "sreq", XRC(31,729,0), X_MASK, M601, { RA, RS, RB } },
4386 { "sreq.", XRC(31,729,1), X_MASK, M601, { RA, RS, RB } },
4388 { "stfdxe", X(31,735), X_MASK, BOOKE64, { FRS, RA0, RB } },
4394 { "stfdux", X(31,759), X_MASK, COM, { FRS, RAS, RB } },
4396 { "srliq", XRC(31,760,0), X_MASK, M601, { RA, RS, SH } },
4397 { "srliq.", XRC(31,760,1), X_MASK, M601, { RA, RS, SH } },
4401 { "stfduxe", X(31,767), X_MASK, BOOKE64, { FRS, RAS, RB } },
4406 { "lwzcix", X(31,789), X_MASK, POWER6, { RT, RA0, RB } },
4408 { "lhbrx", X(31,790), X_MASK, COM, { RT, RA0, RB } },
4410 { "sraw", XRC(31,792,0), X_MASK, PPCCOM, { RA, RS, RB } },
4411 { "sra", XRC(31,792,0), X_MASK, PWRCOM, { RA, RS, RB } },
4412 { "sraw.", XRC(31,792,1), X_MASK, PPCCOM, { RA, RS, RB } },
4413 { "sra.", XRC(31,792,1), X_MASK, PWRCOM, { RA, RS, RB } },
4415 { "srad", XRC(31,794,0), X_MASK, PPC64, { RA, RS, RB } },
4416 { "srad.", XRC(31,794,1), X_MASK, PPC64, { RA, RS, RB } },
4418 { "lhbrxe", X(31,798), X_MASK, BOOKE64, { RT, RA0, RB } },
4420 { "ldxe", X(31,799), X_MASK, BOOKE64, { RT, RA0, RB } },
4421 { "lduxe", X(31,831), X_MASK, BOOKE64, { RT, RA0, RB } },
4423 { "rac", X(31,818), X_MASK, PWRCOM, { RT, RA, RB } },
4425 { "lhzcix", X(31,821), X_MASK, POWER6, { RT, RA0, RB } },
4430 { "srawi", XRC(31,824,0), X_MASK, PPCCOM, { RA, RS, SH } },
4431 { "srai", XRC(31,824,0), X_MASK, PWRCOM, { RA, RS, SH } },
4432 { "srawi.", XRC(31,824,1), X_MASK, PPCCOM, { RA, RS, SH } },
4433 { "srai.", XRC(31,824,1), X_MASK, PWRCOM, { RA, RS, SH } },
4437 { "lbzcix", X(31,853), X_MASK, POWER6, { RT, RA0, RB } },
4439 { "mbar", X(31,854), X_MASK, BOOKE, { MO } },
4442 { "lfiwax", X(31,855), X_MASK, POWER6, { FRT, RA0, RB } },
4444 { "ldcix", X(31,885), X_MASK, POWER6, { RT, RA0, RB } },
4446 { "tlbsx", XRC(31,914,0), X_MASK, PPC403|BOOKE, { RTO, RA, RB } },
4447 { "tlbsx.", XRC(31,914,1), X_MASK, PPC403|BOOKE, { RTO, RA, RB } },
4448 { "tlbsxe", XRC(31,915,0), X_MASK, BOOKE64, { RA, RB } },
4449 { "tlbsxe.", XRC(31,915,1), X_MASK, BOOKE64, { RA, RB } },
4453 { "stwcix", X(31,917), X_MASK, POWER6, { RS, RA0, RB } },
4455 { "sthbrx", X(31,918), X_MASK, COM, { RS, RA0, RB } },
4457 { "sraq", XRC(31,920,0), X_MASK, M601, { RA, RS, RB } },
4458 { "sraq.", XRC(31,920,1), X_MASK, M601, { RA, RS, RB } },
4460 { "srea", XRC(31,921,0), X_MASK, M601, { RA, RS, RB } },
4461 { "srea.", XRC(31,921,1), X_MASK, M601, { RA, RS, RB } },
4468 { "sthbrxe", X(31,926), X_MASK, BOOKE64, { RS, RA0, RB } },
4470 { "stdxe", X(31,927), X_MASK, BOOKE64, { RS, RA0, RB } },
4474 { "tlbre", X(31,946), X_MASK, PPC403|BOOKE, { RSO, RAOPT, SHO } },
4476 { "sthcix", X(31,949), X_MASK, POWER6, { RS, RA0, RB } },
4478 { "sraiq", XRC(31,952,0), X_MASK, M601, { RA, RS, SH } },
4479 { "sraiq.", XRC(31,952,1), X_MASK, M601, { RA, RS, SH } },
4484 { "stduxe", X(31,959), X_MASK, BOOKE64, { RS, RAS, RB } },
4490 { "tlbwe", X(31,978), X_MASK, PPC403|BOOKE, { RSO, RAOPT, SHO } },
4493 { "stbcix", X(31,981), X_MASK, POWER6, { RS, RA0, RB } },
4497 { "stfiwx", X(31,983), X_MASK, PPC, { FRS, RA0, RB } },
4505 { "stfiwxe", X(31,991), X_MASK, BOOKE64, { FRS, RA0, RB } },
4509 { "stdcix", X(31,1013), X_MASK, POWER6, { RS, RA0, RB } },
4517 { "lvebx", X(31, 7), X_MASK, PPCVEC, { VD, RA, RB } },
4518 { "lvehx", X(31, 39), X_MASK, PPCVEC, { VD, RA, RB } },
4519 { "lvewx", X(31, 71), X_MASK, PPCVEC, { VD, RA, RB } },
4520 { "lvsl", X(31, 6), X_MASK, PPCVEC, { VD, RA, RB } },
4521 { "lvsr", X(31, 38), X_MASK, PPCVEC, { VD, RA, RB } },
4522 { "lvx", X(31, 103), X_MASK, PPCVEC, { VD, RA, RB } },
4523 { "lvxl", X(31, 359), X_MASK, PPCVEC, { VD, RA, RB } },
4524 { "stvebx", X(31, 135), X_MASK, PPCVEC, { VS, RA, RB } },
4525 { "stvehx", X(31, 167), X_MASK, PPCVEC, { VS, RA, RB } },
4526 { "stvewx", X(31, 199), X_MASK, PPCVEC, { VS, RA, RB } },
4527 { "stvx", X(31, 231), X_MASK, PPCVEC, { VS, RA, RB } },
4528 { "stvxl", X(31, 487), X_MASK, PPCVEC, { VS, RA, RB } },
4531 { "lvlx", X(31, 519), X_MASK, CELL, { VD, RA0, RB } },
4532 { "lvlxl", X(31, 775), X_MASK, CELL, { VD, RA0, RB } },
4533 { "lvrx", X(31, 551), X_MASK, CELL, { VD, RA0, RB } },
4534 { "lvrxl", X(31, 807), X_MASK, CELL, { VD, RA0, RB } },
4535 { "stvlx", X(31, 647), X_MASK, CELL, { VS, RA0, RB } },
4536 { "stvlxl", X(31, 903), X_MASK, CELL, { VS, RA0, RB } },
4537 { "stvrx", X(31, 679), X_MASK, CELL, { VS, RA0, RB } },
4538 { "stvrxl", X(31, 935), X_MASK, CELL, { VS, RA0, RB } },
4623 { "dadd", XRC(59,2,0), X_MASK, POWER6, { FRT, FRA, FRB } },
4624 { "dadd.", XRC(59,2,1), X_MASK, POWER6, { FRT, FRA, FRB } },
4662 { "dmul", XRC(59,34,0), X_MASK, POWER6, { FRT, FRA, FRB } },
4663 { "dmul.", XRC(59,34,1), X_MASK, POWER6, { FRT, FRA, FRB } },
4680 { "dcmpo", X(59,130), X_MASK, POWER6, { BF, FRA, FRB } },
4682 { "dtstex", X(59,162), X_MASK, POWER6, { BF, FRA, FRB } },
4689 { "dctdp", XRC(59,258,0), X_MASK, POWER6, { FRT, FRB } },
4690 { "dctdp.", XRC(59,258,1), X_MASK, POWER6, { FRT, FRB } },
4692 { "dctfix", XRC(59,290,0), X_MASK, POWER6, { FRT, FRB } },
4693 { "dctfix.", XRC(59,290,1), X_MASK, POWER6, { FRT, FRB } },
4695 { "ddedpd", XRC(59,322,0), X_MASK, POWER6, { SP, FRT, FRB } },
4696 { "ddedpd.", XRC(59,322,1), X_MASK, POWER6, { SP, FRT, FRB } },
4698 { "dxex", XRC(59,354,0), X_MASK, POWER6, { FRT, FRB } },
4699 { "dxex.", XRC(59,354,1), X_MASK, POWER6, { FRT, FRB } },
4701 { "dsub", XRC(59,514,0), X_MASK, POWER6, { FRT, FRA, FRB } },
4702 { "dsub.", XRC(59,514,1), X_MASK, POWER6, { FRT, FRA, FRB } },
4704 { "ddiv", XRC(59,546,0), X_MASK, POWER6, { FRT, FRA, FRB } },
4705 { "ddiv.", XRC(59,546,1), X_MASK, POWER6, { FRT, FRA, FRB } },
4707 { "dcmpu", X(59,642), X_MASK, POWER6, { BF, FRA, FRB } },
4709 { "dtstsf", X(59,674), X_MASK, POWER6, { BF, FRA, FRB } },
4711 { "drsp", XRC(59,770,0), X_MASK, POWER6, { FRT, FRB } },
4712 { "drsp.", XRC(59,770,1), X_MASK, POWER6, { FRT, FRB } },
4714 { "dcffix", XRC(59,802,0), X_MASK, POWER6, { FRT, FRB } },
4715 { "dcffix.", XRC(59,802,1), X_MASK, POWER6, { FRT, FRB } },
4717 { "denbcd", XRC(59,834,0), X_MASK, POWER6, { S, FRT, FRB } },
4718 { "denbcd.", XRC(59,834,1), X_MASK, POWER6, { S, FRT, FRB } },
4720 { "diex", XRC(59,866,0), X_MASK, POWER6, { FRT, FRA, FRB } },
4721 { "diex.", XRC(59,866,1), X_MASK, POWER6, { FRT, FRA, FRB } },
4748 { "fcmpu", X(63,0), X_MASK|(3<<21), COM, { BF, FRA, FRB } },
4750 { "daddq", XRC(63,2,0), X_MASK, POWER6, { FRT, FRA, FRB } },
4751 { "daddq.", XRC(63,2,1), X_MASK, POWER6, { FRT, FRA, FRB } },
4756 { "fcpsgn", XRC(63,8,0), X_MASK, POWER6, { FRT, FRA, FRB } },
4757 { "fcpsgn.", XRC(63,8,1), X_MASK, POWER6, { FRT, FRA, FRB } },
4824 { "fcmpo", X(63,32), X_MASK|(3<<21), COM, { BF, FRA, FRB } },
4826 { "dmulq", XRC(63,34,0), X_MASK, POWER6, { FRT, FRA, FRB } },
4827 { "dmulq.", XRC(63,34,1), X_MASK, POWER6, { FRT, FRA, FRB } },
4858 { "dcmpoq", X(63,130), X_MASK, POWER6, { BF, FRA, FRB } },
4866 { "dtstexq", X(63,162), X_MASK, POWER6, { BF, FRA, FRB } },
4873 { "dctqpq", XRC(63,258,0), X_MASK, POWER6, { FRT, FRB } },
4874 { "dctqpq.", XRC(63,258,1), X_MASK, POWER6, { FRT, FRB } },
4879 { "dctfixq", XRC(63,290,0), X_MASK, POWER6, { FRT, FRB } },
4880 { "dctfixq.",XRC(63,290,1), X_MASK, POWER6, { FRT, FRB } },
4882 { "ddedpdq", XRC(63,322,0), X_MASK, POWER6, { SP, FRT, FRB } },
4883 { "ddedpdq.",XRC(63,322,1), X_MASK, POWER6, { SP, FRT, FRB } },
4885 { "dxexq", XRC(63,354,0), X_MASK, POWER6, { FRT, FRB } },
4886 { "dxexq.", XRC(63,354,1), X_MASK, POWER6, { FRT, FRB } },
4897 { "dsubq", XRC(63,514,0), X_MASK, POWER6, { FRT, FRA, FRB } },
4898 { "dsubq.", XRC(63,514,1), X_MASK, POWER6, { FRT, FRA, FRB } },
4900 { "ddivq", XRC(63,546,0), X_MASK, POWER6, { FRT, FRA, FRB } },
4901 { "ddivq.", XRC(63,546,1), X_MASK, POWER6, { FRT, FRA, FRB } },
4906 { "dcmpuq", X(63,642), X_MASK, POWER6, { BF, FRA, FRB } },
4908 { "dtstsfq", X(63,674), X_MASK, POWER6, { BF, FRA, FRB } },
4913 { "drdpq", XRC(63,770,0), X_MASK, POWER6, { FRT, FRB } },
4914 { "drdpq.", XRC(63,770,1), X_MASK, POWER6, { FRT, FRB } },
4916 { "dcffixq", XRC(63,802,0), X_MASK, POWER6, { FRT, FRB } },
4917 { "dcffixq.",XRC(63,802,1), X_MASK, POWER6, { FRT, FRB } },
4925 { "denbcdq", XRC(63,834,0), X_MASK, POWER6, { S, FRT, FRB } },
4926 { "denbcdq.",XRC(63,834,1), X_MASK, POWER6, { S, FRT, FRB } },
4931 { "diexq", XRC(63,866,0), X_MASK, POWER6, { FRT, FRA, FRB } },
4932 { "diexq.", XRC(63,866,1), X_MASK, POWER6, { FRT, FRA, FRB } },