Lines Matching refs:RA0
378 #define RA0 RA + 1 macro
383 #define RAQ RA0 + 1
2540 { "addi", OP(14), OP_MASK, PPCCOM, { RT, RA0, SI } },
2541 { "cal", OP(14), OP_MASK, PWRCOM, { RT, D, RA0 } },
2542 { "subi", OP(14), OP_MASK, PPCCOM, { RT, RA0, NSI } },
2543 { "la", OP(14), OP_MASK, PPCCOM, { RT, D, RA0 } },
2547 { "addis", OP(15), OP_MASK, PPCCOM, { RT,RA0,SISIGNOPT } },
2548 { "cau", OP(15), OP_MASK, PWRCOM, { RT,RA0,SISIGNOPT } },
2549 { "subis", OP(15), OP_MASK, PPCCOM, { RT, RA0, NSI } },
3392 { "lwarx", X(31,20), XEH_MASK, PPC, { RT, RA0, RB, EH } },
3394 { "ldx", X(31,21), X_MASK, PPC64, { RT, RA0, RB } },
3399 { "lwzx", X(31,23), X_MASK, PPCCOM, { RT, RA0, RB } },
3423 { "lwzxe", X(31,31), X_MASK, BOOKE64, { RT, RA0, RB } },
3485 { "ldarx", X(31,84), XEH_MASK, PPC64, { RT, RA0, RB, EH } },
3490 { "lbzx", X(31,87), X_MASK, COM, { RT, RA0, RB } },
3494 { "lbzxe", X(31,95), X_MASK, BOOKE64, { RT, RA0, RB } },
3519 { "lwarxe", X(31,126), X_MASK, BOOKE64, { RT, RA0, RB } },
3553 { "stdx", X(31,149), X_MASK, PPC64, { RS, RA0, RB } },
3555 { "stwcx.", XRC(31,150,1), X_MASK, PPC, { RS, RA0, RB } },
3557 { "stwx", X(31,151), X_MASK, PPCCOM, { RS, RA0, RB } },
3560 { "stwcxe.", XRC(31,158,1), X_MASK, BOOKE64, { RS, RA0, RB } },
3562 { "stwxe", X(31,159), X_MASK, BOOKE64, { RS, RA0, RB } },
3582 { "stux", X(31,183), X_MASK, PWRCOM, { RS, RA0, RB } },
3611 { "stdcx.", XRC(31,214,1), X_MASK, PPC64, { RS, RA0, RB } },
3613 { "stbx", X(31,215), X_MASK, COM, { RS, RA0, RB } },
3621 { "stbxe", X(31,223), X_MASK, BOOKE64, { RS, RA0, RB } },
3697 { "lhzx", X(31,279), X_MASK, COM, { RT, RA0, RB } },
3704 { "lhzxe", X(31,287), X_MASK, BOOKE64, { RT, RA0, RB } },
3707 { "tlbi", X(31,306), XRT_MASK, POWER, { RA0, RB } },
3950 { "lwax", X(31,341), X_MASK, PPC64, { RT, RA0, RB } },
3955 { "lhax", X(31,343), X_MASK, COM, { RT, RA0, RB } },
3957 { "lhaxe", X(31,351), X_MASK, BOOKE64, { RT, RA0, RB } },
3996 { "sthx", X(31,407), X_MASK, COM, { RS, RA0, RB } },
4018 { "sthxe", X(31,415), X_MASK, BOOKE64, { RS, RA0, RB } },
4287 { "ldbrx", X(31,532), X_MASK, CELL, { RT, RA0, RB } },
4289 { "lswx", X(31,533), X_MASK, PPCCOM, { RT, RA0, RB } },
4292 { "lwbrx", X(31,534), X_MASK, PPCCOM, { RT, RA0, RB } },
4295 { "lfsx", X(31,535), X_MASK, COM, { FRT, RA0, RB } },
4311 { "lwbrxe", X(31,542), X_MASK, BOOKE64, { RT, RA0, RB } },
4313 { "lfsxe", X(31,543), X_MASK, BOOKE64, { FRT, RA0, RB } },
4325 { "lswi", X(31,597), X_MASK, PPCCOM, { RT, RA0, NB } },
4326 { "lsi", X(31,597), X_MASK, PWRCOM, { RT, RA0, NB } },
4334 { "lfdx", X(31,599), X_MASK, COM, { FRT, RA0, RB } },
4336 { "lfdxe", X(31,607), X_MASK, BOOKE64, { FRT, RA0, RB } },
4350 { "stdbrx", X(31,660), X_MASK, CELL, { RS, RA0, RB } },
4352 { "stswx", X(31,661), X_MASK, PPCCOM, { RS, RA0, RB } },
4353 { "stsx", X(31,661), X_MASK, PWRCOM, { RS, RA0, RB } },
4355 { "stwbrx", X(31,662), X_MASK, PPCCOM, { RS, RA0, RB } },
4356 { "stbrx", X(31,662), X_MASK, PWRCOM, { RS, RA0, RB } },
4358 { "stfsx", X(31,663), X_MASK, COM, { FRS, RA0, RB } },
4366 { "stwbrxe", X(31,670), X_MASK, BOOKE64, { RS, RA0, RB } },
4368 { "stfsxe", X(31,671), X_MASK, BOOKE64, { FRS, RA0, RB } },
4377 { "stswi", X(31,725), X_MASK, PPCCOM, { RS, RA0, NB } },
4378 { "stsi", X(31,725), X_MASK, PWRCOM, { RS, RA0, NB } },
4380 { "stfdx", X(31,727), X_MASK, COM, { FRS, RA0, RB } },
4388 { "stfdxe", X(31,735), X_MASK, BOOKE64, { FRS, RA0, RB } },
4406 { "lwzcix", X(31,789), X_MASK, POWER6, { RT, RA0, RB } },
4408 { "lhbrx", X(31,790), X_MASK, COM, { RT, RA0, RB } },
4418 { "lhbrxe", X(31,798), X_MASK, BOOKE64, { RT, RA0, RB } },
4420 { "ldxe", X(31,799), X_MASK, BOOKE64, { RT, RA0, RB } },
4421 { "lduxe", X(31,831), X_MASK, BOOKE64, { RT, RA0, RB } },
4425 { "lhzcix", X(31,821), X_MASK, POWER6, { RT, RA0, RB } },
4437 { "lbzcix", X(31,853), X_MASK, POWER6, { RT, RA0, RB } },
4442 { "lfiwax", X(31,855), X_MASK, POWER6, { FRT, RA0, RB } },
4444 { "ldcix", X(31,885), X_MASK, POWER6, { RT, RA0, RB } },
4453 { "stwcix", X(31,917), X_MASK, POWER6, { RS, RA0, RB } },
4455 { "sthbrx", X(31,918), X_MASK, COM, { RS, RA0, RB } },
4468 { "sthbrxe", X(31,926), X_MASK, BOOKE64, { RS, RA0, RB } },
4470 { "stdxe", X(31,927), X_MASK, BOOKE64, { RS, RA0, RB } },
4476 { "sthcix", X(31,949), X_MASK, POWER6, { RS, RA0, RB } },
4493 { "stbcix", X(31,981), X_MASK, POWER6, { RS, RA0, RB } },
4497 { "stfiwx", X(31,983), X_MASK, PPC, { FRS, RA0, RB } },
4505 { "stfiwxe", X(31,991), X_MASK, BOOKE64, { FRS, RA0, RB } },
4509 { "stdcix", X(31,1013), X_MASK, POWER6, { RS, RA0, RB } },
4531 { "lvlx", X(31, 519), X_MASK, CELL, { VD, RA0, RB } },
4532 { "lvlxl", X(31, 775), X_MASK, CELL, { VD, RA0, RB } },
4533 { "lvrx", X(31, 551), X_MASK, CELL, { VD, RA0, RB } },
4534 { "lvrxl", X(31, 807), X_MASK, CELL, { VD, RA0, RB } },
4535 { "stvlx", X(31, 647), X_MASK, CELL, { VS, RA0, RB } },
4536 { "stvlxl", X(31, 903), X_MASK, CELL, { VS, RA0, RB } },
4537 { "stvrx", X(31, 679), X_MASK, CELL, { VS, RA0, RB } },
4538 { "stvrxl", X(31, 935), X_MASK, CELL, { VS, RA0, RB } },
4540 { "lwz", OP(32), OP_MASK, PPCCOM, { RT, D, RA0 } },
4541 { "l", OP(32), OP_MASK, PWRCOM, { RT, D, RA0 } },
4544 { "lu", OP(33), OP_MASK, PWRCOM, { RT, D, RA0 } },
4546 { "lbz", OP(34), OP_MASK, COM, { RT, D, RA0 } },
4550 { "stw", OP(36), OP_MASK, PPCCOM, { RS, D, RA0 } },
4551 { "st", OP(36), OP_MASK, PWRCOM, { RS, D, RA0 } },
4554 { "stu", OP(37), OP_MASK, PWRCOM, { RS, D, RA0 } },
4556 { "stb", OP(38), OP_MASK, COM, { RS, D, RA0 } },
4560 { "lhz", OP(40), OP_MASK, COM, { RT, D, RA0 } },
4564 { "lha", OP(42), OP_MASK, COM, { RT, D, RA0 } },
4568 { "sth", OP(44), OP_MASK, COM, { RS, D, RA0 } },
4573 { "lm", OP(46), OP_MASK, PWRCOM, { RT, D, RA0 } },
4575 { "stmw", OP(47), OP_MASK, PPCCOM, { RS, D, RA0 } },
4576 { "stm", OP(47), OP_MASK, PWRCOM, { RS, D, RA0 } },
4578 { "lfs", OP(48), OP_MASK, COM, { FRT, D, RA0 } },
4582 { "lfd", OP(50), OP_MASK, COM, { FRT, D, RA0 } },
4586 { "stfs", OP(52), OP_MASK, COM, { FRS, D, RA0 } },
4590 { "stfd", OP(54), OP_MASK, COM, { FRS, D, RA0 } },
4596 { "lfq", OP(56), OP_MASK, POWER2, { FRT, D, RA0 } },
4598 { "lfqu", OP(57), OP_MASK, POWER2, { FRT, D, RA0 } },
4600 { "lfdp", OP(57), OP_MASK, POWER6, { FRT, D, RA0 } },
4602 { "lbze", DEO(58,0), DE_MASK, BOOKE64, { RT, DE, RA0 } },
4604 { "lhze", DEO(58,2), DE_MASK, BOOKE64, { RT, DE, RA0 } },
4606 { "lhae", DEO(58,4), DE_MASK, BOOKE64, { RT, DE, RA0 } },
4608 { "lwze", DEO(58,6), DE_MASK, BOOKE64, { RT, DE, RA0 } },
4610 { "stbe", DEO(58,8), DE_MASK, BOOKE64, { RS, DE, RA0 } },
4612 { "sthe", DEO(58,10), DE_MASK, BOOKE64, { RS, DE, RA0 } },
4614 { "stwe", DEO(58,14), DE_MASK, BOOKE64, { RS, DE, RA0 } },
4617 { "ld", DSO(58,0), DS_MASK, PPC64, { RT, DS, RA0 } },
4621 { "lwa", DSO(58,2), DS_MASK, PPC64, { RT, DS, RA0 } },
4727 { "stfdp", OP(61), OP_MASK, POWER6, { FRT, D, RA0 } },
4729 { "lde", DEO(62,0), DE_MASK, BOOKE64, { RT, DES, RA0 } },
4730 { "ldue", DEO(62,1), DE_MASK, BOOKE64, { RT, DES, RA0 } },
4731 { "lfse", DEO(62,4), DE_MASK, BOOKE64, { FRT, DES, RA0 } },
4733 { "lfde", DEO(62,6), DE_MASK, BOOKE64, { FRT, DES, RA0 } },
4735 { "stde", DEO(62,8), DE_MASK, BOOKE64, { RS, DES, RA0 } },
4737 { "stfse", DEO(62,12), DE_MASK, BOOKE64, { FRS, DES, RA0 } },
4739 { "stfde", DEO(62,14), DE_MASK, BOOKE64, { FRS, DES, RA0 } },
4742 { "std", DSO(62,0), DS_MASK, PPC64, { RS, DS, RA0 } },
4746 { "stq", DSO(62,2), DS_MASK, POWER4, { RSQ, DS, RA0 } },