Lines Matching refs:PPC860
1890 #define PPC860 PPC macro
3786 { "mfcmpa", XSPR(31,339,144), XSPR_MASK, PPC860, { RT } },
3787 { "mfcmpb", XSPR(31,339,145), XSPR_MASK, PPC860, { RT } },
3788 { "mfcmpc", XSPR(31,339,146), XSPR_MASK, PPC860, { RT } },
3789 { "mfcmpd", XSPR(31,339,147), XSPR_MASK, PPC860, { RT } },
3790 { "mficr", XSPR(31,339,148), XSPR_MASK, PPC860, { RT } },
3791 { "mfder", XSPR(31,339,149), XSPR_MASK, PPC860, { RT } },
3792 { "mfcounta", XSPR(31,339,150), XSPR_MASK, PPC860, { RT } },
3793 { "mfcountb", XSPR(31,339,151), XSPR_MASK, PPC860, { RT } },
3794 { "mfcmpe", XSPR(31,339,152), XSPR_MASK, PPC860, { RT } },
3795 { "mfcmpf", XSPR(31,339,153), XSPR_MASK, PPC860, { RT } },
3796 { "mfcmpg", XSPR(31,339,154), XSPR_MASK, PPC860, { RT } },
3797 { "mfcmph", XSPR(31,339,155), XSPR_MASK, PPC860, { RT } },
3798 { "mflctrl1", XSPR(31,339,156), XSPR_MASK, PPC860, { RT } },
3799 { "mflctrl2", XSPR(31,339,157), XSPR_MASK, PPC860, { RT } },
3800 { "mfictrl", XSPR(31,339,158), XSPR_MASK, PPC860, { RT } },
3801 { "mfbar", XSPR(31,339,159), XSPR_MASK, PPC860, { RT } },
3877 { "mfic_cst", XSPR(31,339,560), XSPR_MASK, PPC860, { RT } },
3878 { "mfic_adr", XSPR(31,339,561), XSPR_MASK, PPC860, { RT } },
3879 { "mfic_dat", XSPR(31,339,562), XSPR_MASK, PPC860, { RT } },
3880 { "mfdc_cst", XSPR(31,339,568), XSPR_MASK, PPC860, { RT } },
3881 { "mfdc_adr", XSPR(31,339,569), XSPR_MASK, PPC860, { RT } },
3883 { "mfdc_dat", XSPR(31,339,570), XSPR_MASK, PPC860, { RT } },
3887 { "mfdpdr", XSPR(31,339,630), XSPR_MASK, PPC860, { RT } },
3888 { "mfdpir", XSPR(31,339,631), XSPR_MASK, PPC860, { RT } },
3889 { "mfimmr", XSPR(31,339,638), XSPR_MASK, PPC860, { RT } },
3890 { "mfmi_ctr", XSPR(31,339,784), XSPR_MASK, PPC860, { RT } },
3891 { "mfmi_ap", XSPR(31,339,786), XSPR_MASK, PPC860, { RT } },
3892 { "mfmi_epn", XSPR(31,339,787), XSPR_MASK, PPC860, { RT } },
3893 { "mfmi_twc", XSPR(31,339,789), XSPR_MASK, PPC860, { RT } },
3894 { "mfmi_rpn", XSPR(31,339,790), XSPR_MASK, PPC860, { RT } },
3895 { "mfmd_ctr", XSPR(31,339,792), XSPR_MASK, PPC860, { RT } },
3896 { "mfm_casid", XSPR(31,339,793), XSPR_MASK, PPC860, { RT } },
3897 { "mfmd_ap", XSPR(31,339,794), XSPR_MASK, PPC860, { RT } },
3898 { "mfmd_epn", XSPR(31,339,795), XSPR_MASK, PPC860, { RT } },
3899 { "mfmd_twb", XSPR(31,339,796), XSPR_MASK, PPC860, { RT } },
3900 { "mfmd_twc", XSPR(31,339,797), XSPR_MASK, PPC860, { RT } },
3901 { "mfmd_rpn", XSPR(31,339,798), XSPR_MASK, PPC860, { RT } },
3902 { "mfm_tw", XSPR(31,339,799), XSPR_MASK, PPC860, { RT } },
3903 { "mfmi_dbcam", XSPR(31,339,816), XSPR_MASK, PPC860, { RT } },
3904 { "mfmi_dbram0",XSPR(31,339,817), XSPR_MASK, PPC860, { RT } },
3905 { "mfmi_dbram1",XSPR(31,339,818), XSPR_MASK, PPC860, { RT } },
3906 { "mfmd_dbcam", XSPR(31,339,824), XSPR_MASK, PPC860, { RT } },
3907 { "mfmd_dbram0",XSPR(31,339,825), XSPR_MASK, PPC860, { RT } },
3908 { "mfmd_dbram1",XSPR(31,339,826), XSPR_MASK, PPC860, { RT } },
4110 { "mtcmpa", XSPR(31,467,144), XSPR_MASK, PPC860, { RS } },
4111 { "mtcmpb", XSPR(31,467,145), XSPR_MASK, PPC860, { RS } },
4112 { "mtcmpc", XSPR(31,467,146), XSPR_MASK, PPC860, { RS } },
4113 { "mtcmpd", XSPR(31,467,147), XSPR_MASK, PPC860, { RS } },
4114 { "mticr", XSPR(31,467,148), XSPR_MASK, PPC860, { RS } },
4115 { "mtder", XSPR(31,467,149), XSPR_MASK, PPC860, { RS } },
4116 { "mtcounta", XSPR(31,467,150), XSPR_MASK, PPC860, { RS } },
4117 { "mtcountb", XSPR(31,467,151), XSPR_MASK, PPC860, { RS } },
4118 { "mtcmpe", XSPR(31,467,152), XSPR_MASK, PPC860, { RS } },
4119 { "mtcmpf", XSPR(31,467,153), XSPR_MASK, PPC860, { RS } },
4120 { "mtcmpg", XSPR(31,467,154), XSPR_MASK, PPC860, { RS } },
4121 { "mtcmph", XSPR(31,467,155), XSPR_MASK, PPC860, { RS } },
4122 { "mtlctrl1", XSPR(31,467,156), XSPR_MASK, PPC860, { RS } },
4123 { "mtlctrl2", XSPR(31,467,157), XSPR_MASK, PPC860, { RS } },
4124 { "mtictrl", XSPR(31,467,158), XSPR_MASK, PPC860, { RS } },
4125 { "mtbar", XSPR(31,467,159), XSPR_MASK, PPC860, { RS } },