26 static u8 *bridge_base;  variable
53 	mv64x60_config_ctlr_windows(bridge_base, bridge_pbase, is_coherent);  in c2k_bridge_setup()
58 	enables = in_le32((u32 *)(bridge_base + MV64x60_CPU_BAR_ENABLE));  in c2k_bridge_setup()
60 	out_le32((u32 *)(bridge_base + MV64x60_CPU_BAR_ENABLE), enables);  in c2k_bridge_setup()
77 		mv64x60_config_pci_windows(bridge_base, bridge_pbase, bus, 0,  in c2k_bridge_setup()
111 			mv64x60_config_cpu2pci_window(bridge_base, bus,  in c2k_bridge_setup()
117 		out_le32((u32 *)(bridge_base + MV64x60_CPU_BAR_ENABLE),  in c2k_bridge_setup()
126 	mem_size = mv64x60_get_mem_size(bridge_base);  in c2k_fixups()
142 	if (bridge_base != 0) {  in c2k_reset()
143 		temp = in_le32((u32 *)(bridge_base + MV64x60_MPP_CNTL_0));  in c2k_reset()
145 		out_le32((u32 *)(bridge_base + MV64x60_MPP_CNTL_0), temp);  in c2k_reset()
147 		temp = in_le32((u32 *)(bridge_base + MV64x60_GPP_LEVEL_CNTL));  in c2k_reset()
149 		out_le32((u32 *)(bridge_base + MV64x60_GPP_LEVEL_CNTL), temp);  in c2k_reset()
151 		temp = in_le32((u32 *)(bridge_base + MV64x60_GPP_IO_CNTL));  in c2k_reset()
153 		out_le32((u32 *)(bridge_base + MV64x60_GPP_IO_CNTL), temp);  in c2k_reset()
155 		temp = in_le32((u32 *)(bridge_base + MV64x60_MPP_CNTL_2));  in c2k_reset()
157 		out_le32((u32 *)(bridge_base + MV64x60_MPP_CNTL_2), temp);  in c2k_reset()
159 		temp = in_le32((u32 *)(bridge_base + MV64x60_GPP_LEVEL_CNTL));  in c2k_reset()
161 		out_le32((u32 *)(bridge_base + MV64x60_GPP_LEVEL_CNTL), temp);  in c2k_reset()
163 		temp = in_le32((u32 *)(bridge_base + MV64x60_GPP_IO_CNTL));  in c2k_reset()
165 		out_le32((u32 *)(bridge_base + MV64x60_GPP_IO_CNTL), temp);  in c2k_reset()
167 		out_le32((u32 *)(bridge_base + MV64x60_GPP_VALUE_SET),  in c2k_reset()
183 	bridge_base = mv64x60_get_bridge_base();  in platform_init()