Lines Matching refs:ctl_status_2
377 union cvmx_pci_ctl_status_2 ctl_status_2; in octeon_pci_initialize() local
401 ctl_status_2.u32 = 0; in octeon_pci_initialize()
402 ctl_status_2.s.tsr_hwm = 1; /* Initializes to 0. Must be set in octeon_pci_initialize()
404 ctl_status_2.s.bar2pres = 1; /* Enable BAR2 */ in octeon_pci_initialize()
405 ctl_status_2.s.bar2_enb = 1; in octeon_pci_initialize()
406 ctl_status_2.s.bar2_cax = 1; /* Don't use L2 */ in octeon_pci_initialize()
407 ctl_status_2.s.bar2_esx = 1; in octeon_pci_initialize()
408 ctl_status_2.s.pmo_amod = 1; /* Round robin priority */ in octeon_pci_initialize()
411 ctl_status_2.s.bb1_hole = OCTEON_PCI_BAR1_HOLE_BITS; in octeon_pci_initialize()
412 ctl_status_2.s.bb1_siz = 1; /* BAR1 is 2GB */ in octeon_pci_initialize()
413 ctl_status_2.s.bb_ca = 1; /* Don't use L2 with big bars */ in octeon_pci_initialize()
414 ctl_status_2.s.bb_es = 1; /* Big bar in byte swap mode */ in octeon_pci_initialize()
415 ctl_status_2.s.bb1 = 1; /* BAR1 is big */ in octeon_pci_initialize()
416 ctl_status_2.s.bb0 = 1; /* BAR0 is big */ in octeon_pci_initialize()
419 octeon_npi_write32(CVMX_NPI_PCI_CTL_STATUS_2, ctl_status_2.u32); in octeon_pci_initialize()
422 ctl_status_2.u32 = octeon_npi_read32(CVMX_NPI_PCI_CTL_STATUS_2); in octeon_pci_initialize()
424 ctl_status_2.s.ap_pcix ? "PCI-X" : "PCI", in octeon_pci_initialize()
425 ctl_status_2.s.ap_64ad ? "64" : "32"); in octeon_pci_initialize()
450 if (ctl_status_2.s.ap_pcix) { in octeon_pci_initialize()