Lines Matching refs:C
285 [C(L1D)] = {
292 [C(OP_READ)] = {
293 [C(RESULT_ACCESS)] = { 0x0a, CNTR_EVEN, T },
294 [C(RESULT_MISS)] = { 0x0b, CNTR_EVEN | CNTR_ODD, T },
296 [C(OP_WRITE)] = {
297 [C(RESULT_ACCESS)] = { 0x0a, CNTR_EVEN, T },
298 [C(RESULT_MISS)] = { 0x0b, CNTR_EVEN | CNTR_ODD, T },
300 [C(OP_PREFETCH)] = {
301 [C(RESULT_ACCESS)] = { UNSUPPORTED_PERF_EVENT_ID },
302 [C(RESULT_MISS)] = { UNSUPPORTED_PERF_EVENT_ID },
305 [C(L1I)] = {
306 [C(OP_READ)] = {
307 [C(RESULT_ACCESS)] = { 0x09, CNTR_EVEN, T },
308 [C(RESULT_MISS)] = { 0x09, CNTR_ODD, T },
310 [C(OP_WRITE)] = {
311 [C(RESULT_ACCESS)] = { 0x09, CNTR_EVEN, T },
312 [C(RESULT_MISS)] = { 0x09, CNTR_ODD, T },
314 [C(OP_PREFETCH)] = {
315 [C(RESULT_ACCESS)] = { 0x14, CNTR_EVEN, T },
320 [C(RESULT_MISS)] = { UNSUPPORTED_PERF_EVENT_ID },
323 [C(LL)] = {
324 [C(OP_READ)] = {
325 [C(RESULT_ACCESS)] = { 0x15, CNTR_ODD, P },
326 [C(RESULT_MISS)] = { 0x16, CNTR_EVEN, P },
328 [C(OP_WRITE)] = {
329 [C(RESULT_ACCESS)] = { 0x15, CNTR_ODD, P },
330 [C(RESULT_MISS)] = { 0x16, CNTR_EVEN, P },
332 [C(OP_PREFETCH)] = {
333 [C(RESULT_ACCESS)] = { UNSUPPORTED_PERF_EVENT_ID },
334 [C(RESULT_MISS)] = { UNSUPPORTED_PERF_EVENT_ID },
337 [C(DTLB)] = {
338 [C(OP_READ)] = {
339 [C(RESULT_ACCESS)] = { 0x06, CNTR_EVEN, T },
340 [C(RESULT_MISS)] = { 0x06, CNTR_ODD, T },
342 [C(OP_WRITE)] = {
343 [C(RESULT_ACCESS)] = { 0x06, CNTR_EVEN, T },
344 [C(RESULT_MISS)] = { 0x06, CNTR_ODD, T },
346 [C(OP_PREFETCH)] = {
347 [C(RESULT_ACCESS)] = { UNSUPPORTED_PERF_EVENT_ID },
348 [C(RESULT_MISS)] = { UNSUPPORTED_PERF_EVENT_ID },
351 [C(ITLB)] = {
352 [C(OP_READ)] = {
353 [C(RESULT_ACCESS)] = { 0x05, CNTR_EVEN, T },
354 [C(RESULT_MISS)] = { 0x05, CNTR_ODD, T },
356 [C(OP_WRITE)] = {
357 [C(RESULT_ACCESS)] = { 0x05, CNTR_EVEN, T },
358 [C(RESULT_MISS)] = { 0x05, CNTR_ODD, T },
360 [C(OP_PREFETCH)] = {
361 [C(RESULT_ACCESS)] = { UNSUPPORTED_PERF_EVENT_ID },
362 [C(RESULT_MISS)] = { UNSUPPORTED_PERF_EVENT_ID },
365 [C(BPU)] = {
367 [C(OP_READ)] = {
368 [C(RESULT_ACCESS)] = { 0x02, CNTR_EVEN, T },
369 [C(RESULT_MISS)] = { 0x02, CNTR_ODD, T },
371 [C(OP_WRITE)] = {
372 [C(RESULT_ACCESS)] = { 0x02, CNTR_EVEN, T },
373 [C(RESULT_MISS)] = { 0x02, CNTR_ODD, T },
375 [C(OP_PREFETCH)] = {
376 [C(RESULT_ACCESS)] = { UNSUPPORTED_PERF_EVENT_ID },
377 [C(RESULT_MISS)] = { UNSUPPORTED_PERF_EVENT_ID },
387 [C(L1D)] = {
394 [C(OP_READ)] = {
395 [C(RESULT_ACCESS)] = { 0x17, CNTR_ODD, T },
396 [C(RESULT_MISS)] = { 0x18, CNTR_ODD, T },
398 [C(OP_WRITE)] = {
399 [C(RESULT_ACCESS)] = { 0x17, CNTR_ODD, T },
400 [C(RESULT_MISS)] = { 0x18, CNTR_ODD, T },
402 [C(OP_PREFETCH)] = {
403 [C(RESULT_ACCESS)] = { UNSUPPORTED_PERF_EVENT_ID },
404 [C(RESULT_MISS)] = { UNSUPPORTED_PERF_EVENT_ID },
407 [C(L1I)] = {
408 [C(OP_READ)] = {
409 [C(RESULT_ACCESS)] = { 0x06, CNTR_EVEN, T },
410 [C(RESULT_MISS)] = { 0x06, CNTR_ODD, T },
412 [C(OP_WRITE)] = {
413 [C(RESULT_ACCESS)] = { 0x06, CNTR_EVEN, T },
414 [C(RESULT_MISS)] = { 0x06, CNTR_ODD, T },
416 [C(OP_PREFETCH)] = {
417 [C(RESULT_ACCESS)] = { 0x34, CNTR_EVEN, T },
422 [C(RESULT_MISS)] = { UNSUPPORTED_PERF_EVENT_ID },
425 [C(LL)] = {
426 [C(OP_READ)] = {
427 [C(RESULT_ACCESS)] = { 0x1c, CNTR_ODD, P },
428 [C(RESULT_MISS)] = { 0x1d, CNTR_EVEN | CNTR_ODD, P },
430 [C(OP_WRITE)] = {
431 [C(RESULT_ACCESS)] = { 0x1c, CNTR_ODD, P },
432 [C(RESULT_MISS)] = { 0x1d, CNTR_EVEN | CNTR_ODD, P },
434 [C(OP_PREFETCH)] = {
435 [C(RESULT_ACCESS)] = { UNSUPPORTED_PERF_EVENT_ID },
436 [C(RESULT_MISS)] = { UNSUPPORTED_PERF_EVENT_ID },
439 [C(DTLB)] = {
441 [C(OP_READ)] = {
442 [C(RESULT_ACCESS)] = { UNSUPPORTED_PERF_EVENT_ID },
443 [C(RESULT_MISS)] = { UNSUPPORTED_PERF_EVENT_ID },
445 [C(OP_WRITE)] = {
446 [C(RESULT_ACCESS)] = { UNSUPPORTED_PERF_EVENT_ID },
447 [C(RESULT_MISS)] = { UNSUPPORTED_PERF_EVENT_ID },
449 [C(OP_PREFETCH)] = {
450 [C(RESULT_ACCESS)] = { UNSUPPORTED_PERF_EVENT_ID },
451 [C(RESULT_MISS)] = { UNSUPPORTED_PERF_EVENT_ID },
454 [C(ITLB)] = {
455 [C(OP_READ)] = {
456 [C(RESULT_ACCESS)] = { 0x04, CNTR_EVEN, T },
457 [C(RESULT_MISS)] = { 0x04, CNTR_ODD, T },
459 [C(OP_WRITE)] = {
460 [C(RESULT_ACCESS)] = { 0x04, CNTR_EVEN, T },
461 [C(RESULT_MISS)] = { 0x04, CNTR_ODD, T },
463 [C(OP_PREFETCH)] = {
464 [C(RESULT_ACCESS)] = { UNSUPPORTED_PERF_EVENT_ID },
465 [C(RESULT_MISS)] = { UNSUPPORTED_PERF_EVENT_ID },
468 [C(BPU)] = {
470 [C(OP_READ)] = {
471 [C(RESULT_ACCESS)] = { 0x27, CNTR_EVEN, T },
472 [C(RESULT_MISS)] = { 0x27, CNTR_ODD, T },
474 [C(OP_WRITE)] = {
475 [C(RESULT_ACCESS)] = { 0x27, CNTR_EVEN, T },
476 [C(RESULT_MISS)] = { 0x27, CNTR_ODD, T },
478 [C(OP_PREFETCH)] = {
479 [C(RESULT_ACCESS)] = { UNSUPPORTED_PERF_EVENT_ID },
480 [C(RESULT_MISS)] = { UNSUPPORTED_PERF_EVENT_ID },