Lines Matching refs:jz_clk_reg_read
120 static uint32_t jz_clk_reg_read(int reg) in jz_clk_reg_read() function
182 return !(jz_clk_reg_read(JZ_REG_CLOCK_GATE) & clk->gate_bit); in jz_clk_is_enabled_gating()
204 return !!(jz_clk_reg_read(JZ_REG_CLOCK_CTRL) & JZ_CLOCK_CTRL_KO_ENABLE); in jz_clk_ko_is_enabled()
216 val = jz_clk_reg_read(JZ_REG_CLOCK_PLL); in jz_clk_pll_get_rate()
232 reg = jz_clk_reg_read(JZ_REG_CLOCK_CTRL); in jz_clk_pll_half_get_rate()
261 div = jz_clk_reg_read(JZ_REG_CLOCK_CTRL); in jz_clk_main_get_rate()
429 return !!(jz_clk_reg_read(JZ_REG_CLOCK_SLEEP_CTRL) & in jz_clk_udc_is_enabled()
473 div = (jz_clk_reg_read(JZ_REG_CLOCK_CTRL) & JZ_CLOCK_CTRL_UDIV_MASK); in jz_clk_udc_get_rate()
488 div = (jz_clk_reg_read(dclk->reg) & dclk->mask) + 1; in jz_clk_divided_get_rate()
553 div = jz_clk_reg_read(JZ_REG_CLOCK_CTRL) & JZ_CLOCK_CTRL_LDIV_MASK; in jz_clk_ldclk_get_rate()
885 pll = jz_clk_reg_read(JZ_REG_CLOCK_PLL); in jz4740_clock_resume()
905 val = jz_clk_reg_read(JZ_REG_CLOCK_SPI); in jz4740_clock_init()
910 val = jz_clk_reg_read(JZ_REG_CLOCK_CTRL); in jz4740_clock_init()