Lines Matching refs:jz_clk_pll_half
322 static struct clk jz_clk_pll_half = { variable
399 if (parent == &jz_clk_pll_half) in jz_clk_i2s_set_parent()
435 if (parent == &jz_clk_pll_half) in jz_clk_udc_set_parent()
571 .parent = &jz_clk_pll_half,
625 .parent = &jz_clk_pll_half,
635 .parent = &jz_clk_pll_half,
645 .parent = &jz_clk_pll_half,
831 clk_add(&jz_clk_pll_half); in clk_register_clks()
908 jz4740_clock_divided_clks[1].clk.parent = &jz_clk_pll_half; in jz4740_clock_init()
913 jz4740_clock_divided_clks[0].clk.parent = &jz_clk_pll_half; in jz4740_clock_init()
916 jz4740_clock_simple_clks[0].parent = &jz_clk_pll_half; in jz4740_clock_init()