Lines Matching refs:jz_clk_ext

300 static struct static_clk jz_clk_ext = {  variable
314 	.parent = &jz_clk_ext.clk,
387 	else if (parent == &jz_clk_ext.clk)  in jz_clk_spi_set_parent()
401 	else if (parent == &jz_clk_ext.clk)  in jz_clk_i2s_set_parent()
437 	else if (parent == &jz_clk_ext.clk)  in jz_clk_udc_set_parent()
451 	if (clk->parent == &jz_clk_ext.clk)  in jz_clk_udc_set_rate()
470 	if (clk->parent == &jz_clk_ext.clk)  in jz_clk_udc_get_rate()
485 	if (clk->parent == &jz_clk_ext.clk)  in jz_clk_divided_get_rate()
498 	if (clk->parent == &jz_clk_ext.clk)  in jz_clk_divided_set_rate()
605 			.parent = &jz_clk_ext.clk,
615 			.parent = &jz_clk_ext.clk,
672 		.parent = &jz_clk_ext.clk,
677 		.parent = &jz_clk_ext.clk,
683 		.parent = &jz_clk_ext.clk,
701 		.parent = &jz_clk_ext.clk,
707 		.parent = &jz_clk_ext.clk,
713 		.parent = &jz_clk_ext.clk,
829 	clk_add(&jz_clk_ext.clk);  in clk_register_clks()
902 	jz_clk_ext.rate = jz4740_clock_bdata.ext_rate;  in jz4740_clock_init()