Lines Matching refs:IRQ_INTERNAL_BASE
464 #define BCM_6338_TIMER_IRQ (IRQ_INTERNAL_BASE + 0)
465 #define BCM_6338_SPI_IRQ (IRQ_INTERNAL_BASE + 1)
466 #define BCM_6338_UART0_IRQ (IRQ_INTERNAL_BASE + 2)
467 #define BCM_6338_DG_IRQ (IRQ_INTERNAL_BASE + 4)
468 #define BCM_6338_DSL_IRQ (IRQ_INTERNAL_BASE + 5)
469 #define BCM_6338_ATM_IRQ (IRQ_INTERNAL_BASE + 6)
470 #define BCM_6338_UDC0_IRQ (IRQ_INTERNAL_BASE + 7)
471 #define BCM_6338_ENET0_IRQ (IRQ_INTERNAL_BASE + 8)
472 #define BCM_6338_ENET_PHY_IRQ (IRQ_INTERNAL_BASE + 9)
473 #define BCM_6338_SDRAM_IRQ (IRQ_INTERNAL_BASE + 10)
474 #define BCM_6338_USB_CNTL_RX_DMA_IRQ (IRQ_INTERNAL_BASE + 11)
475 #define BCM_6338_USB_CNTL_TX_DMA_IRQ (IRQ_INTERNAL_BASE + 12)
476 #define BCM_6338_USB_BULK_RX_DMA_IRQ (IRQ_INTERNAL_BASE + 13)
477 #define BCM_6338_USB_BULK_TX_DMA_IRQ (IRQ_INTERNAL_BASE + 14)
478 #define BCM_6338_ENET0_RXDMA_IRQ (IRQ_INTERNAL_BASE + 15)
479 #define BCM_6338_ENET0_TXDMA_IRQ (IRQ_INTERNAL_BASE + 16)
480 #define BCM_6338_SDIO_IRQ (IRQ_INTERNAL_BASE + 17)
485 #define BCM_6345_TIMER_IRQ (IRQ_INTERNAL_BASE + 0)
486 #define BCM_6345_UART0_IRQ (IRQ_INTERNAL_BASE + 2)
487 #define BCM_6345_DSL_IRQ (IRQ_INTERNAL_BASE + 3)
488 #define BCM_6345_ATM_IRQ (IRQ_INTERNAL_BASE + 4)
489 #define BCM_6345_USB_IRQ (IRQ_INTERNAL_BASE + 5)
490 #define BCM_6345_ENET0_IRQ (IRQ_INTERNAL_BASE + 8)
491 #define BCM_6345_ENET_PHY_IRQ (IRQ_INTERNAL_BASE + 12)
492 #define BCM_6345_ENET0_RXDMA_IRQ (IRQ_INTERNAL_BASE + 13 + 1)
493 #define BCM_6345_ENET0_TXDMA_IRQ (IRQ_INTERNAL_BASE + 13 + 2)
494 #define BCM_6345_EBI_RX_IRQ (IRQ_INTERNAL_BASE + 13 + 5)
495 #define BCM_6345_EBI_TX_IRQ (IRQ_INTERNAL_BASE + 13 + 6)
496 #define BCM_6345_RESERVED_RX_IRQ (IRQ_INTERNAL_BASE + 13 + 9)
497 #define BCM_6345_RESERVED_TX_IRQ (IRQ_INTERNAL_BASE + 13 + 10)
498 #define BCM_6345_USB_BULK_RX_DMA_IRQ (IRQ_INTERNAL_BASE + 13 + 13)
499 #define BCM_6345_USB_BULK_TX_DMA_IRQ (IRQ_INTERNAL_BASE + 13 + 14)
500 #define BCM_6345_USB_CNTL_RX_DMA_IRQ (IRQ_INTERNAL_BASE + 13 + 15)
501 #define BCM_6345_USB_CNTL_TX_DMA_IRQ (IRQ_INTERNAL_BASE + 13 + 16)
502 #define BCM_6345_USB_ISO_RX_DMA_IRQ (IRQ_INTERNAL_BASE + 13 + 17)
503 #define BCM_6345_USB_ISO_TX_DMA_IRQ (IRQ_INTERNAL_BASE + 13 + 18)
508 #define BCM_6348_TIMER_IRQ (IRQ_INTERNAL_BASE + 0)
509 #define BCM_6348_UART0_IRQ (IRQ_INTERNAL_BASE + 2)
510 #define BCM_6348_DSL_IRQ (IRQ_INTERNAL_BASE + 4)
511 #define BCM_6348_ENET1_IRQ (IRQ_INTERNAL_BASE + 7)
512 #define BCM_6348_ENET0_IRQ (IRQ_INTERNAL_BASE + 8)
513 #define BCM_6348_ENET_PHY_IRQ (IRQ_INTERNAL_BASE + 9)
514 #define BCM_6348_OHCI0_IRQ (IRQ_INTERNAL_BASE + 12)
515 #define BCM_6348_ENET0_RXDMA_IRQ (IRQ_INTERNAL_BASE + 20)
516 #define BCM_6348_ENET0_TXDMA_IRQ (IRQ_INTERNAL_BASE + 21)
517 #define BCM_6348_ENET1_RXDMA_IRQ (IRQ_INTERNAL_BASE + 22)
518 #define BCM_6348_ENET1_TXDMA_IRQ (IRQ_INTERNAL_BASE + 23)
519 #define BCM_6348_PCMCIA_IRQ (IRQ_INTERNAL_BASE + 24)
520 #define BCM_6348_PCI_IRQ (IRQ_INTERNAL_BASE + 24)
525 #define BCM_6358_TIMER_IRQ (IRQ_INTERNAL_BASE + 0)
526 #define BCM_6358_UART0_IRQ (IRQ_INTERNAL_BASE + 2)
527 #define BCM_6358_UART1_IRQ (IRQ_INTERNAL_BASE + 3)
528 #define BCM_6358_OHCI0_IRQ (IRQ_INTERNAL_BASE + 5)
529 #define BCM_6358_ENET1_IRQ (IRQ_INTERNAL_BASE + 6)
530 #define BCM_6358_ENET0_IRQ (IRQ_INTERNAL_BASE + 8)
531 #define BCM_6358_ENET_PHY_IRQ (IRQ_INTERNAL_BASE + 9)
532 #define BCM_6358_EHCI0_IRQ (IRQ_INTERNAL_BASE + 10)
533 #define BCM_6358_ENET0_RXDMA_IRQ (IRQ_INTERNAL_BASE + 15)
534 #define BCM_6358_ENET0_TXDMA_IRQ (IRQ_INTERNAL_BASE + 16)
535 #define BCM_6358_ENET1_RXDMA_IRQ (IRQ_INTERNAL_BASE + 17)
536 #define BCM_6358_ENET1_TXDMA_IRQ (IRQ_INTERNAL_BASE + 18)
537 #define BCM_6358_DSL_IRQ (IRQ_INTERNAL_BASE + 29)
538 #define BCM_6358_PCI_IRQ (IRQ_INTERNAL_BASE + 31)
539 #define BCM_6358_PCMCIA_IRQ (IRQ_INTERNAL_BASE + 24)