Lines Matching refs:bootcr
173 u32 *bootcr, u32 bus_clock) in tnetd7300_get_clock() argument
184 switch ((*bootcr & (BOOT_PLL_SOURCE_MASK << shift)) >> shift) { in tnetd7300_get_clock()
199 if (*bootcr & BOOT_PLL_BYPASS) in tnetd7300_get_clock()
219 u32 *bootcr, u32 frequency) in tnetd7300_set_clock() argument
224 switch ((*bootcr & (BOOT_PLL_SOURCE_MASK << shift)) >> shift) { in tnetd7300_set_clock()
252 u32 *bootcr = (u32 *)ioremap_nocache(AR7_REGS_DCL, 4); in tnetd7300_init_clocks() local
258 &clocks->bus, bootcr, AR7_AFE_CLOCK); in tnetd7300_init_clocks()
260 if (*bootcr & BOOT_PLL_ASYNC_MODE) in tnetd7300_init_clocks()
262 &clocks->cpu, bootcr, AR7_AFE_CLOCK); in tnetd7300_init_clocks()
268 bootcr, dsp_clk.rate); in tnetd7300_init_clocks()
271 iounmap(bootcr); in tnetd7300_init_clocks()
308 static int tnetd7200_get_clock_base(int clock_id, u32 *bootcr) in tnetd7200_get_clock_base() argument
310 if (*bootcr & BOOT_PLL_ASYNC_MODE) in tnetd7200_get_clock_base()
320 if (*bootcr & BOOT_PLL_2TO1_MODE) in tnetd7200_get_clock_base()
336 u32 *bootcr = (u32 *)ioremap_nocache(AR7_REGS_DCL, 4); in tnetd7200_init_clocks() local
344 cpu_base = tnetd7200_get_clock_base(TNETD7200_CLOCK_ID_CPU, bootcr); in tnetd7200_init_clocks()
345 dsp_base = tnetd7200_get_clock_base(TNETD7200_CLOCK_ID_DSP, bootcr); in tnetd7200_init_clocks()
347 if (*bootcr & BOOT_PLL_ASYNC_MODE) { in tnetd7200_init_clocks()
369 if (*bootcr & BOOT_PLL_2TO1_MODE) { in tnetd7200_init_clocks()
414 iounmap(bootcr); in tnetd7200_init_clocks()