118 extern struct dma_channel dma_ch[MAX_DMA_CHANNELS];
124 	dma_ch[channel].regs->start_addr = addr;  in set_dma_start_addr()
128 	dma_ch[channel].regs->next_desc_ptr = addr;  in set_dma_next_desc_addr()
132 	dma_ch[channel].regs->curr_desc_ptr = addr;  in set_dma_curr_desc_addr()
136 	dma_ch[channel].regs->x_count = x_count;  in set_dma_x_count()
140 	dma_ch[channel].regs->y_count = y_count;  in set_dma_y_count()
144 	dma_ch[channel].regs->x_modify = x_modify;  in set_dma_x_modify()
148 	dma_ch[channel].regs->y_modify = y_modify;  in set_dma_y_modify()
152 	dma_ch[channel].regs->cfg = config;  in set_dma_config()
156 	dma_ch[channel].regs->curr_addr_ptr = addr;  in set_dma_curr_addr()
169 	return dma_ch[channel].regs->irq_status;  in get_dma_curr_irqstat()
173 	return dma_ch[channel].regs->curr_x_count;  in get_dma_curr_xcount()
177 	return dma_ch[channel].regs->curr_y_count;  in get_dma_curr_ycount()
181 	return dma_ch[channel].regs->next_desc_ptr;  in get_dma_next_desc_ptr()
185 	return dma_ch[channel].regs->curr_desc_ptr;  in get_dma_curr_desc_ptr()
189 	return dma_ch[channel].regs->cfg;  in get_dma_config()
193 	return dma_ch[channel].regs->curr_addr_ptr;  in get_dma_curr_addr()
204 	dma_ch[channel].regs->next_desc_ptr = sg;  in set_dma_sg()
205 	dma_ch[channel].regs->cfg =  in set_dma_sg()
206 		(dma_ch[channel].regs->cfg & ~(0xf << 8)) |  in set_dma_sg()
212 	return atomic_read(&dma_ch[channel].chan_status);  in dma_channel_active()
217 	dma_ch[channel].regs->cfg &= ~DMAEN;  in disable_dma()
222 	dma_ch[channel].regs->curr_x_count = 0;  in enable_dma()
223 	dma_ch[channel].regs->curr_y_count = 0;  in enable_dma()
224 	dma_ch[channel].regs->cfg |= DMAEN;  in enable_dma()
230 	disable_irq(dma_ch[channel].irq);  in dma_disable_irq()
234 	disable_irq_nosync(dma_ch[channel].irq);  in dma_disable_irq_nosync()
238 	enable_irq(dma_ch[channel].irq);  in dma_enable_irq()
242 	dma_ch[channel].regs->irq_status = DMA_DONE | DMA_ERR;  in clear_dma_irqstat()