Lines Matching refs:S3C2443_DMAREQSEL_SRC
121 #define S3C2443_DMAREQSEL_SRC(x) ((x)<<1) macro
125 #define S3C2443_DMAREQSEL_SPI0TX S3C2443_DMAREQSEL_SRC(0)
126 #define S3C2443_DMAREQSEL_SPI0RX S3C2443_DMAREQSEL_SRC(1)
127 #define S3C2443_DMAREQSEL_SPI1TX S3C2443_DMAREQSEL_SRC(2)
128 #define S3C2443_DMAREQSEL_SPI1RX S3C2443_DMAREQSEL_SRC(3)
129 #define S3C2443_DMAREQSEL_I2STX S3C2443_DMAREQSEL_SRC(4)
130 #define S3C2443_DMAREQSEL_I2SRX S3C2443_DMAREQSEL_SRC(5)
131 #define S3C2443_DMAREQSEL_TIMER S3C2443_DMAREQSEL_SRC(9)
132 #define S3C2443_DMAREQSEL_SDI S3C2443_DMAREQSEL_SRC(10)
133 #define S3C2443_DMAREQSEL_XDREQ0 S3C2443_DMAREQSEL_SRC(17)
134 #define S3C2443_DMAREQSEL_XDREQ1 S3C2443_DMAREQSEL_SRC(18)
135 #define S3C2443_DMAREQSEL_UART0_0 S3C2443_DMAREQSEL_SRC(19)
136 #define S3C2443_DMAREQSEL_UART0_1 S3C2443_DMAREQSEL_SRC(20)
137 #define S3C2443_DMAREQSEL_UART1_0 S3C2443_DMAREQSEL_SRC(21)
138 #define S3C2443_DMAREQSEL_UART1_1 S3C2443_DMAREQSEL_SRC(22)
139 #define S3C2443_DMAREQSEL_UART2_0 S3C2443_DMAREQSEL_SRC(23)
140 #define S3C2443_DMAREQSEL_UART2_1 S3C2443_DMAREQSEL_SRC(24)
141 #define S3C2443_DMAREQSEL_UART3_0 S3C2443_DMAREQSEL_SRC(25)
142 #define S3C2443_DMAREQSEL_UART3_1 S3C2443_DMAREQSEL_SRC(26)
143 #define S3C2443_DMAREQSEL_PCMOUT S3C2443_DMAREQSEL_SRC(27)
144 #define S3C2443_DMAREQSEL_PCMIN S3C2443_DMAREQSEL_SRC(28)
145 #define S3C2443_DMAREQSEL_MICIN S3C2443_DMAREQSEL_SRC(29)