Lines Matching refs:APB_DMA_CHAN_CSR
45 #define APB_DMA_CHAN_CSR 0x000 macro
165 csr = readl(ch->addr + APB_DMA_CHAN_CSR); in tegra_dma_stop()
167 writel(csr, ch->addr + APB_DMA_CHAN_CSR); in tegra_dma_stop()
170 writel(csr, ch->addr + APB_DMA_CHAN_CSR); in tegra_dma_stop()
186 csr = readl(ch->addr + APB_DMA_CHAN_CSR); in tegra_dma_cancel()
189 writel(csr, ch->addr + APB_DMA_CHAN_CSR); in tegra_dma_cancel()
230 csr = readl(ch->addr + APB_DMA_CHAN_CSR); in tegra_dma_dequeue_req()
233 writel(csr, ch->addr + APB_DMA_CHAN_CSR); in tegra_dma_dequeue_req()
506 writel(csr, ch->addr + APB_DMA_CHAN_CSR); in tegra_dma_update_hw()
513 writel(csr, ch->addr + APB_DMA_CHAN_CSR); in tegra_dma_update_hw()
763 *ctx++ = readl(addr + APB_DMA_CHAN_CSR); in tegra_dma_suspend()
785 writel(*ctx++, addr + APB_DMA_CHAN_CSR); in tegra_dma_resume()