Lines Matching refs:S3C64XX_GPIOREG
16 #define S3C64XX_GPIOREG(reg) (S3C64XX_VA_GPIO + (reg)) macro
18 #define S3C64XX_GPA_BASE S3C64XX_GPIOREG(0x0000)
19 #define S3C64XX_GPB_BASE S3C64XX_GPIOREG(0x0020)
20 #define S3C64XX_GPC_BASE S3C64XX_GPIOREG(0x0040)
21 #define S3C64XX_GPD_BASE S3C64XX_GPIOREG(0x0060)
22 #define S3C64XX_GPE_BASE S3C64XX_GPIOREG(0x0080)
23 #define S3C64XX_GPF_BASE S3C64XX_GPIOREG(0x00A0)
24 #define S3C64XX_GPG_BASE S3C64XX_GPIOREG(0x00C0)
25 #define S3C64XX_GPH_BASE S3C64XX_GPIOREG(0x00E0)
26 #define S3C64XX_GPI_BASE S3C64XX_GPIOREG(0x0100)
27 #define S3C64XX_GPJ_BASE S3C64XX_GPIOREG(0x0120)
28 #define S3C64XX_GPK_BASE S3C64XX_GPIOREG(0x0800)
29 #define S3C64XX_GPL_BASE S3C64XX_GPIOREG(0x0810)
30 #define S3C64XX_GPM_BASE S3C64XX_GPIOREG(0x0820)
31 #define S3C64XX_GPN_BASE S3C64XX_GPIOREG(0x0830)
32 #define S3C64XX_GPO_BASE S3C64XX_GPIOREG(0x0140)
33 #define S3C64XX_GPP_BASE S3C64XX_GPIOREG(0x0160)
34 #define S3C64XX_GPQ_BASE S3C64XX_GPIOREG(0x0180)
38 #define S3C64XX_SPCON S3C64XX_GPIOREG(0x1A0)
123 #define S3C64XX_EINT12CON S3C64XX_GPIOREG(0x200)
124 #define S3C64XX_EINT34CON S3C64XX_GPIOREG(0x204)
125 #define S3C64XX_EINT56CON S3C64XX_GPIOREG(0x208)
126 #define S3C64XX_EINT78CON S3C64XX_GPIOREG(0x20C)
127 #define S3C64XX_EINT9CON S3C64XX_GPIOREG(0x210)
129 #define S3C64XX_EINT12FLTCON S3C64XX_GPIOREG(0x220)
130 #define S3C64XX_EINT34FLTCON S3C64XX_GPIOREG(0x224)
131 #define S3C64XX_EINT56FLTCON S3C64XX_GPIOREG(0x228)
132 #define S3C64XX_EINT78FLTCON S3C64XX_GPIOREG(0x22C)
133 #define S3C64XX_EINT9FLTCON S3C64XX_GPIOREG(0x230)
135 #define S3C64XX_EINT12MASK S3C64XX_GPIOREG(0x240)
136 #define S3C64XX_EINT34MASK S3C64XX_GPIOREG(0x244)
137 #define S3C64XX_EINT56MASK S3C64XX_GPIOREG(0x248)
138 #define S3C64XX_EINT78MASK S3C64XX_GPIOREG(0x24C)
139 #define S3C64XX_EINT9MASK S3C64XX_GPIOREG(0x250)
141 #define S3C64XX_EINT12PEND S3C64XX_GPIOREG(0x260)
142 #define S3C64XX_EINT34PEND S3C64XX_GPIOREG(0x264)
143 #define S3C64XX_EINT56PEND S3C64XX_GPIOREG(0x268)
144 #define S3C64XX_EINT78PEND S3C64XX_GPIOREG(0x26C)
145 #define S3C64XX_EINT9PEND S3C64XX_GPIOREG(0x270)
147 #define S3C64XX_PRIORITY S3C64XX_GPIOREG(0x280)
150 #define S3C64XX_SERVICE S3C64XX_GPIOREG(0x284)
151 #define S3C64XX_SERVICEPEND S3C64XX_GPIOREG(0x288)
153 #define S3C64XX_EINT0CON0 S3C64XX_GPIOREG(0x900)
154 #define S3C64XX_EINT0CON1 S3C64XX_GPIOREG(0x904)
155 #define S3C64XX_EINT0FLTCON0 S3C64XX_GPIOREG(0x910)
156 #define S3C64XX_EINT0FLTCON1 S3C64XX_GPIOREG(0x914)
157 #define S3C64XX_EINT0FLTCON2 S3C64XX_GPIOREG(0x918)
158 #define S3C64XX_EINT0FLTCON3 S3C64XX_GPIOREG(0x91C)
160 #define S3C64XX_EINT0MASK S3C64XX_GPIOREG(0x920)
161 #define S3C64XX_EINT0PEND S3C64XX_GPIOREG(0x924)
165 #define S3C64XX_SPCONSLP S3C64XX_GPIOREG(0x880)
181 #define S3C64XX_SLPEN S3C64XX_GPIOREG(0x930)