Lines Matching refs:ref_xtal_clk
79 static struct clk ref_xtal_clk = { variable
146 .parent = &ref_xtal_clk, \
227 if (clk->parent == &ref_xtal_clk) \
301 if (clk->parent == &ref_xtal_clk) { \
544 .parent = &ref_xtal_clk,
554 .parent = &ref_xtal_clk,
586 _DEFINE_CLOCK(emi_clk, EMI, CLKGATE, &ref_xtal_clk);
587 _DEFINE_CLOCK(ssp0_clk, SSP0, CLKGATE, &ref_xtal_clk);
588 _DEFINE_CLOCK(ssp1_clk, SSP1, CLKGATE, &ref_xtal_clk);
589 _DEFINE_CLOCK(ssp2_clk, SSP2, CLKGATE, &ref_xtal_clk);
590 _DEFINE_CLOCK(ssp3_clk, SSP3, CLKGATE, &ref_xtal_clk);
591 _DEFINE_CLOCK(lcdif_clk, DIS_LCDIF, CLKGATE, &ref_xtal_clk);
592 _DEFINE_CLOCK(gpmi_clk, GPMI, CLKGATE, &ref_xtal_clk);
593 _DEFINE_CLOCK(saif0_clk, SAIF0, CLKGATE, &ref_xtal_clk);
594 _DEFINE_CLOCK(saif1_clk, SAIF1, CLKGATE, &ref_xtal_clk);
595 _DEFINE_CLOCK(can0_clk, FLEXCAN, STOP_CAN0, &ref_xtal_clk);
596 _DEFINE_CLOCK(can1_clk, FLEXCAN, STOP_CAN1, &ref_xtal_clk);
597 _DEFINE_CLOCK(pwm_clk, XTAL, PWM_CLK24M_GATE, &ref_xtal_clk);
598 _DEFINE_CLOCK(uart_clk, XTAL, UART_CLK_GATE, &ref_xtal_clk);
599 _DEFINE_CLOCK(clk32k_clk, XTAL, TIMROT_CLK32K_GATE, &ref_xtal_clk);
653 &ref_xtal_clk : &ref_cpu_clk; in clk_misc_init()
655 &ref_xtal_clk : &ref_emi_clk; in clk_misc_init()
657 &ref_xtal_clk : &ref_io0_clk; in clk_misc_init()
659 &ref_xtal_clk : &ref_io0_clk; in clk_misc_init()
661 &ref_xtal_clk : &ref_io1_clk; in clk_misc_init()
663 &ref_xtal_clk : &ref_io1_clk; in clk_misc_init()
665 &ref_xtal_clk : &ref_pix_clk; in clk_misc_init()
667 &ref_xtal_clk : &ref_gpmi_clk; in clk_misc_init()
669 &ref_xtal_clk : &pll0_clk; in clk_misc_init()
671 &ref_xtal_clk : &pll0_clk; in clk_misc_init()