Lines Matching refs:CCM_PCCR0
42 #define CCM_PCCR0 IO_ADDR_CCM(0x20) macro
130 #define CCM_PCCR_HCLK_CSI_REG CCM_PCCR0
132 #define CCM_PCCR_HCLK_DMA_REG CCM_PCCR0
134 #define CCM_PCCR_HCLK_BROM_REG CCM_PCCR0
136 #define CCM_PCCR_HCLK_EMMA_REG CCM_PCCR0
138 #define CCM_PCCR_HCLK_LCDC_REG CCM_PCCR0
140 #define CCM_PCCR_HCLK_SLCDC_REG CCM_PCCR0
142 #define CCM_PCCR_HCLK_USBOTG_REG CCM_PCCR0
145 #define CCM_PCCR_HCLK_BMI_REG CCM_PCCR0
147 #define CCM_PCCR_PERCLK4_REG CCM_PCCR0
149 #define CCM_PCCR_SLCDC_REG CCM_PCCR0
152 #define CCM_PCCR_FIRI_BAUD_REG CCM_PCCR0
154 #define CCM_PCCR_NFC_REG CCM_PCCR0
156 #define CCM_PCCR_LCDC_REG CCM_PCCR0
158 #define CCM_PCCR_SSI1_BAUD_REG CCM_PCCR0
160 #define CCM_PCCR_SSI2_BAUD_REG CCM_PCCR0
162 #define CCM_PCCR_EMMA_REG CCM_PCCR0
164 #define CCM_PCCR_USBOTG_REG CCM_PCCR0
166 #define CCM_PCCR_DMA_REG CCM_PCCR0
168 #define CCM_PCCR_I2C1_REG CCM_PCCR0
170 #define CCM_PCCR_GPIO_REG CCM_PCCR0
172 #define CCM_PCCR_SDHC2_REG CCM_PCCR0
174 #define CCM_PCCR_SDHC1_REG CCM_PCCR0
177 #define CCM_PCCR_FIRI_REG CCM_PCCR0
179 #define CCM_PCCR_SSI2_REG CCM_PCCR0
181 #define CCM_PCCR_SSI1_REG CCM_PCCR0
183 #define CCM_PCCR_CSPI2_REG CCM_PCCR0
185 #define CCM_PCCR_CSPI1_REG CCM_PCCR0
187 #define CCM_PCCR_UART4_REG CCM_PCCR0
189 #define CCM_PCCR_UART3_REG CCM_PCCR0
191 #define CCM_PCCR_UART2_REG CCM_PCCR0
193 #define CCM_PCCR_UART1_REG CCM_PCCR0
1222 __raw_writel(0, CCM_PCCR0); in mx21_clocks_init()