Lines Matching refs:p_init
282 (SET_DMA_CIE_ENABLE(p_init->int_enable) | /* interrupt enable */ \
283 SET_DMA_BEN(p_init->buffer_enable) | /* buffer enable */\
284 SET_DMA_ETD(p_init->etd_output) | /* end of transfer pin */ \
285 SET_DMA_TCE(p_init->tce_enable) | /* terminal count enable */ \
286 SET_DMA_PL(p_init->pl) | /* peripheral location */ \
287 SET_DMA_DAI(p_init->dai) | /* dest addr increment */ \
288 SET_DMA_SAI(p_init->sai) | /* src addr increment */ \
289 SET_DMA_PRIORITY(p_init->cp) | /* channel priority */ \
290 SET_DMA_PW(p_init->pwidth) | /* peripheral/bus width */ \
291 SET_DMA_PSC(p_init->psc) | /* peripheral setup cycles */ \
292 SET_DMA_PWC(p_init->pwc) | /* peripheral wait cycles */ \
293 SET_DMA_PHC(p_init->phc) | /* peripheral hold cycles */ \
294 SET_DMA_PREFETCH(p_init->pf) /* read prefetch */)
388 (SET_DMA_CIE_ENABLE(p_init->int_enable) | /* interrupt enable */ \
389 SET_DMA_ETD(p_init->etd_output) | /* end of transfer pin */ \
390 SET_DMA_TCE(p_init->tce_enable) | /* terminal count enable */ \
391 SET_DMA_PL(p_init->pl) | /* peripheral location */ \
392 SET_DMA_DAI(p_init->dai) | /* dest addr increment */ \
393 SET_DMA_SAI(p_init->sai) | /* src addr increment */ \
394 SET_DMA_PRIORITY(p_init->cp) | /* channel priority */ \
395 SET_DMA_PW(p_init->pwidth) | /* peripheral/bus width */ \
396 SET_DMA_PSC(p_init->psc) | /* peripheral setup cycles */ \
397 SET_DMA_PWC(p_init->pwc) | /* peripheral wait cycles */ \
398 SET_DMA_PHC(p_init->phc) | /* peripheral hold cycles */ \
399 SET_DMA_TCD(p_init->tcd_disable) | /* TC chain mode disable */ \
400 SET_DMA_ECE(p_init->ece_enable) | /* ECE chanin mode enable */ \
401 SET_DMA_CH(p_init->ch_enable) | /* Chain enable */ \