Lines Matching defs:immap

570 typedef struct immap {  struct
575 	u8		im_dpram1[16*1024];
576 	u8		res1[16*1024];
577 	u8		im_dpram2[4*1024];
578 	u8		res2[8*1024];
579 	u8		im_dpram3[4*1024];
580 	u8		res3[16*1024];
582 	sysconf_cpm2_t	im_siu_conf;	/* SIU Configuration */
583 	memctl_cpm2_t	im_memctl;	/* Memory Controller */
584 	sit_cpm2_t	im_sit;		/* System Integration Timers */
585 	pci_cpm2_t	im_pci;		/* PCI Controller */
586 	intctl_cpm2_t	im_intctl;	/* Interrupt Controller */
587 	car_cpm2_t	im_clkrst;	/* Clocks and reset */
588 	iop_cpm2_t	im_ioport;	/* IO Port control/status */
589 	cpmtimer_cpm2_t	im_cpmtimer;	/* CPM timers */
590 	sdma_cpm2_t	im_sdma;	/* SDMA control/status */
592 	fcc_t		im_fcc[3];	/* Three FCCs */
593 	u8		res4z[32];
594 	fcc_c_t		im_fcc_c[3];	/* Continued FCCs */
596 	u8		res4[32];
598 	tclayer_t	im_tclayer[8];	/* Eight TCLayers */
599 	u16		tc_tcgsr;
600 	u16		tc_tcger;
604 	u8		res[236];
605 	u32		im_brgc5;
606 	u32		im_brgc6;
607 	u32		im_brgc7;
608 	u32		im_brgc8;
610 	u8		res5[608];
612 	i2c_cpm2_t	im_i2c;		/* I2C control/status */
613 	cpm_cpm2_t	im_cpm;		/* Communication processor */
617 	u32		im_brgc1;
618 	u32		im_brgc2;
619 	u32		im_brgc3;
620 	u32		im_brgc4;
622 	scc_t		im_scc[4];	/* Four SCCs */
623 	smc_t		im_smc[2];	/* Couple of SMCs */
624 	spictl_cpm2_t	im_spi;		/* A SPI */
625 	cpmux_t		im_cpmux;	/* CPM clock route mux */
626 	siramctl_t	im_siramctl1;	/* First SI RAM Control */
627 	mcc_t		im_mcc1;	/* First MCC */
628 	siramctl_t	im_siramctl2;	/* Second SI RAM Control */
629 	mcc_t		im_mcc2;	/* Second MCC */
630 	usb_cpm2_t	im_usb;		/* USB Controller */
632 	u8		res6[1153];
634 	u16		im_si1txram[256];
635 	u8		res7[512];
636 	u16		im_si1rxram[256];
637 	u8		res8[512];
638 	u16		im_si2txram[256];
639 	u8		res9[512];
640 	u16		im_si2rxram[256];
641 	u8		res10[512];
642 	u8		res11[4096];