Lines Matching refs:_SB_MAKEMASK1
172 #define M_SYS_LDT_PLL_BYP _SB_MAKEMASK1(3)
173 #define M_SYS_PCI_SYNC_TEST_MODE _SB_MAKEMASK1(4)
174 #define M_SYS_IOB0_DIV _SB_MAKEMASK1(5)
175 #define M_SYS_IOB1_DIV _SB_MAKEMASK1(6)
182 #define M_SYS_SER0_ENABLE _SB_MAKEMASK1(12)
183 #define M_SYS_SER0_RSTB_EN _SB_MAKEMASK1(13)
184 #define M_SYS_SER1_ENABLE _SB_MAKEMASK1(14)
185 #define M_SYS_SER1_RSTB_EN _SB_MAKEMASK1(15)
186 #define M_SYS_PCMCIA_ENABLE _SB_MAKEMASK1(16)
197 #define M_SYS_PCI_HOST _SB_MAKEMASK1(19)
198 #define M_SYS_PCI_ARBITER _SB_MAKEMASK1(20)
199 #define M_SYS_SOUTH_ON_LDT _SB_MAKEMASK1(21)
200 #define M_SYS_BIG_ENDIAN _SB_MAKEMASK1(22)
201 #define M_SYS_GENCLK_EN _SB_MAKEMASK1(23)
202 #define M_SYS_LDT_TEST_EN _SB_MAKEMASK1(24)
203 #define M_SYS_GEN_PARITY_EN _SB_MAKEMASK1(25)
212 #define M_SYS_CLKSTOP _SB_MAKEMASK1(32)
213 #define M_SYS_CLKSTEP _SB_MAKEMASK1(33)
220 #define M_SYS_PLL_BYPASS _SB_MAKEMASK1(42)
231 #define M_SYS_MEM_RESET _SB_MAKEMASK1(49)
232 #define M_SYS_L2C_RESET _SB_MAKEMASK1(50)
233 #define M_SYS_IO_RESET_0 _SB_MAKEMASK1(51)
234 #define M_SYS_IO_RESET_1 _SB_MAKEMASK1(52)
235 #define M_SYS_SCD_RESET _SB_MAKEMASK1(53)
239 #define M_SYS_CPU_RESET_0 _SB_MAKEMASK1(54)
240 #define M_SYS_CPU_RESET_1 _SB_MAKEMASK1(55)
242 #define M_SYS_UNICPU0 _SB_MAKEMASK1(56)
243 #define M_SYS_UNICPU1 _SB_MAKEMASK1(57)
245 #define M_SYS_SB_SOFTRES _SB_MAKEMASK1(58)
246 #define M_SYS_EXT_RESET _SB_MAKEMASK1(59)
247 #define M_SYS_SYSTEM_RESET _SB_MAKEMASK1(60)
249 #define M_SYS_MISR_MODE _SB_MAKEMASK1(61)
250 #define M_SYS_MISR_RESET _SB_MAKEMASK1(62)
253 #define M_SYS_SW_FLAG _SB_MAKEMASK1(63)
285 #define M_SCD_WDOG_ENABLE _SB_MAKEMASK1(S_SCD_WDOG_ENABLE)
301 #define M_SCD_WDOG_HAS_RESET _SB_MAKEMASK1(S_SCD_WDOG_HAS_RESET)
321 #define M_SCD_TIMER_ENABLE _SB_MAKEMASK1(0)
322 #define M_SCD_TIMER_MODE _SB_MAKEMASK1(1)
349 #define M_SPC_CFG_CLEAR _SB_MAKEMASK1(32)
350 #define M_SPC_CFG_ENABLE _SB_MAKEMASK1(33)
372 #define M_SCD_BERR_MULTERRS _SB_MAKEMASK1(30)
423 #define M_ATRAP_CFG_WRITE _SB_MAKEMASK1(3)
424 #define M_ATRAP_CFG_ALL _SB_MAKEMASK1(4)
425 #define M_ATRAP_CFG_INV _SB_MAKEMASK1(5)
426 #define M_ATRAP_CFG_USESRC _SB_MAKEMASK1(6)
427 #define M_ATRAP_CFG_SRCINV _SB_MAKEMASK1(7)
461 #define M_SCD_TRACE_CFG_RESET _SB_MAKEMASK1(0)
462 #define M_SCD_TRACE_CFG_START_READ _SB_MAKEMASK1(1)
463 #define M_SCD_TRACE_CFG_START _SB_MAKEMASK1(2)
464 #define M_SCD_TRACE_CFG_STOP _SB_MAKEMASK1(3)
465 #define M_SCD_TRACE_CFG_FREEZE _SB_MAKEMASK1(4)
466 #define M_SCD_TRACE_CFG_FREEZE_FULL _SB_MAKEMASK1(5)
467 #define M_SCD_TRACE_CFG_DEBUG_FULL _SB_MAKEMASK1(6)
468 #define M_SCD_TRACE_CFG_FULL _SB_MAKEMASK1(7)
470 #define M_SCD_TRACE_CFG_FORCECNT _SB_MAKEMASK1(8)
487 #define M_SCD_TREVT_REQID_MATCH _SB_MAKEMASK1(4)
488 #define M_SCD_TREVT_DATAID_MATCH _SB_MAKEMASK1(5)
489 #define M_SCD_TREVT_RESPID_MATCH _SB_MAKEMASK1(6)
490 #define M_SCD_TREVT_INTERRUPT _SB_MAKEMASK1(7)
491 #define M_SCD_TREVT_DEBUG_PIN _SB_MAKEMASK1(9)
492 #define M_SCD_TREVT_WRITE _SB_MAKEMASK1(10)
493 #define M_SCD_TREVT_READ _SB_MAKEMASK1(11)
576 #define M_SCD_TRSEQ_ASAMPLE _SB_MAKEMASK1(18)
577 #define M_SCD_TRSEQ_DSAMPLE _SB_MAKEMASK1(19)
578 #define M_SCD_TRSEQ_DEBUGPIN _SB_MAKEMASK1(20)
579 #define M_SCD_TRSEQ_DEBUGCPU _SB_MAKEMASK1(21)
580 #define M_SCD_TRSEQ_CLEARUSE _SB_MAKEMASK1(22)