Lines Matching refs:IO_DMA2_BASE
73 #define IO_DMA2_BASE 0x10D00 /* 16 bit master DMA, ch 4(=slave input)..7 */ macro
87 #define DMA2_CMD_REG (IO_DMA2_BASE+0x10) /* command register (w) */
88 #define DMA2_STAT_REG (IO_DMA2_BASE+0x10) /* status register (r) */
89 #define DMA2_REQ_REG (IO_DMA2_BASE+0x12) /* request register (w) */
90 #define DMA2_MASK_REG (IO_DMA2_BASE+0x14) /* single-channel mask (w) */
91 #define DMA2_MODE_REG (IO_DMA2_BASE+0x16) /* mode register (w) */
92 #define DMA2_CLEAR_FF_REG (IO_DMA2_BASE+0x18) /* clear pointer flip-flop (w) */
93 #define DMA2_TEMP_REG (IO_DMA2_BASE+0x1A) /* Temporary Register (r) */
94 #define DMA2_RESET_REG (IO_DMA2_BASE+0x1A) /* Master Clear (w) */
95 #define DMA2_CLR_MASK_REG (IO_DMA2_BASE+0x1C) /* Clear Mask */
96 #define DMA2_MASK_ALL_REG (IO_DMA2_BASE+0x1E) /* all-channels mask (w) */
102 #define DMA_ADDR_4 (IO_DMA2_BASE+0x00)
103 #define DMA_ADDR_5 (IO_DMA2_BASE+0x04)
104 #define DMA_ADDR_6 (IO_DMA2_BASE+0x08)
105 #define DMA_ADDR_7 (IO_DMA2_BASE+0x0C)
111 #define DMA_CNT_4 (IO_DMA2_BASE+0x02)
112 #define DMA_CNT_5 (IO_DMA2_BASE+0x06)
113 #define DMA_CNT_6 (IO_DMA2_BASE+0x0A)
114 #define DMA_CNT_7 (IO_DMA2_BASE+0x0E)
190 dma_outb( (a>>1) & 0xff, ((dmanr&3)<<2) + IO_DMA2_BASE ); in set_dma_addr()
191 dma_outb( (a>>9) & 0xff, ((dmanr&3)<<2) + IO_DMA2_BASE ); in set_dma_addr()
211 dma_outb( (count>>1) & 0xff, ((dmanr&3)<<2) + 2 + IO_DMA2_BASE ); in set_dma_count()
212 dma_outb( (count>>9) & 0xff, ((dmanr&3)<<2) + 2 + IO_DMA2_BASE ); in set_dma_count()
228 : ((dmanr&3)<<2) + 2 + IO_DMA2_BASE; in get_dma_residue()