Lines Matching refs:IO_DMA1_BASE
72 #define IO_DMA1_BASE 0x10C00 /* 8 bit slave DMA, channels 0..3 */ macro
76 #define DMA1_CMD_REG (IO_DMA1_BASE+0x08) /* command register (w) */
77 #define DMA1_STAT_REG (IO_DMA1_BASE+0x08) /* status register (r) */
78 #define DMA1_REQ_REG (IO_DMA1_BASE+0x09) /* request register (w) */
79 #define DMA1_MASK_REG (IO_DMA1_BASE+0x0A) /* single-channel mask (w) */
80 #define DMA1_MODE_REG (IO_DMA1_BASE+0x0B) /* mode register (w) */
81 #define DMA1_CLEAR_FF_REG (IO_DMA1_BASE+0x0C) /* clear pointer flip-flop (w) */
82 #define DMA1_TEMP_REG (IO_DMA1_BASE+0x0D) /* Temporary Register (r) */
83 #define DMA1_RESET_REG (IO_DMA1_BASE+0x0D) /* Master Clear (w) */
84 #define DMA1_CLR_MASK_REG (IO_DMA1_BASE+0x0E) /* Clear Mask */
85 #define DMA1_MASK_ALL_REG (IO_DMA1_BASE+0x0F) /* all-channels mask (w) */
98 #define DMA_ADDR_0 (IO_DMA1_BASE+0x00) /* DMA address registers */
99 #define DMA_ADDR_1 (IO_DMA1_BASE+0x02)
100 #define DMA_ADDR_2 (IO_DMA1_BASE+0x04)
101 #define DMA_ADDR_3 (IO_DMA1_BASE+0x06)
107 #define DMA_CNT_0 (IO_DMA1_BASE+0x01) /* DMA count registers */
108 #define DMA_CNT_1 (IO_DMA1_BASE+0x03)
109 #define DMA_CNT_2 (IO_DMA1_BASE+0x05)
110 #define DMA_CNT_3 (IO_DMA1_BASE+0x07)
187 dma_outb( a & 0xff, ((dmanr&3)<<1) + IO_DMA1_BASE ); in set_dma_addr()
188 dma_outb( (a>>8) & 0xff, ((dmanr&3)<<1) + IO_DMA1_BASE ); in set_dma_addr()
208 dma_outb( count & 0xff, ((dmanr&3)<<1) + 1 + IO_DMA1_BASE ); in set_dma_count()
209 dma_outb( (count>>8) & 0xff, ((dmanr&3)<<1) + 1 + IO_DMA1_BASE ); in set_dma_count()
227 unsigned int io_port = (dmanr<=3)? ((dmanr&3)<<1) + 1 + IO_DMA1_BASE in get_dma_residue()