Lines Matching refs:mmr_t

24 	mmr_t	sh_fsb_binit_control_regval;
26 		mmr_t	binit       : 1;
27 		mmr_t	reserved_0  : 63;
32 	mmr_t	sh_fsb_binit_control_regval;
34 		mmr_t	reserved_0  : 63;
35 		mmr_t	binit       : 1;
47 	mmr_t	sh_fsb_reset_control_regval;
49 		mmr_t	reset       : 1;
50 		mmr_t	reserved_0  : 63;
55 	mmr_t	sh_fsb_reset_control_regval;
57 		mmr_t	reserved_0  : 63;
58 		mmr_t	reset       : 1;
70 	mmr_t	sh_fsb_system_agent_config_regval;
72 		mmr_t	rcnt_scnt_en        : 1;
73 		mmr_t	reserved_0          : 2;
74 		mmr_t	berr_assert_en      : 1;
75 		mmr_t	berr_sampling_en    : 1;
76 		mmr_t	binit_assert_en     : 1;
77 		mmr_t	bnr_throttling_en   : 1;
78 		mmr_t	short_hang_en       : 1;
79 		mmr_t	inta_rsp_data       : 8;
80 		mmr_t	io_trans_rsp        : 1;
81 		mmr_t	xtpr_trans_rsp      : 1;
82 		mmr_t	inta_trans_rsp      : 1;
83 		mmr_t	reserved_1          : 4;
84 		mmr_t	tdot                : 1;
85 		mmr_t	serialize_fsb_en    : 1;
86 		mmr_t	reserved_2          : 7;
87 		mmr_t	binit_event_enables : 14;
88 		mmr_t	reserved_3          : 18;
93 	mmr_t	sh_fsb_system_agent_config_regval;
95 		mmr_t	reserved_3          : 18;
96 		mmr_t	binit_event_enables : 14;
97 		mmr_t	reserved_2          : 7;
98 		mmr_t	serialize_fsb_en    : 1;
99 		mmr_t	tdot                : 1;
100 		mmr_t	reserved_1          : 4;
101 		mmr_t	inta_trans_rsp      : 1;
102 		mmr_t	xtpr_trans_rsp      : 1;
103 		mmr_t	io_trans_rsp        : 1;
104 		mmr_t	inta_rsp_data       : 8;
105 		mmr_t	short_hang_en       : 1;
106 		mmr_t	bnr_throttling_en   : 1;
107 		mmr_t	binit_assert_en     : 1;
108 		mmr_t	berr_sampling_en    : 1;
109 		mmr_t	berr_assert_en      : 1;
110 		mmr_t	reserved_0          : 2;
111 		mmr_t	rcnt_scnt_en        : 1;
123 	mmr_t	sh_fsb_vga_remap_regval;
125 		mmr_t	reserved_0            : 17;
126 		mmr_t	offset                : 19;
127 		mmr_t	asid                  : 2;
128 		mmr_t	nid                   : 11;
129 		mmr_t	reserved_1            : 13;
130 		mmr_t	vga_remapping_enabled : 1;
131 		mmr_t	reserved_2            : 1;
136 	mmr_t	sh_fsb_vga_remap_regval;
138 		mmr_t	reserved_2            : 1;
139 		mmr_t	vga_remapping_enabled : 1;
140 		mmr_t	reserved_1            : 13;
141 		mmr_t	nid                   : 11;
142 		mmr_t	asid                  : 2;
143 		mmr_t	offset                : 19;
144 		mmr_t	reserved_0            : 17;
156 	mmr_t	sh_fsb_reset_status_regval;
158 		mmr_t	reset_in_progress : 1;
159 		mmr_t	reserved_0        : 63;
164 	mmr_t	sh_fsb_reset_status_regval;
166 		mmr_t	reserved_0        : 63;
167 		mmr_t	reset_in_progress : 1;
179 	mmr_t	sh_fsb_symmetric_agent_status_regval;
181 		mmr_t	cpu_0_active : 1;
182 		mmr_t	cpu_1_active : 1;
183 		mmr_t	cpus_ready   : 1;
184 		mmr_t	reserved_0   : 61;
189 	mmr_t	sh_fsb_symmetric_agent_status_regval;
191 		mmr_t	reserved_0   : 61;
192 		mmr_t	cpus_ready   : 1;
193 		mmr_t	cpu_1_active : 1;
194 		mmr_t	cpu_0_active : 1;
206 	mmr_t	sh_gfx_credit_count_0_regval;
208 		mmr_t	count           : 20;
209 		mmr_t	reserved_0      : 43;
210 		mmr_t	reset_gfx_state : 1;
215 	mmr_t	sh_gfx_credit_count_0_regval;
217 		mmr_t	reset_gfx_state : 1;
218 		mmr_t	reserved_0      : 43;
219 		mmr_t	count           : 20;
231 	mmr_t	sh_gfx_credit_count_1_regval;
233 		mmr_t	count           : 20;
234 		mmr_t	reserved_0      : 43;
235 		mmr_t	reset_gfx_state : 1;
240 	mmr_t	sh_gfx_credit_count_1_regval;
242 		mmr_t	reset_gfx_state : 1;
243 		mmr_t	reserved_0      : 43;
244 		mmr_t	count           : 20;
256 	mmr_t	sh_gfx_mode_cntrl_0_regval;
258 		mmr_t	dword_credits      : 1;
259 		mmr_t	mixed_mode_credits : 1;
260 		mmr_t	relaxed_ordering   : 1;
261 		mmr_t	reserved_0         : 61;
266 	mmr_t	sh_gfx_mode_cntrl_0_regval;
268 		mmr_t	reserved_0         : 61;
269 		mmr_t	relaxed_ordering   : 1;
270 		mmr_t	mixed_mode_credits : 1;
271 		mmr_t	dword_credits      : 1;
283 	mmr_t	sh_gfx_mode_cntrl_1_regval;
285 		mmr_t	dword_credits      : 1;
286 		mmr_t	mixed_mode_credits : 1;
287 		mmr_t	relaxed_ordering   : 1;
288 		mmr_t	reserved_0         : 61;
293 	mmr_t	sh_gfx_mode_cntrl_1_regval;
295 		mmr_t	reserved_0         : 61;
296 		mmr_t	relaxed_ordering   : 1;
297 		mmr_t	mixed_mode_credits : 1;
298 		mmr_t	dword_credits      : 1;
310 	mmr_t	sh_gfx_skid_credit_count_0_regval;
312 		mmr_t	skid        : 20;
313 		mmr_t	reserved_0  : 44;
318 	mmr_t	sh_gfx_skid_credit_count_0_regval;
320 		mmr_t	reserved_0  : 44;
321 		mmr_t	skid        : 20;
333 	mmr_t	sh_gfx_skid_credit_count_1_regval;
335 		mmr_t	skid        : 20;
336 		mmr_t	reserved_0  : 44;
341 	mmr_t	sh_gfx_skid_credit_count_1_regval;
343 		mmr_t	reserved_0  : 44;
344 		mmr_t	skid        : 20;
356 	mmr_t	sh_gfx_stall_limit_0_regval;
358 		mmr_t	limit       : 26;
359 		mmr_t	reserved_0  : 38;
364 	mmr_t	sh_gfx_stall_limit_0_regval;
366 		mmr_t	reserved_0  : 38;
367 		mmr_t	limit       : 26;
379 	mmr_t	sh_gfx_stall_limit_1_regval;
381 		mmr_t	limit       : 26;
382 		mmr_t	reserved_0  : 38;
387 	mmr_t	sh_gfx_stall_limit_1_regval;
389 		mmr_t	reserved_0  : 38;
390 		mmr_t	limit       : 26;
402 	mmr_t	sh_gfx_stall_timer_0_regval;
404 		mmr_t	timer_value : 26;
405 		mmr_t	reserved_0  : 38;
410 	mmr_t	sh_gfx_stall_timer_0_regval;
412 		mmr_t	reserved_0  : 38;
413 		mmr_t	timer_value : 26;
425 	mmr_t	sh_gfx_stall_timer_1_regval;
427 		mmr_t	timer_value : 26;
428 		mmr_t	reserved_0  : 38;
433 	mmr_t	sh_gfx_stall_timer_1_regval;
435 		mmr_t	reserved_0  : 38;
436 		mmr_t	timer_value : 26;
448 	mmr_t	sh_gfx_window_0_regval;
450 		mmr_t	reserved_0    : 24;
451 		mmr_t	base_addr     : 12;
452 		mmr_t	reserved_1    : 27;
453 		mmr_t	gfx_window_en : 1;
458 	mmr_t	sh_gfx_window_0_regval;
460 		mmr_t	gfx_window_en : 1;
461 		mmr_t	reserved_1    : 27;
462 		mmr_t	base_addr     : 12;
463 		mmr_t	reserved_0    : 24;
475 	mmr_t	sh_gfx_window_1_regval;
477 		mmr_t	reserved_0    : 24;
478 		mmr_t	base_addr     : 12;
479 		mmr_t	reserved_1    : 27;
480 		mmr_t	gfx_window_en : 1;
485 	mmr_t	sh_gfx_window_1_regval;
487 		mmr_t	gfx_window_en : 1;
488 		mmr_t	reserved_1    : 27;
489 		mmr_t	base_addr     : 12;
490 		mmr_t	reserved_0    : 24;
502 	mmr_t	sh_gfx_interrupt_timer_limit_0_regval;
504 		mmr_t	interrupt_timer_limit : 8;
505 		mmr_t	reserved_0            : 56;
510 	mmr_t	sh_gfx_interrupt_timer_limit_0_regval;
512 		mmr_t	reserved_0            : 56;
513 		mmr_t	interrupt_timer_limit : 8;
525 	mmr_t	sh_gfx_interrupt_timer_limit_1_regval;
527 		mmr_t	interrupt_timer_limit : 8;
528 		mmr_t	reserved_0            : 56;
533 	mmr_t	sh_gfx_interrupt_timer_limit_1_regval;
535 		mmr_t	reserved_0            : 56;
536 		mmr_t	interrupt_timer_limit : 8;
548 	mmr_t	sh_gfx_write_status_0_regval;
550 		mmr_t	busy                : 1;
551 		mmr_t	reserved_0          : 62;
552 		mmr_t	re_enable_gfx_stall : 1;
557 	mmr_t	sh_gfx_write_status_0_regval;
559 		mmr_t	re_enable_gfx_stall : 1;
560 		mmr_t	reserved_0          : 62;
561 		mmr_t	busy                : 1;
573 	mmr_t	sh_gfx_write_status_1_regval;
575 		mmr_t	busy                : 1;
576 		mmr_t	reserved_0          : 62;
577 		mmr_t	re_enable_gfx_stall : 1;
582 	mmr_t	sh_gfx_write_status_1_regval;
584 		mmr_t	re_enable_gfx_stall : 1;
585 		mmr_t	reserved_0          : 62;
586 		mmr_t	busy                : 1;
598 	mmr_t	sh_ii_int0_regval;
600 		mmr_t	idx         : 8;
601 		mmr_t	send        : 1;
602 		mmr_t	reserved_0  : 55;
607 	mmr_t	sh_ii_int0_regval;
609 		mmr_t	reserved_0  : 55;
610 		mmr_t	send        : 1;
611 		mmr_t	idx         : 8;
623 	mmr_t	sh_ii_int0_config_regval;
625 		mmr_t	type        : 3;
626 		mmr_t	agt         : 1;
627 		mmr_t	pid         : 16;
628 		mmr_t	reserved_0  : 1;
629 		mmr_t	base        : 29;
630 		mmr_t	reserved_1  : 14;
635 	mmr_t	sh_ii_int0_config_regval;
637 		mmr_t	reserved_1  : 14;
638 		mmr_t	base        : 29;
639 		mmr_t	reserved_0  : 1;
640 		mmr_t	pid         : 16;
641 		mmr_t	agt         : 1;
642 		mmr_t	type        : 3;
654 	mmr_t	sh_ii_int0_enable_regval;
656 		mmr_t	ii_enable   : 1;
657 		mmr_t	reserved_0  : 63;
662 	mmr_t	sh_ii_int0_enable_regval;
664 		mmr_t	reserved_0  : 63;
665 		mmr_t	ii_enable   : 1;
677 	mmr_t	sh_ii_int1_regval;
679 		mmr_t	idx         : 8;
680 		mmr_t	send        : 1;
681 		mmr_t	reserved_0  : 55;
686 	mmr_t	sh_ii_int1_regval;
688 		mmr_t	reserved_0  : 55;
689 		mmr_t	send        : 1;
690 		mmr_t	idx         : 8;
702 	mmr_t	sh_ii_int1_config_regval;
704 		mmr_t	type        : 3;
705 		mmr_t	agt         : 1;
706 		mmr_t	pid         : 16;
707 		mmr_t	reserved_0  : 1;
708 		mmr_t	base        : 29;
709 		mmr_t	reserved_1  : 14;
714 	mmr_t	sh_ii_int1_config_regval;
716 		mmr_t	reserved_1  : 14;
717 		mmr_t	base        : 29;
718 		mmr_t	reserved_0  : 1;
719 		mmr_t	pid         : 16;
720 		mmr_t	agt         : 1;
721 		mmr_t	type        : 3;
733 	mmr_t	sh_ii_int1_enable_regval;
735 		mmr_t	ii_enable   : 1;
736 		mmr_t	reserved_0  : 63;
741 	mmr_t	sh_ii_int1_enable_regval;
743 		mmr_t	reserved_0  : 63;
744 		mmr_t	ii_enable   : 1;
756 	mmr_t	sh_int_node_id_config_regval;
758 		mmr_t	node_id     : 11;
759 		mmr_t	id_sel      : 1;
760 		mmr_t	reserved_0  : 52;
765 	mmr_t	sh_int_node_id_config_regval;
767 		mmr_t	reserved_0  : 52;
768 		mmr_t	id_sel      : 1;
769 		mmr_t	node_id     : 11;
781 	mmr_t	sh_ipi_int_regval;
783 		mmr_t	type        : 3;
784 		mmr_t	agt         : 1;
785 		mmr_t	pid         : 16;
786 		mmr_t	reserved_0  : 1;
787 		mmr_t	base        : 29;
788 		mmr_t	reserved_1  : 2;
789 		mmr_t	idx         : 8;
790 		mmr_t	reserved_2  : 3;
791 		mmr_t	send        : 1;
796 	mmr_t	sh_ipi_int_regval;
798 		mmr_t	send        : 1;
799 		mmr_t	reserved_2  : 3;
800 		mmr_t	idx         : 8;
801 		mmr_t	reserved_1  : 2;
802 		mmr_t	base        : 29;
803 		mmr_t	reserved_0  : 1;
804 		mmr_t	pid         : 16;
805 		mmr_t	agt         : 1;
806 		mmr_t	type        : 3;
818 	mmr_t	sh_ipi_int_enable_regval;
820 		mmr_t	pio_enable  : 1;
821 		mmr_t	reserved_0  : 63;
826 	mmr_t	sh_ipi_int_enable_regval;
828 		mmr_t	reserved_0  : 63;
829 		mmr_t	pio_enable  : 1;
841 	mmr_t	sh_local_int0_config_regval;
843 		mmr_t	type        : 3;
844 		mmr_t	agt         : 1;
845 		mmr_t	pid         : 16;
846 		mmr_t	reserved_0  : 1;
847 		mmr_t	base        : 29;
848 		mmr_t	reserved_1  : 2;
849 		mmr_t	idx         : 8;
850 		mmr_t	reserved_2  : 4;
855 	mmr_t	sh_local_int0_config_regval;
857 		mmr_t	reserved_2  : 4;
858 		mmr_t	idx         : 8;
859 		mmr_t	reserved_1  : 2;
860 		mmr_t	base        : 29;
861 		mmr_t	reserved_0  : 1;
862 		mmr_t	pid         : 16;
863 		mmr_t	agt         : 1;
864 		mmr_t	type        : 3;
876 	mmr_t	sh_local_int0_enable_regval;
878 		mmr_t	pi_hw_int           : 1;
879 		mmr_t	md_hw_int           : 1;
880 		mmr_t	xn_hw_int           : 1;
881 		mmr_t	lb_hw_int           : 1;
882 		mmr_t	ii_hw_int           : 1;
883 		mmr_t	pi_ce_int           : 1;
884 		mmr_t	md_ce_int           : 1;
885 		mmr_t	xn_ce_int           : 1;
886 		mmr_t	pi_uce_int          : 1;
887 		mmr_t	md_uce_int          : 1;
888 		mmr_t	xn_uce_int          : 1;
889 		mmr_t	reserved_0          : 1;
890 		mmr_t	system_shutdown_int : 1;
891 		mmr_t	uart_int            : 1;
892 		mmr_t	l1_nmi_int          : 1;
893 		mmr_t	stop_clock          : 1;
894 		mmr_t	reserved_1          : 48;
899 	mmr_t	sh_local_int0_enable_regval;
901 		mmr_t	reserved_1          : 48;
902 		mmr_t	stop_clock          : 1;
903 		mmr_t	l1_nmi_int          : 1;
904 		mmr_t	uart_int            : 1;
905 		mmr_t	system_shutdown_int : 1;
906 		mmr_t	reserved_0          : 1;
907 		mmr_t	xn_uce_int          : 1;
908 		mmr_t	md_uce_int          : 1;
909 		mmr_t	pi_uce_int          : 1;
910 		mmr_t	xn_ce_int           : 1;
911 		mmr_t	md_ce_int           : 1;
912 		mmr_t	pi_ce_int           : 1;
913 		mmr_t	ii_hw_int           : 1;
914 		mmr_t	lb_hw_int           : 1;
915 		mmr_t	xn_hw_int           : 1;
916 		mmr_t	md_hw_int           : 1;
917 		mmr_t	pi_hw_int           : 1;
929 	mmr_t	sh_local_int1_config_regval;
931 		mmr_t	type        : 3;
932 		mmr_t	agt         : 1;
933 		mmr_t	pid         : 16;
934 		mmr_t	reserved_0  : 1;
935 		mmr_t	base        : 29;
936 		mmr_t	reserved_1  : 2;
937 		mmr_t	idx         : 8;
938 		mmr_t	reserved_2  : 4;
943 	mmr_t	sh_local_int1_config_regval;
945 		mmr_t	reserved_2  : 4;
946 		mmr_t	idx         : 8;
947 		mmr_t	reserved_1  : 2;
948 		mmr_t	base        : 29;
949 		mmr_t	reserved_0  : 1;
950 		mmr_t	pid         : 16;
951 		mmr_t	agt         : 1;
952 		mmr_t	type        : 3;
964 	mmr_t	sh_local_int1_enable_regval;
966 		mmr_t	pi_hw_int           : 1;
967 		mmr_t	md_hw_int           : 1;
968 		mmr_t	xn_hw_int           : 1;
969 		mmr_t	lb_hw_int           : 1;
970 		mmr_t	ii_hw_int           : 1;
971 		mmr_t	pi_ce_int           : 1;
972 		mmr_t	md_ce_int           : 1;
973 		mmr_t	xn_ce_int           : 1;
974 		mmr_t	pi_uce_int          : 1;
975 		mmr_t	md_uce_int          : 1;
976 		mmr_t	xn_uce_int          : 1;
977 		mmr_t	reserved_0          : 1;
978 		mmr_t	system_shutdown_int : 1;
979 		mmr_t	uart_int            : 1;
980 		mmr_t	l1_nmi_int          : 1;
981 		mmr_t	stop_clock          : 1;
982 		mmr_t	reserved_1          : 48;
987 	mmr_t	sh_local_int1_enable_regval;
989 		mmr_t	reserved_1          : 48;
990 		mmr_t	stop_clock          : 1;
991 		mmr_t	l1_nmi_int          : 1;
992 		mmr_t	uart_int            : 1;
993 		mmr_t	system_shutdown_int : 1;
994 		mmr_t	reserved_0          : 1;
995 		mmr_t	xn_uce_int          : 1;
996 		mmr_t	md_uce_int          : 1;
997 		mmr_t	pi_uce_int          : 1;
998 		mmr_t	xn_ce_int           : 1;
999 		mmr_t	md_ce_int           : 1;
1000 		mmr_t	pi_ce_int           : 1;
1001 		mmr_t	ii_hw_int           : 1;
1002 		mmr_t	lb_hw_int           : 1;
1003 		mmr_t	xn_hw_int           : 1;
1004 		mmr_t	md_hw_int           : 1;
1005 		mmr_t	pi_hw_int           : 1;
1017 	mmr_t	sh_local_int2_config_regval;
1019 		mmr_t	type        : 3;
1020 		mmr_t	agt         : 1;
1021 		mmr_t	pid         : 16;
1022 		mmr_t	reserved_0  : 1;
1023 		mmr_t	base        : 29;
1024 		mmr_t	reserved_1  : 2;
1025 		mmr_t	idx         : 8;
1026 		mmr_t	reserved_2  : 4;
1031 	mmr_t	sh_local_int2_config_regval;
1033 		mmr_t	reserved_2  : 4;
1034 		mmr_t	idx         : 8;
1035 		mmr_t	reserved_1  : 2;
1036 		mmr_t	base        : 29;
1037 		mmr_t	reserved_0  : 1;
1038 		mmr_t	pid         : 16;
1039 		mmr_t	agt         : 1;
1040 		mmr_t	type        : 3;
1052 	mmr_t	sh_local_int2_enable_regval;
1054 		mmr_t	pi_hw_int           : 1;
1055 		mmr_t	md_hw_int           : 1;
1056 		mmr_t	xn_hw_int           : 1;
1057 		mmr_t	lb_hw_int           : 1;
1058 		mmr_t	ii_hw_int           : 1;
1059 		mmr_t	pi_ce_int           : 1;
1060 		mmr_t	md_ce_int           : 1;
1061 		mmr_t	xn_ce_int           : 1;
1062 		mmr_t	pi_uce_int          : 1;
1063 		mmr_t	md_uce_int          : 1;
1064 		mmr_t	xn_uce_int          : 1;
1065 		mmr_t	reserved_0          : 1;
1066 		mmr_t	system_shutdown_int : 1;
1067 		mmr_t	uart_int            : 1;
1068 		mmr_t	l1_nmi_int          : 1;
1069 		mmr_t	stop_clock          : 1;
1070 		mmr_t	reserved_1          : 48;
1075 	mmr_t	sh_local_int2_enable_regval;
1077 		mmr_t	reserved_1          : 48;
1078 		mmr_t	stop_clock          : 1;
1079 		mmr_t	l1_nmi_int          : 1;
1080 		mmr_t	uart_int            : 1;
1081 		mmr_t	system_shutdown_int : 1;
1082 		mmr_t	reserved_0          : 1;
1083 		mmr_t	xn_uce_int          : 1;
1084 		mmr_t	md_uce_int          : 1;
1085 		mmr_t	pi_uce_int          : 1;
1086 		mmr_t	xn_ce_int           : 1;
1087 		mmr_t	md_ce_int           : 1;
1088 		mmr_t	pi_ce_int           : 1;
1089 		mmr_t	ii_hw_int           : 1;
1090 		mmr_t	lb_hw_int           : 1;
1091 		mmr_t	xn_hw_int           : 1;
1092 		mmr_t	md_hw_int           : 1;
1093 		mmr_t	pi_hw_int           : 1;
1105 	mmr_t	sh_local_int3_config_regval;
1107 		mmr_t	type        : 3;
1108 		mmr_t	agt         : 1;
1109 		mmr_t	pid         : 16;
1110 		mmr_t	reserved_0  : 1;
1111 		mmr_t	base        : 29;
1112 		mmr_t	reserved_1  : 2;
1113 		mmr_t	idx         : 8;
1114 		mmr_t	reserved_2  : 4;
1119 	mmr_t	sh_local_int3_config_regval;
1121 		mmr_t	reserved_2  : 4;
1122 		mmr_t	idx         : 8;
1123 		mmr_t	reserved_1  : 2;
1124 		mmr_t	base        : 29;
1125 		mmr_t	reserved_0  : 1;
1126 		mmr_t	pid         : 16;
1127 		mmr_t	agt         : 1;
1128 		mmr_t	type        : 3;
1140 	mmr_t	sh_local_int3_enable_regval;
1142 		mmr_t	pi_hw_int           : 1;
1143 		mmr_t	md_hw_int           : 1;
1144 		mmr_t	xn_hw_int           : 1;
1145 		mmr_t	lb_hw_int           : 1;
1146 		mmr_t	ii_hw_int           : 1;
1147 		mmr_t	pi_ce_int           : 1;
1148 		mmr_t	md_ce_int           : 1;
1149 		mmr_t	xn_ce_int           : 1;
1150 		mmr_t	pi_uce_int          : 1;
1151 		mmr_t	md_uce_int          : 1;
1152 		mmr_t	xn_uce_int          : 1;
1153 		mmr_t	reserved_0          : 1;
1154 		mmr_t	system_shutdown_int : 1;
1155 		mmr_t	uart_int            : 1;
1156 		mmr_t	l1_nmi_int          : 1;
1157 		mmr_t	stop_clock          : 1;
1158 		mmr_t	reserved_1          : 48;
1163 	mmr_t	sh_local_int3_enable_regval;
1165 		mmr_t	reserved_1          : 48;
1166 		mmr_t	stop_clock          : 1;
1167 		mmr_t	l1_nmi_int          : 1;
1168 		mmr_t	uart_int            : 1;
1169 		mmr_t	system_shutdown_int : 1;
1170 		mmr_t	reserved_0          : 1;
1171 		mmr_t	xn_uce_int          : 1;
1172 		mmr_t	md_uce_int          : 1;
1173 		mmr_t	pi_uce_int          : 1;
1174 		mmr_t	xn_ce_int           : 1;
1175 		mmr_t	md_ce_int           : 1;
1176 		mmr_t	pi_ce_int           : 1;
1177 		mmr_t	ii_hw_int           : 1;
1178 		mmr_t	lb_hw_int           : 1;
1179 		mmr_t	xn_hw_int           : 1;
1180 		mmr_t	md_hw_int           : 1;
1181 		mmr_t	pi_hw_int           : 1;
1193 	mmr_t	sh_local_int4_config_regval;
1195 		mmr_t	type        : 3;
1196 		mmr_t	agt         : 1;
1197 		mmr_t	pid         : 16;
1198 		mmr_t	reserved_0  : 1;
1199 		mmr_t	base        : 29;
1200 		mmr_t	reserved_1  : 2;
1201 		mmr_t	idx         : 8;
1202 		mmr_t	reserved_2  : 4;
1207 	mmr_t	sh_local_int4_config_regval;
1209 		mmr_t	reserved_2  : 4;
1210 		mmr_t	idx         : 8;
1211 		mmr_t	reserved_1  : 2;
1212 		mmr_t	base        : 29;
1213 		mmr_t	reserved_0  : 1;
1214 		mmr_t	pid         : 16;
1215 		mmr_t	agt         : 1;
1216 		mmr_t	type        : 3;
1228 	mmr_t	sh_local_int4_enable_regval;
1230 		mmr_t	pi_hw_int           : 1;
1231 		mmr_t	md_hw_int           : 1;
1232 		mmr_t	xn_hw_int           : 1;
1233 		mmr_t	lb_hw_int           : 1;
1234 		mmr_t	ii_hw_int           : 1;
1235 		mmr_t	pi_ce_int           : 1;
1236 		mmr_t	md_ce_int           : 1;
1237 		mmr_t	xn_ce_int           : 1;
1238 		mmr_t	pi_uce_int          : 1;
1239 		mmr_t	md_uce_int          : 1;
1240 		mmr_t	xn_uce_int          : 1;
1241 		mmr_t	reserved_0          : 1;
1242 		mmr_t	system_shutdown_int : 1;
1243 		mmr_t	uart_int            : 1;
1244 		mmr_t	l1_nmi_int          : 1;
1245 		mmr_t	stop_clock          : 1;
1246 		mmr_t	reserved_1          : 48;
1251 	mmr_t	sh_local_int4_enable_regval;
1253 		mmr_t	reserved_1          : 48;
1254 		mmr_t	stop_clock          : 1;
1255 		mmr_t	l1_nmi_int          : 1;
1256 		mmr_t	uart_int            : 1;
1257 		mmr_t	system_shutdown_int : 1;
1258 		mmr_t	reserved_0          : 1;
1259 		mmr_t	xn_uce_int          : 1;
1260 		mmr_t	md_uce_int          : 1;
1261 		mmr_t	pi_uce_int          : 1;
1262 		mmr_t	xn_ce_int           : 1;
1263 		mmr_t	md_ce_int           : 1;
1264 		mmr_t	pi_ce_int           : 1;
1265 		mmr_t	ii_hw_int           : 1;
1266 		mmr_t	lb_hw_int           : 1;
1267 		mmr_t	xn_hw_int           : 1;
1268 		mmr_t	md_hw_int           : 1;
1269 		mmr_t	pi_hw_int           : 1;
1281 	mmr_t	sh_local_int5_config_regval;
1283 		mmr_t	type        : 3;
1284 		mmr_t	agt         : 1;
1285 		mmr_t	pid         : 16;
1286 		mmr_t	reserved_0  : 1;
1287 		mmr_t	base        : 29;
1288 		mmr_t	reserved_1  : 2;
1289 		mmr_t	idx         : 8;
1290 		mmr_t	reserved_2  : 4;
1295 	mmr_t	sh_local_int5_config_regval;
1297 		mmr_t	reserved_2  : 4;
1298 		mmr_t	idx         : 8;
1299 		mmr_t	reserved_1  : 2;
1300 		mmr_t	base        : 29;
1301 		mmr_t	reserved_0  : 1;
1302 		mmr_t	pid         : 16;
1303 		mmr_t	agt         : 1;
1304 		mmr_t	type        : 3;
1316 	mmr_t	sh_local_int5_enable_regval;
1318 		mmr_t	pi_hw_int           : 1;
1319 		mmr_t	md_hw_int           : 1;
1320 		mmr_t	xn_hw_int           : 1;
1321 		mmr_t	lb_hw_int           : 1;
1322 		mmr_t	ii_hw_int           : 1;
1323 		mmr_t	pi_ce_int           : 1;
1324 		mmr_t	md_ce_int           : 1;
1325 		mmr_t	xn_ce_int           : 1;
1326 		mmr_t	pi_uce_int          : 1;
1327 		mmr_t	md_uce_int          : 1;
1328 		mmr_t	xn_uce_int          : 1;
1329 		mmr_t	reserved_0          : 1;
1330 		mmr_t	system_shutdown_int : 1;
1331 		mmr_t	uart_int            : 1;
1332 		mmr_t	l1_nmi_int          : 1;
1333 		mmr_t	stop_clock          : 1;
1334 		mmr_t	reserved_1          : 48;
1339 	mmr_t	sh_local_int5_enable_regval;
1341 		mmr_t	reserved_1          : 48;
1342 		mmr_t	stop_clock          : 1;
1343 		mmr_t	l1_nmi_int          : 1;
1344 		mmr_t	uart_int            : 1;
1345 		mmr_t	system_shutdown_int : 1;
1346 		mmr_t	reserved_0          : 1;
1347 		mmr_t	xn_uce_int          : 1;
1348 		mmr_t	md_uce_int          : 1;
1349 		mmr_t	pi_uce_int          : 1;
1350 		mmr_t	xn_ce_int           : 1;
1351 		mmr_t	md_ce_int           : 1;
1352 		mmr_t	pi_ce_int           : 1;
1353 		mmr_t	ii_hw_int           : 1;
1354 		mmr_t	lb_hw_int           : 1;
1355 		mmr_t	xn_hw_int           : 1;
1356 		mmr_t	md_hw_int           : 1;
1357 		mmr_t	pi_hw_int           : 1;
1369 	mmr_t	sh_proc0_err_int_config_regval;
1371 		mmr_t	type        : 3;
1372 		mmr_t	agt         : 1;
1373 		mmr_t	pid         : 16;
1374 		mmr_t	reserved_0  : 1;
1375 		mmr_t	base        : 29;
1376 		mmr_t	reserved_1  : 2;
1377 		mmr_t	idx         : 8;
1378 		mmr_t	reserved_2  : 4;
1383 	mmr_t	sh_proc0_err_int_config_regval;
1385 		mmr_t	reserved_2  : 4;
1386 		mmr_t	idx         : 8;
1387 		mmr_t	reserved_1  : 2;
1388 		mmr_t	base        : 29;
1389 		mmr_t	reserved_0  : 1;
1390 		mmr_t	pid         : 16;
1391 		mmr_t	agt         : 1;
1392 		mmr_t	type        : 3;
1404 	mmr_t	sh_proc1_err_int_config_regval;
1406 		mmr_t	type        : 3;
1407 		mmr_t	agt         : 1;
1408 		mmr_t	pid         : 16;
1409 		mmr_t	reserved_0  : 1;
1410 		mmr_t	base        : 29;
1411 		mmr_t	reserved_1  : 2;
1412 		mmr_t	idx         : 8;
1413 		mmr_t	reserved_2  : 4;
1418 	mmr_t	sh_proc1_err_int_config_regval;
1420 		mmr_t	reserved_2  : 4;
1421 		mmr_t	idx         : 8;
1422 		mmr_t	reserved_1  : 2;
1423 		mmr_t	base        : 29;
1424 		mmr_t	reserved_0  : 1;
1425 		mmr_t	pid         : 16;
1426 		mmr_t	agt         : 1;
1427 		mmr_t	type        : 3;
1439 	mmr_t	sh_proc2_err_int_config_regval;
1441 		mmr_t	type        : 3;
1442 		mmr_t	agt         : 1;
1443 		mmr_t	pid         : 16;
1444 		mmr_t	reserved_0  : 1;
1445 		mmr_t	base        : 29;
1446 		mmr_t	reserved_1  : 2;
1447 		mmr_t	idx         : 8;
1448 		mmr_t	reserved_2  : 4;
1453 	mmr_t	sh_proc2_err_int_config_regval;
1455 		mmr_t	reserved_2  : 4;
1456 		mmr_t	idx         : 8;
1457 		mmr_t	reserved_1  : 2;
1458 		mmr_t	base        : 29;
1459 		mmr_t	reserved_0  : 1;
1460 		mmr_t	pid         : 16;
1461 		mmr_t	agt         : 1;
1462 		mmr_t	type        : 3;
1474 	mmr_t	sh_proc3_err_int_config_regval;
1476 		mmr_t	type        : 3;
1477 		mmr_t	agt         : 1;
1478 		mmr_t	pid         : 16;
1479 		mmr_t	reserved_0  : 1;
1480 		mmr_t	base        : 29;
1481 		mmr_t	reserved_1  : 2;
1482 		mmr_t	idx         : 8;
1483 		mmr_t	reserved_2  : 4;
1488 	mmr_t	sh_proc3_err_int_config_regval;
1490 		mmr_t	reserved_2  : 4;
1491 		mmr_t	idx         : 8;
1492 		mmr_t	reserved_1  : 2;
1493 		mmr_t	base        : 29;
1494 		mmr_t	reserved_0  : 1;
1495 		mmr_t	pid         : 16;
1496 		mmr_t	agt         : 1;
1497 		mmr_t	type        : 3;
1509 	mmr_t	sh_proc0_adv_int_config_regval;
1511 		mmr_t	type        : 3;
1512 		mmr_t	agt         : 1;
1513 		mmr_t	pid         : 16;
1514 		mmr_t	reserved_0  : 1;
1515 		mmr_t	base        : 29;
1516 		mmr_t	reserved_1  : 2;
1517 		mmr_t	idx         : 8;
1518 		mmr_t	reserved_2  : 4;
1523 	mmr_t	sh_proc0_adv_int_config_regval;
1525 		mmr_t	reserved_2  : 4;
1526 		mmr_t	idx         : 8;
1527 		mmr_t	reserved_1  : 2;
1528 		mmr_t	base        : 29;
1529 		mmr_t	reserved_0  : 1;
1530 		mmr_t	pid         : 16;
1531 		mmr_t	agt         : 1;
1532 		mmr_t	type        : 3;
1544 	mmr_t	sh_proc1_adv_int_config_regval;
1546 		mmr_t	type        : 3;
1547 		mmr_t	agt         : 1;
1548 		mmr_t	pid         : 16;
1549 		mmr_t	reserved_0  : 1;
1550 		mmr_t	base        : 29;
1551 		mmr_t	reserved_1  : 2;
1552 		mmr_t	idx         : 8;
1553 		mmr_t	reserved_2  : 4;
1558 	mmr_t	sh_proc1_adv_int_config_regval;
1560 		mmr_t	reserved_2  : 4;
1561 		mmr_t	idx         : 8;
1562 		mmr_t	reserved_1  : 2;
1563 		mmr_t	base        : 29;
1564 		mmr_t	reserved_0  : 1;
1565 		mmr_t	pid         : 16;
1566 		mmr_t	agt         : 1;
1567 		mmr_t	type        : 3;
1579 	mmr_t	sh_proc2_adv_int_config_regval;
1581 		mmr_t	type        : 3;
1582 		mmr_t	agt         : 1;
1583 		mmr_t	pid         : 16;
1584 		mmr_t	reserved_0  : 1;
1585 		mmr_t	base        : 29;
1586 		mmr_t	reserved_1  : 2;
1587 		mmr_t	idx         : 8;
1588 		mmr_t	reserved_2  : 4;
1593 	mmr_t	sh_proc2_adv_int_config_regval;
1595 		mmr_t	reserved_2  : 4;
1596 		mmr_t	idx         : 8;
1597 		mmr_t	reserved_1  : 2;
1598 		mmr_t	base        : 29;
1599 		mmr_t	reserved_0  : 1;
1600 		mmr_t	pid         : 16;
1601 		mmr_t	agt         : 1;
1602 		mmr_t	type        : 3;
1614 	mmr_t	sh_proc3_adv_int_config_regval;
1616 		mmr_t	type        : 3;
1617 		mmr_t	agt         : 1;
1618 		mmr_t	pid         : 16;
1619 		mmr_t	reserved_0  : 1;
1620 		mmr_t	base        : 29;
1621 		mmr_t	reserved_1  : 2;
1622 		mmr_t	idx         : 8;
1623 		mmr_t	reserved_2  : 4;
1628 	mmr_t	sh_proc3_adv_int_config_regval;
1630 		mmr_t	reserved_2  : 4;
1631 		mmr_t	idx         : 8;
1632 		mmr_t	reserved_1  : 2;
1633 		mmr_t	base        : 29;
1634 		mmr_t	reserved_0  : 1;
1635 		mmr_t	pid         : 16;
1636 		mmr_t	agt         : 1;
1637 		mmr_t	type        : 3;
1649 	mmr_t	sh_proc0_err_int_enable_regval;
1651 		mmr_t	proc0_err_enable : 1;
1652 		mmr_t	reserved_0       : 63;
1657 	mmr_t	sh_proc0_err_int_enable_regval;
1659 		mmr_t	reserved_0       : 63;
1660 		mmr_t	proc0_err_enable : 1;
1672 	mmr_t	sh_proc1_err_int_enable_regval;
1674 		mmr_t	proc1_err_enable : 1;
1675 		mmr_t	reserved_0       : 63;
1680 	mmr_t	sh_proc1_err_int_enable_regval;
1682 		mmr_t	reserved_0       : 63;
1683 		mmr_t	proc1_err_enable : 1;
1695 	mmr_t	sh_proc2_err_int_enable_regval;
1697 		mmr_t	proc2_err_enable : 1;
1698 		mmr_t	reserved_0       : 63;
1703 	mmr_t	sh_proc2_err_int_enable_regval;
1705 		mmr_t	reserved_0       : 63;
1706 		mmr_t	proc2_err_enable : 1;
1718 	mmr_t	sh_proc3_err_int_enable_regval;
1720 		mmr_t	proc3_err_enable : 1;
1721 		mmr_t	reserved_0       : 63;
1726 	mmr_t	sh_proc3_err_int_enable_regval;
1728 		mmr_t	reserved_0       : 63;
1729 		mmr_t	proc3_err_enable : 1;
1741 	mmr_t	sh_proc0_adv_int_enable_regval;
1743 		mmr_t	proc0_adv_enable : 1;
1744 		mmr_t	reserved_0       : 63;
1749 	mmr_t	sh_proc0_adv_int_enable_regval;
1751 		mmr_t	reserved_0       : 63;
1752 		mmr_t	proc0_adv_enable : 1;
1764 	mmr_t	sh_proc1_adv_int_enable_regval;
1766 		mmr_t	proc1_adv_enable : 1;
1767 		mmr_t	reserved_0       : 63;
1772 	mmr_t	sh_proc1_adv_int_enable_regval;
1774 		mmr_t	reserved_0       : 63;
1775 		mmr_t	proc1_adv_enable : 1;
1787 	mmr_t	sh_proc2_adv_int_enable_regval;
1789 		mmr_t	proc2_adv_enable : 1;
1790 		mmr_t	reserved_0       : 63;
1795 	mmr_t	sh_proc2_adv_int_enable_regval;
1797 		mmr_t	reserved_0       : 63;
1798 		mmr_t	proc2_adv_enable : 1;
1810 	mmr_t	sh_proc3_adv_int_enable_regval;
1812 		mmr_t	proc3_adv_enable : 1;
1813 		mmr_t	reserved_0       : 63;
1818 	mmr_t	sh_proc3_adv_int_enable_regval;
1820 		mmr_t	reserved_0       : 63;
1821 		mmr_t	proc3_adv_enable : 1;
1833 	mmr_t	sh_profile_int_config_regval;
1835 		mmr_t	type        : 3;
1836 		mmr_t	agt         : 1;
1837 		mmr_t	pid         : 16;
1838 		mmr_t	reserved_0  : 1;
1839 		mmr_t	base        : 29;
1840 		mmr_t	reserved_1  : 2;
1841 		mmr_t	idx         : 8;
1842 		mmr_t	reserved_2  : 4;
1847 	mmr_t	sh_profile_int_config_regval;
1849 		mmr_t	reserved_2  : 4;
1850 		mmr_t	idx         : 8;
1851 		mmr_t	reserved_1  : 2;
1852 		mmr_t	base        : 29;
1853 		mmr_t	reserved_0  : 1;
1854 		mmr_t	pid         : 16;
1855 		mmr_t	agt         : 1;
1856 		mmr_t	type        : 3;
1868 	mmr_t	sh_profile_int_enable_regval;
1870 		mmr_t	profile_enable : 1;
1871 		mmr_t	reserved_0     : 63;
1876 	mmr_t	sh_profile_int_enable_regval;
1878 		mmr_t	reserved_0     : 63;
1879 		mmr_t	profile_enable : 1;
1891 	mmr_t	sh_rtc0_int_config_regval;
1893 		mmr_t	type        : 3;
1894 		mmr_t	agt         : 1;
1895 		mmr_t	pid         : 16;
1896 		mmr_t	reserved_0  : 1;
1897 		mmr_t	base        : 29;
1898 		mmr_t	reserved_1  : 2;
1899 		mmr_t	idx         : 8;
1900 		mmr_t	reserved_2  : 4;
1905 	mmr_t	sh_rtc0_int_config_regval;
1907 		mmr_t	reserved_2  : 4;
1908 		mmr_t	idx         : 8;
1909 		mmr_t	reserved_1  : 2;
1910 		mmr_t	base        : 29;
1911 		mmr_t	reserved_0  : 1;
1912 		mmr_t	pid         : 16;
1913 		mmr_t	agt         : 1;
1914 		mmr_t	type        : 3;
1926 	mmr_t	sh_rtc0_int_enable_regval;
1928 		mmr_t	rtc0_enable : 1;
1929 		mmr_t	reserved_0  : 63;
1934 	mmr_t	sh_rtc0_int_enable_regval;
1936 		mmr_t	reserved_0  : 63;
1937 		mmr_t	rtc0_enable : 1;
1949 	mmr_t	sh_rtc1_int_config_regval;
1951 		mmr_t	type        : 3;
1952 		mmr_t	agt         : 1;
1953 		mmr_t	pid         : 16;
1954 		mmr_t	reserved_0  : 1;
1955 		mmr_t	base        : 29;
1956 		mmr_t	reserved_1  : 2;
1957 		mmr_t	idx         : 8;
1958 		mmr_t	reserved_2  : 4;
1963 	mmr_t	sh_rtc1_int_config_regval;
1965 		mmr_t	reserved_2  : 4;
1966 		mmr_t	idx         : 8;
1967 		mmr_t	reserved_1  : 2;
1968 		mmr_t	base        : 29;
1969 		mmr_t	reserved_0  : 1;
1970 		mmr_t	pid         : 16;
1971 		mmr_t	agt         : 1;
1972 		mmr_t	type        : 3;
1984 	mmr_t	sh_rtc1_int_enable_regval;
1986 		mmr_t	rtc1_enable : 1;
1987 		mmr_t	reserved_0  : 63;
1992 	mmr_t	sh_rtc1_int_enable_regval;
1994 		mmr_t	reserved_0  : 63;
1995 		mmr_t	rtc1_enable : 1;
2007 	mmr_t	sh_rtc2_int_config_regval;
2009 		mmr_t	type        : 3;
2010 		mmr_t	agt         : 1;
2011 		mmr_t	pid         : 16;
2012 		mmr_t	reserved_0  : 1;
2013 		mmr_t	base        : 29;
2014 		mmr_t	reserved_1  : 2;
2015 		mmr_t	idx         : 8;
2016 		mmr_t	reserved_2  : 4;
2021 	mmr_t	sh_rtc2_int_config_regval;
2023 		mmr_t	reserved_2  : 4;
2024 		mmr_t	idx         : 8;
2025 		mmr_t	reserved_1  : 2;
2026 		mmr_t	base        : 29;
2027 		mmr_t	reserved_0  : 1;
2028 		mmr_t	pid         : 16;
2029 		mmr_t	agt         : 1;
2030 		mmr_t	type        : 3;
2042 	mmr_t	sh_rtc2_int_enable_regval;
2044 		mmr_t	rtc2_enable : 1;
2045 		mmr_t	reserved_0  : 63;
2050 	mmr_t	sh_rtc2_int_enable_regval;
2052 		mmr_t	reserved_0  : 63;
2053 		mmr_t	rtc2_enable : 1;
2065 	mmr_t	sh_rtc3_int_config_regval;
2067 		mmr_t	type        : 3;
2068 		mmr_t	agt         : 1;
2069 		mmr_t	pid         : 16;
2070 		mmr_t	reserved_0  : 1;
2071 		mmr_t	base        : 29;
2072 		mmr_t	reserved_1  : 2;
2073 		mmr_t	idx         : 8;
2074 		mmr_t	reserved_2  : 4;
2079 	mmr_t	sh_rtc3_int_config_regval;
2081 		mmr_t	reserved_2  : 4;
2082 		mmr_t	idx         : 8;
2083 		mmr_t	reserved_1  : 2;
2084 		mmr_t	base        : 29;
2085 		mmr_t	reserved_0  : 1;
2086 		mmr_t	pid         : 16;
2087 		mmr_t	agt         : 1;
2088 		mmr_t	type        : 3;
2100 	mmr_t	sh_rtc3_int_enable_regval;
2102 		mmr_t	rtc3_enable : 1;
2103 		mmr_t	reserved_0  : 63;
2108 	mmr_t	sh_rtc3_int_enable_regval;
2110 		mmr_t	reserved_0  : 63;
2111 		mmr_t	rtc3_enable : 1;
2123 	mmr_t	sh_event_occurred_regval;
2125 		mmr_t	pi_hw_int           : 1;
2126 		mmr_t	md_hw_int           : 1;
2127 		mmr_t	xn_hw_int           : 1;
2128 		mmr_t	lb_hw_int           : 1;
2129 		mmr_t	ii_hw_int           : 1;
2130 		mmr_t	pi_ce_int           : 1;
2131 		mmr_t	md_ce_int           : 1;
2132 		mmr_t	xn_ce_int           : 1;
2133 		mmr_t	pi_uce_int          : 1;
2134 		mmr_t	md_uce_int          : 1;
2135 		mmr_t	xn_uce_int          : 1;
2136 		mmr_t	proc0_adv_int       : 1;
2137 		mmr_t	proc1_adv_int       : 1;
2138 		mmr_t	proc2_adv_int       : 1;
2139 		mmr_t	proc3_adv_int       : 1;
2140 		mmr_t	proc0_err_int       : 1;
2141 		mmr_t	proc1_err_int       : 1;
2142 		mmr_t	proc2_err_int       : 1;
2143 		mmr_t	proc3_err_int       : 1;
2144 		mmr_t	system_shutdown_int : 1;
2145 		mmr_t	uart_int            : 1;
2146 		mmr_t	l1_nmi_int          : 1;
2147 		mmr_t	stop_clock          : 1;
2148 		mmr_t	rtc0_int            : 1;
2149 		mmr_t	rtc1_int            : 1;
2150 		mmr_t	rtc2_int            : 1;
2151 		mmr_t	rtc3_int            : 1;
2152 		mmr_t	profile_int         : 1;
2153 		mmr_t	ipi_int             : 1;
2154 		mmr_t	ii_int0             : 1;
2155 		mmr_t	ii_int1             : 1;
2156 		mmr_t	reserved_0          : 33;
2161 	mmr_t	sh_event_occurred_regval;
2163 		mmr_t	reserved_0          : 33;
2164 		mmr_t	ii_int1             : 1;
2165 		mmr_t	ii_int0             : 1;
2166 		mmr_t	ipi_int             : 1;
2167 		mmr_t	profile_int         : 1;
2168 		mmr_t	rtc3_int            : 1;
2169 		mmr_t	rtc2_int            : 1;
2170 		mmr_t	rtc1_int            : 1;
2171 		mmr_t	rtc0_int            : 1;
2172 		mmr_t	stop_clock          : 1;
2173 		mmr_t	l1_nmi_int          : 1;
2174 		mmr_t	uart_int            : 1;
2175 		mmr_t	system_shutdown_int : 1;
2176 		mmr_t	proc3_err_int       : 1;
2177 		mmr_t	proc2_err_int       : 1;
2178 		mmr_t	proc1_err_int       : 1;
2179 		mmr_t	proc0_err_int       : 1;
2180 		mmr_t	proc3_adv_int       : 1;
2181 		mmr_t	proc2_adv_int       : 1;
2182 		mmr_t	proc1_adv_int       : 1;
2183 		mmr_t	proc0_adv_int       : 1;
2184 		mmr_t	xn_uce_int          : 1;
2185 		mmr_t	md_uce_int          : 1;
2186 		mmr_t	pi_uce_int          : 1;
2187 		mmr_t	xn_ce_int           : 1;
2188 		mmr_t	md_ce_int           : 1;
2189 		mmr_t	pi_ce_int           : 1;
2190 		mmr_t	ii_hw_int           : 1;
2191 		mmr_t	lb_hw_int           : 1;
2192 		mmr_t	xn_hw_int           : 1;
2193 		mmr_t	md_hw_int           : 1;
2194 		mmr_t	pi_hw_int           : 1;
2206 	mmr_t	sh_event_overflow_regval;
2208 		mmr_t	pi_hw_int           : 1;
2209 		mmr_t	md_hw_int           : 1;
2210 		mmr_t	xn_hw_int           : 1;
2211 		mmr_t	lb_hw_int           : 1;
2212 		mmr_t	ii_hw_int           : 1;
2213 		mmr_t	pi_ce_int           : 1;
2214 		mmr_t	md_ce_int           : 1;
2215 		mmr_t	xn_ce_int           : 1;
2216 		mmr_t	pi_uce_int          : 1;
2217 		mmr_t	md_uce_int          : 1;
2218 		mmr_t	xn_uce_int          : 1;
2219 		mmr_t	proc0_adv_int       : 1;
2220 		mmr_t	proc1_adv_int       : 1;
2221 		mmr_t	proc2_adv_int       : 1;
2222 		mmr_t	proc3_adv_int       : 1;
2223 		mmr_t	proc0_err_int       : 1;
2224 		mmr_t	proc1_err_int       : 1;
2225 		mmr_t	proc2_err_int       : 1;
2226 		mmr_t	proc3_err_int       : 1;
2227 		mmr_t	system_shutdown_int : 1;
2228 		mmr_t	uart_int            : 1;
2229 		mmr_t	l1_nmi_int          : 1;
2230 		mmr_t	stop_clock          : 1;
2231 		mmr_t	rtc0_int            : 1;
2232 		mmr_t	rtc1_int            : 1;
2233 		mmr_t	rtc2_int            : 1;
2234 		mmr_t	rtc3_int            : 1;
2235 		mmr_t	profile_int         : 1;
2236 		mmr_t	reserved_0          : 36;
2241 	mmr_t	sh_event_overflow_regval;
2243 		mmr_t	reserved_0          : 36;
2244 		mmr_t	profile_int         : 1;
2245 		mmr_t	rtc3_int            : 1;
2246 		mmr_t	rtc2_int            : 1;
2247 		mmr_t	rtc1_int            : 1;
2248 		mmr_t	rtc0_int            : 1;
2249 		mmr_t	stop_clock          : 1;
2250 		mmr_t	l1_nmi_int          : 1;
2251 		mmr_t	uart_int            : 1;
2252 		mmr_t	system_shutdown_int : 1;
2253 		mmr_t	proc3_err_int       : 1;
2254 		mmr_t	proc2_err_int       : 1;
2255 		mmr_t	proc1_err_int       : 1;
2256 		mmr_t	proc0_err_int       : 1;
2257 		mmr_t	proc3_adv_int       : 1;
2258 		mmr_t	proc2_adv_int       : 1;
2259 		mmr_t	proc1_adv_int       : 1;
2260 		mmr_t	proc0_adv_int       : 1;
2261 		mmr_t	xn_uce_int          : 1;
2262 		mmr_t	md_uce_int          : 1;
2263 		mmr_t	pi_uce_int          : 1;
2264 		mmr_t	xn_ce_int           : 1;
2265 		mmr_t	md_ce_int           : 1;
2266 		mmr_t	pi_ce_int           : 1;
2267 		mmr_t	ii_hw_int           : 1;
2268 		mmr_t	lb_hw_int           : 1;
2269 		mmr_t	xn_hw_int           : 1;
2270 		mmr_t	md_hw_int           : 1;
2271 		mmr_t	pi_hw_int           : 1;
2283 	mmr_t	sh_junk_bus_time_regval;
2285 		mmr_t	fprom_setup_hold : 8;
2286 		mmr_t	fprom_enable     : 8;
2287 		mmr_t	uart_setup_hold  : 8;
2288 		mmr_t	uart_enable      : 8;
2289 		mmr_t	reserved_0       : 32;
2294 	mmr_t	sh_junk_bus_time_regval;
2296 		mmr_t	reserved_0       : 32;
2297 		mmr_t	uart_enable      : 8;
2298 		mmr_t	uart_setup_hold  : 8;
2299 		mmr_t	fprom_enable     : 8;
2300 		mmr_t	fprom_setup_hold : 8;
2312 	mmr_t	sh_junk_latch_time_regval;
2314 		mmr_t	setup_hold  : 3;
2315 		mmr_t	reserved_0  : 61;
2320 	mmr_t	sh_junk_latch_time_regval;
2322 		mmr_t	reserved_0  : 61;
2323 		mmr_t	setup_hold  : 3;
2335 	mmr_t	sh_junk_nack_reset_regval;
2337 		mmr_t	pulse       : 1;
2338 		mmr_t	reserved_0  : 63;
2343 	mmr_t	sh_junk_nack_reset_regval;
2345 		mmr_t	reserved_0  : 63;
2346 		mmr_t	pulse       : 1;
2358 	mmr_t	sh_junk_bus_led0_regval;
2360 		mmr_t	led0_data   : 8;
2361 		mmr_t	reserved_0  : 56;
2366 	mmr_t	sh_junk_bus_led0_regval;
2368 		mmr_t	reserved_0  : 56;
2369 		mmr_t	led0_data   : 8;
2381 	mmr_t	sh_junk_bus_led1_regval;
2383 		mmr_t	led1_data   : 8;
2384 		mmr_t	reserved_0  : 56;
2389 	mmr_t	sh_junk_bus_led1_regval;
2391 		mmr_t	reserved_0  : 56;
2392 		mmr_t	led1_data   : 8;
2404 	mmr_t	sh_junk_bus_led2_regval;
2406 		mmr_t	led2_data   : 8;
2407 		mmr_t	reserved_0  : 56;
2412 	mmr_t	sh_junk_bus_led2_regval;
2414 		mmr_t	reserved_0  : 56;
2415 		mmr_t	led2_data   : 8;
2427 	mmr_t	sh_junk_bus_led3_regval;
2429 		mmr_t	led3_data   : 8;
2430 		mmr_t	reserved_0  : 56;
2435 	mmr_t	sh_junk_bus_led3_regval;
2437 		mmr_t	reserved_0  : 56;
2438 		mmr_t	led3_data   : 8;
2450 	mmr_t	sh_junk_error_status_regval;
2452 		mmr_t	address     : 47;
2453 		mmr_t	reserved_0  : 1;
2454 		mmr_t	cmd         : 8;
2455 		mmr_t	mode        : 1;
2456 		mmr_t	status      : 4;
2457 		mmr_t	reserved_1  : 3;
2462 	mmr_t	sh_junk_error_status_regval;
2464 		mmr_t	reserved_1  : 3;
2465 		mmr_t	status      : 4;
2466 		mmr_t	mode        : 1;
2467 		mmr_t	cmd         : 8;
2468 		mmr_t	reserved_0  : 1;
2469 		mmr_t	address     : 47;
2481 	mmr_t	sh_ni0_llp_stat_regval;
2483 		mmr_t	link_reset_state : 4;
2484 		mmr_t	reserved_0       : 60;
2489 	mmr_t	sh_ni0_llp_stat_regval;
2491 		mmr_t	reserved_0       : 60;
2492 		mmr_t	link_reset_state : 4;
2504 	mmr_t	sh_ni0_llp_reset_regval;
2506 		mmr_t	link        : 1;
2507 		mmr_t	warm        : 1;
2508 		mmr_t	reserved_0  : 62;
2513 	mmr_t	sh_ni0_llp_reset_regval;
2515 		mmr_t	reserved_0  : 62;
2516 		mmr_t	warm        : 1;
2517 		mmr_t	link        : 1;
2529 	mmr_t	sh_ni0_llp_reset_en_regval;
2531 		mmr_t	ok          : 1;
2532 		mmr_t	reserved_0  : 63;
2537 	mmr_t	sh_ni0_llp_reset_en_regval;
2539 		mmr_t	reserved_0  : 63;
2540 		mmr_t	ok          : 1;
2552 	mmr_t	sh_ni0_llp_chan_mode_regval;
2554 		mmr_t	bitmode32         : 1;
2555 		mmr_t	ac_encode         : 1;
2556 		mmr_t	enable_tuning     : 1;
2557 		mmr_t	enable_rmt_ft_upd : 1;
2558 		mmr_t	enable_clkquad    : 1;
2559 		mmr_t	reserved_0        : 59;
2564 	mmr_t	sh_ni0_llp_chan_mode_regval;
2566 		mmr_t	reserved_0        : 59;
2567 		mmr_t	enable_clkquad    : 1;
2568 		mmr_t	enable_rmt_ft_upd : 1;
2569 		mmr_t	enable_tuning     : 1;
2570 		mmr_t	ac_encode         : 1;
2571 		mmr_t	bitmode32         : 1;
2583 	mmr_t	sh_ni0_llp_config_regval;
2585 		mmr_t	maxburst    : 10;
2586 		mmr_t	maxretry    : 10;
2587 		mmr_t	nulltimeout : 6;
2588 		mmr_t	ftu_time    : 12;
2589 		mmr_t	reserved_0  : 26;
2594 	mmr_t	sh_ni0_llp_config_regval;
2596 		mmr_t	reserved_0  : 26;
2597 		mmr_t	ftu_time    : 12;
2598 		mmr_t	nulltimeout : 6;
2599 		mmr_t	maxretry    : 10;
2600 		mmr_t	maxburst    : 10;
2611 	mmr_t	sh_ni0_llp_test_ctl_regval;
2613 		mmr_t	pattern        : 40;
2614 		mmr_t	send_test_mode : 2;
2615 		mmr_t	reserved_0     : 2;
2616 		mmr_t	wire_sel       : 6;
2617 		mmr_t	reserved_1     : 2;
2618 		mmr_t	lfsr_mode      : 2;
2619 		mmr_t	noise_mode     : 2;
2620 		mmr_t	armcapture     : 1;
2621 		mmr_t	capturecbonly  : 1;
2622 		mmr_t	sendcberror    : 1;
2623 		mmr_t	sendsnerror    : 1;
2624 		mmr_t	fakesnerror    : 1;
2625 		mmr_t	captured       : 1;
2626 		mmr_t	cberror        : 1;
2627 		mmr_t	reserved_2     : 1;
2632 	mmr_t	sh_ni0_llp_test_ctl_regval;
2634 		mmr_t	reserved_2     : 1;
2635 		mmr_t	cberror        : 1;
2636 		mmr_t	captured       : 1;
2637 		mmr_t	fakesnerror    : 1;
2638 		mmr_t	sendsnerror    : 1;
2639 		mmr_t	sendcberror    : 1;
2640 		mmr_t	capturecbonly  : 1;
2641 		mmr_t	armcapture     : 1;
2642 		mmr_t	noise_mode     : 2;
2643 		mmr_t	lfsr_mode      : 2;
2644 		mmr_t	reserved_1     : 2;
2645 		mmr_t	wire_sel       : 6;
2646 		mmr_t	reserved_0     : 2;
2647 		mmr_t	send_test_mode : 2;
2648 		mmr_t	pattern        : 40;
2660 	mmr_t	sh_ni0_llp_capt_wd1_regval;
2662 		mmr_t	data        : 64;
2667 	mmr_t	sh_ni0_llp_capt_wd1_regval;
2669 		mmr_t	data        : 64;
2681 	mmr_t	sh_ni0_llp_capt_wd2_regval;
2683 		mmr_t	data        : 64;
2688 	mmr_t	sh_ni0_llp_capt_wd2_regval;
2690 		mmr_t	data        : 64;
2702 	mmr_t	sh_ni0_llp_capt_sbcb_regval;
2704 		mmr_t	capturedrcvsbsn  : 16;
2705 		mmr_t	capturedrcvcrc   : 16;
2706 		mmr_t	sentallcberrors  : 1;
2707 		mmr_t	sentallsnerrors  : 1;
2708 		mmr_t	fakedallsnerrors : 1;
2709 		mmr_t	chargeoverflow   : 1;
2710 		mmr_t	chargeunderflow  : 1;
2711 		mmr_t	reserved_0       : 27;
2716 	mmr_t	sh_ni0_llp_capt_sbcb_regval;
2718 		mmr_t	reserved_0       : 27;
2719 		mmr_t	chargeunderflow  : 1;
2720 		mmr_t	chargeoverflow   : 1;
2721 		mmr_t	fakedallsnerrors : 1;
2722 		mmr_t	sentallsnerrors  : 1;
2723 		mmr_t	sentallcberrors  : 1;
2724 		mmr_t	capturedrcvcrc   : 16;
2725 		mmr_t	capturedrcvsbsn  : 16;
2736 	mmr_t	sh_ni0_llp_err_regval;
2738 		mmr_t	rx_sn_err_count : 8;
2739 		mmr_t	rx_cb_err_count : 8;
2740 		mmr_t	retry_count     : 8;
2741 		mmr_t	retry_timeout   : 1;
2742 		mmr_t	rcv_link_reset  : 1;
2743 		mmr_t	squash          : 1;
2744 		mmr_t	power_not_ok    : 1;
2745 		mmr_t	wire_cnt        : 24;
2746 		mmr_t	wire_overflow   : 1;
2747 		mmr_t	reserved_0      : 11;
2752 	mmr_t	sh_ni0_llp_err_regval;
2754 		mmr_t	reserved_0      : 11;
2755 		mmr_t	wire_overflow   : 1;
2756 		mmr_t	wire_cnt        : 24;
2757 		mmr_t	power_not_ok    : 1;
2758 		mmr_t	squash          : 1;
2759 		mmr_t	rcv_link_reset  : 1;
2760 		mmr_t	retry_timeout   : 1;
2761 		mmr_t	retry_count     : 8;
2762 		mmr_t	rx_cb_err_count : 8;
2763 		mmr_t	rx_sn_err_count : 8;
2775 	mmr_t	sh_ni1_llp_stat_regval;
2777 		mmr_t	link_reset_state : 4;
2778 		mmr_t	reserved_0       : 60;
2783 	mmr_t	sh_ni1_llp_stat_regval;
2785 		mmr_t	reserved_0       : 60;
2786 		mmr_t	link_reset_state : 4;
2798 	mmr_t	sh_ni1_llp_reset_regval;
2800 		mmr_t	link        : 1;
2801 		mmr_t	warm        : 1;
2802 		mmr_t	reserved_0  : 62;
2807 	mmr_t	sh_ni1_llp_reset_regval;
2809 		mmr_t	reserved_0  : 62;
2810 		mmr_t	warm        : 1;
2811 		mmr_t	link        : 1;
2823 	mmr_t	sh_ni1_llp_reset_en_regval;
2825 		mmr_t	ok          : 1;
2826 		mmr_t	reserved_0  : 63;
2831 	mmr_t	sh_ni1_llp_reset_en_regval;
2833 		mmr_t	reserved_0  : 63;
2834 		mmr_t	ok          : 1;
2846 	mmr_t	sh_ni1_llp_chan_mode_regval;
2848 		mmr_t	bitmode32         : 1;
2849 		mmr_t	ac_encode         : 1;
2850 		mmr_t	enable_tuning     : 1;
2851 		mmr_t	enable_rmt_ft_upd : 1;
2852 		mmr_t	enable_clkquad    : 1;
2853 		mmr_t	reserved_0        : 59;
2858 	mmr_t	sh_ni1_llp_chan_mode_regval;
2860 		mmr_t	reserved_0        : 59;
2861 		mmr_t	enable_clkquad    : 1;
2862 		mmr_t	enable_rmt_ft_upd : 1;
2863 		mmr_t	enable_tuning     : 1;
2864 		mmr_t	ac_encode         : 1;
2865 		mmr_t	bitmode32         : 1;
2877 	mmr_t	sh_ni1_llp_config_regval;
2879 		mmr_t	maxburst    : 10;
2880 		mmr_t	maxretry    : 10;
2881 		mmr_t	nulltimeout : 6;
2882 		mmr_t	ftu_time    : 12;
2883 		mmr_t	reserved_0  : 26;
2888 	mmr_t	sh_ni1_llp_config_regval;
2890 		mmr_t	reserved_0  : 26;
2891 		mmr_t	ftu_time    : 12;
2892 		mmr_t	nulltimeout : 6;
2893 		mmr_t	maxretry    : 10;
2894 		mmr_t	maxburst    : 10;
2905 	mmr_t	sh_ni1_llp_test_ctl_regval;
2907 		mmr_t	pattern        : 40;
2908 		mmr_t	send_test_mode : 2;
2909 		mmr_t	reserved_0     : 2;
2910 		mmr_t	wire_sel       : 6;
2911 		mmr_t	reserved_1     : 2;
2912 		mmr_t	lfsr_mode      : 2;
2913 		mmr_t	noise_mode     : 2;
2914 		mmr_t	armcapture     : 1;
2915 		mmr_t	capturecbonly  : 1;
2916 		mmr_t	sendcberror    : 1;
2917 		mmr_t	sendsnerror    : 1;
2918 		mmr_t	fakesnerror    : 1;
2919 		mmr_t	captured       : 1;
2920 		mmr_t	cberror        : 1;
2921 		mmr_t	reserved_2     : 1;
2926 	mmr_t	sh_ni1_llp_test_ctl_regval;
2928 		mmr_t	reserved_2     : 1;
2929 		mmr_t	cberror        : 1;
2930 		mmr_t	captured       : 1;
2931 		mmr_t	fakesnerror    : 1;
2932 		mmr_t	sendsnerror    : 1;
2933 		mmr_t	sendcberror    : 1;
2934 		mmr_t	capturecbonly  : 1;
2935 		mmr_t	armcapture     : 1;
2936 		mmr_t	noise_mode     : 2;
2937 		mmr_t	lfsr_mode      : 2;
2938 		mmr_t	reserved_1     : 2;
2939 		mmr_t	wire_sel       : 6;
2940 		mmr_t	reserved_0     : 2;
2941 		mmr_t	send_test_mode : 2;
2942 		mmr_t	pattern        : 40;
2954 	mmr_t	sh_ni1_llp_capt_wd1_regval;
2956 		mmr_t	data        : 64;
2961 	mmr_t	sh_ni1_llp_capt_wd1_regval;
2963 		mmr_t	data        : 64;
2975 	mmr_t	sh_ni1_llp_capt_wd2_regval;
2977 		mmr_t	data        : 64;
2982 	mmr_t	sh_ni1_llp_capt_wd2_regval;
2984 		mmr_t	data        : 64;
2996 	mmr_t	sh_ni1_llp_capt_sbcb_regval;
2998 		mmr_t	capturedrcvsbsn  : 16;
2999 		mmr_t	capturedrcvcrc   : 16;
3000 		mmr_t	sentallcberrors  : 1;
3001 		mmr_t	sentallsnerrors  : 1;
3002 		mmr_t	fakedallsnerrors : 1;
3003 		mmr_t	chargeoverflow   : 1;
3004 		mmr_t	chargeunderflow  : 1;
3005 		mmr_t	reserved_0       : 27;
3010 	mmr_t	sh_ni1_llp_capt_sbcb_regval;
3012 		mmr_t	reserved_0       : 27;
3013 		mmr_t	chargeunderflow  : 1;
3014 		mmr_t	chargeoverflow   : 1;
3015 		mmr_t	fakedallsnerrors : 1;
3016 		mmr_t	sentallsnerrors  : 1;
3017 		mmr_t	sentallcberrors  : 1;
3018 		mmr_t	capturedrcvcrc   : 16;
3019 		mmr_t	capturedrcvsbsn  : 16;
3030 	mmr_t	sh_ni1_llp_err_regval;
3032 		mmr_t	rx_sn_err_count : 8;
3033 		mmr_t	rx_cb_err_count : 8;
3034 		mmr_t	retry_count     : 8;
3035 		mmr_t	retry_timeout   : 1;
3036 		mmr_t	rcv_link_reset  : 1;
3037 		mmr_t	squash          : 1;
3038 		mmr_t	power_not_ok    : 1;
3039 		mmr_t	wire_cnt        : 24;
3040 		mmr_t	wire_overflow   : 1;
3041 		mmr_t	reserved_0      : 11;
3046 	mmr_t	sh_ni1_llp_err_regval;
3048 		mmr_t	reserved_0      : 11;
3049 		mmr_t	wire_overflow   : 1;
3050 		mmr_t	wire_cnt        : 24;
3051 		mmr_t	power_not_ok    : 1;
3052 		mmr_t	squash          : 1;
3053 		mmr_t	rcv_link_reset  : 1;
3054 		mmr_t	retry_timeout   : 1;
3055 		mmr_t	retry_count     : 8;
3056 		mmr_t	rx_cb_err_count : 8;
3057 		mmr_t	rx_sn_err_count : 8;
3068 	mmr_t	sh_xnni0_llp_to_fifo02_flow_regval;
3070 		mmr_t	debit_vc0_withhold   : 6;
3071 		mmr_t	reserved_0           : 1;
3072 		mmr_t	debit_vc0_force_cred : 1;
3073 		mmr_t	debit_vc2_withhold   : 6;
3074 		mmr_t	reserved_1           : 1;
3075 		mmr_t	debit_vc2_force_cred : 1;
3076 		mmr_t	reserved_2           : 8;
3077 		mmr_t	credit_vc0_dyn       : 6;
3078 		mmr_t	reserved_3           : 2;
3079 		mmr_t	credit_vc0_cap       : 6;
3080 		mmr_t	reserved_4           : 10;
3081 		mmr_t	credit_vc2_dyn       : 6;
3082 		mmr_t	reserved_5           : 2;
3083 		mmr_t	credit_vc2_cap       : 6;
3084 		mmr_t	reserved_6           : 2;
3089 	mmr_t	sh_xnni0_llp_to_fifo02_flow_regval;
3091 		mmr_t	reserved_6           : 2;
3092 		mmr_t	credit_vc2_cap       : 6;
3093 		mmr_t	reserved_5           : 2;
3094 		mmr_t	credit_vc2_dyn       : 6;
3095 		mmr_t	reserved_4           : 10;
3096 		mmr_t	credit_vc0_cap       : 6;
3097 		mmr_t	reserved_3           : 2;
3098 		mmr_t	credit_vc0_dyn       : 6;
3099 		mmr_t	reserved_2           : 8;
3100 		mmr_t	debit_vc2_force_cred : 1;
3101 		mmr_t	reserved_1           : 1;
3102 		mmr_t	debit_vc2_withhold   : 6;
3103 		mmr_t	debit_vc0_force_cred : 1;
3104 		mmr_t	reserved_0           : 1;
3105 		mmr_t	debit_vc0_withhold   : 6;
3116 	mmr_t	sh_xnni0_llp_to_fifo13_flow_regval;
3118 		mmr_t	debit_vc0_withhold   : 6;
3119 		mmr_t	reserved_0           : 1;
3120 		mmr_t	debit_vc0_force_cred : 1;
3121 		mmr_t	debit_vc2_withhold   : 6;
3122 		mmr_t	reserved_1           : 1;
3123 		mmr_t	debit_vc2_force_cred : 1;
3124 		mmr_t	reserved_2           : 8;
3125 		mmr_t	credit_vc0_dyn       : 6;
3126 		mmr_t	reserved_3           : 2;
3127 		mmr_t	credit_vc0_cap       : 6;
3128 		mmr_t	reserved_4           : 10;
3129 		mmr_t	credit_vc2_dyn       : 6;
3130 		mmr_t	reserved_5           : 2;
3131 		mmr_t	credit_vc2_cap       : 6;
3132 		mmr_t	reserved_6           : 2;
3137 	mmr_t	sh_xnni0_llp_to_fifo13_flow_regval;
3139 		mmr_t	reserved_6           : 2;
3140 		mmr_t	credit_vc2_cap       : 6;
3141 		mmr_t	reserved_5           : 2;
3142 		mmr_t	credit_vc2_dyn       : 6;
3143 		mmr_t	reserved_4           : 10;
3144 		mmr_t	credit_vc0_cap       : 6;
3145 		mmr_t	reserved_3           : 2;
3146 		mmr_t	credit_vc0_dyn       : 6;
3147 		mmr_t	reserved_2           : 8;
3148 		mmr_t	debit_vc2_force_cred : 1;
3149 		mmr_t	reserved_1           : 1;
3150 		mmr_t	debit_vc2_withhold   : 6;
3151 		mmr_t	debit_vc0_force_cred : 1;
3152 		mmr_t	reserved_0           : 1;
3153 		mmr_t	debit_vc0_withhold   : 6;
3164 	mmr_t	sh_xnni0_llp_debit_flow_regval;
3166 		mmr_t	debit_vc0_dyn : 5;
3167 		mmr_t	reserved_0    : 3;
3168 		mmr_t	debit_vc0_cap : 5;
3169 		mmr_t	reserved_1    : 3;
3170 		mmr_t	debit_vc1_dyn : 5;
3171 		mmr_t	reserved_2    : 3;
3172 		mmr_t	debit_vc1_cap : 5;
3173 		mmr_t	reserved_3    : 3;
3174 		mmr_t	debit_vc2_dyn : 5;
3175 		mmr_t	reserved_4    : 3;
3176 		mmr_t	debit_vc2_cap : 5;
3177 		mmr_t	reserved_5    : 3;
3178 		mmr_t	debit_vc3_dyn : 5;
3179 		mmr_t	reserved_6    : 3;
3180 		mmr_t	debit_vc3_cap : 5;
3181 		mmr_t	reserved_7    : 3;
3186 	mmr_t	sh_xnni0_llp_debit_flow_regval;
3188 		mmr_t	reserved_7    : 3;
3189 		mmr_t	debit_vc3_cap : 5;
3190 		mmr_t	reserved_6    : 3;
3191 		mmr_t	debit_vc3_dyn : 5;
3192 		mmr_t	reserved_5    : 3;
3193 		mmr_t	debit_vc2_cap : 5;
3194 		mmr_t	reserved_4    : 3;
3195 		mmr_t	debit_vc2_dyn : 5;
3196 		mmr_t	reserved_3    : 3;
3197 		mmr_t	debit_vc1_cap : 5;
3198 		mmr_t	reserved_2    : 3;
3199 		mmr_t	debit_vc1_dyn : 5;
3200 		mmr_t	reserved_1    : 3;
3201 		mmr_t	debit_vc0_cap : 5;
3202 		mmr_t	reserved_0    : 3;
3203 		mmr_t	debit_vc0_dyn : 5;
3214 	mmr_t	sh_xnni0_link_0_flow_regval;
3216 		mmr_t	debit_vc0_withhold   : 6;
3217 		mmr_t	reserved_0           : 1;
3218 		mmr_t	debit_vc0_force_cred : 1;
3219 		mmr_t	credit_vc0_test      : 7;
3220 		mmr_t	reserved_1           : 1;
3221 		mmr_t	credit_vc0_dyn       : 7;
3222 		mmr_t	reserved_2           : 1;
3223 		mmr_t	credit_vc0_cap       : 7;
3224 		mmr_t	reserved_3           : 33;
3229 	mmr_t	sh_xnni0_link_0_flow_regval;
3231 		mmr_t	reserved_3           : 33;
3232 		mmr_t	credit_vc0_cap       : 7;
3233 		mmr_t	reserved_2           : 1;
3234 		mmr_t	credit_vc0_dyn       : 7;
3235 		mmr_t	reserved_1           : 1;
3236 		mmr_t	credit_vc0_test      : 7;
3237 		mmr_t	debit_vc0_force_cred : 1;
3238 		mmr_t	reserved_0           : 1;
3239 		mmr_t	debit_vc0_withhold   : 6;
3250 	mmr_t	sh_xnni0_link_1_flow_regval;
3252 		mmr_t	debit_vc1_withhold   : 6;
3253 		mmr_t	reserved_0           : 1;
3254 		mmr_t	debit_vc1_force_cred : 1;
3255 		mmr_t	credit_vc1_test      : 7;
3256 		mmr_t	reserved_1           : 1;
3257 		mmr_t	credit_vc1_dyn       : 7;
3258 		mmr_t	reserved_2           : 1;
3259 		mmr_t	credit_vc1_cap       : 7;
3260 		mmr_t	reserved_3           : 33;
3265 	mmr_t	sh_xnni0_link_1_flow_regval;
3267 		mmr_t	reserved_3           : 33;
3268 		mmr_t	credit_vc1_cap       : 7;
3269 		mmr_t	reserved_2           : 1;
3270 		mmr_t	credit_vc1_dyn       : 7;
3271 		mmr_t	reserved_1           : 1;
3272 		mmr_t	credit_vc1_test      : 7;
3273 		mmr_t	debit_vc1_force_cred : 1;
3274 		mmr_t	reserved_0           : 1;
3275 		mmr_t	debit_vc1_withhold   : 6;
3286 	mmr_t	sh_xnni0_link_2_flow_regval;
3288 		mmr_t	debit_vc2_withhold   : 6;
3289 		mmr_t	reserved_0           : 1;
3290 		mmr_t	debit_vc2_force_cred : 1;
3291 		mmr_t	credit_vc2_test      : 7;
3292 		mmr_t	reserved_1           : 1;
3293 		mmr_t	credit_vc2_dyn       : 7;
3294 		mmr_t	reserved_2           : 1;
3295 		mmr_t	credit_vc2_cap       : 7;
3296 		mmr_t	reserved_3           : 33;
3301 	mmr_t	sh_xnni0_link_2_flow_regval;
3303 		mmr_t	reserved_3           : 33;
3304 		mmr_t	credit_vc2_cap       : 7;
3305 		mmr_t	reserved_2           : 1;
3306 		mmr_t	credit_vc2_dyn       : 7;
3307 		mmr_t	reserved_1           : 1;
3308 		mmr_t	credit_vc2_test      : 7;
3309 		mmr_t	debit_vc2_force_cred : 1;
3310 		mmr_t	reserved_0           : 1;
3311 		mmr_t	debit_vc2_withhold   : 6;
3322 	mmr_t	sh_xnni0_link_3_flow_regval;
3324 		mmr_t	debit_vc3_withhold   : 6;
3325 		mmr_t	reserved_0           : 1;
3326 		mmr_t	debit_vc3_force_cred : 1;
3327 		mmr_t	credit_vc3_test      : 7;
3328 		mmr_t	reserved_1           : 1;
3329 		mmr_t	credit_vc3_dyn       : 7;
3330 		mmr_t	reserved_2           : 1;
3331 		mmr_t	credit_vc3_cap       : 7;
3332 		mmr_t	reserved_3           : 33;
3337 	mmr_t	sh_xnni0_link_3_flow_regval;
3339 		mmr_t	reserved_3           : 33;
3340 		mmr_t	credit_vc3_cap       : 7;
3341 		mmr_t	reserved_2           : 1;
3342 		mmr_t	credit_vc3_dyn       : 7;
3343 		mmr_t	reserved_1           : 1;
3344 		mmr_t	credit_vc3_test      : 7;
3345 		mmr_t	debit_vc3_force_cred : 1;
3346 		mmr_t	reserved_0           : 1;
3347 		mmr_t	debit_vc3_withhold   : 6;
3358 	mmr_t	sh_xnni1_llp_to_fifo02_flow_regval;
3360 		mmr_t	debit_vc0_withhold   : 6;
3361 		mmr_t	reserved_0           : 1;
3362 		mmr_t	debit_vc0_force_cred : 1;
3363 		mmr_t	debit_vc2_withhold   : 6;
3364 		mmr_t	reserved_1           : 1;
3365 		mmr_t	debit_vc2_force_cred : 1;
3366 		mmr_t	reserved_2           : 8;
3367 		mmr_t	credit_vc0_dyn       : 6;
3368 		mmr_t	reserved_3           : 2;
3369 		mmr_t	credit_vc0_cap       : 6;
3370 		mmr_t	reserved_4           : 10;
3371 		mmr_t	credit_vc2_dyn       : 6;
3372 		mmr_t	reserved_5           : 2;
3373 		mmr_t	credit_vc2_cap       : 6;
3374 		mmr_t	reserved_6           : 2;
3379 	mmr_t	sh_xnni1_llp_to_fifo02_flow_regval;
3381 		mmr_t	reserved_6           : 2;
3382 		mmr_t	credit_vc2_cap       : 6;
3383 		mmr_t	reserved_5           : 2;
3384 		mmr_t	credit_vc2_dyn       : 6;
3385 		mmr_t	reserved_4           : 10;
3386 		mmr_t	credit_vc0_cap       : 6;
3387 		mmr_t	reserved_3           : 2;
3388 		mmr_t	credit_vc0_dyn       : 6;
3389 		mmr_t	reserved_2           : 8;
3390 		mmr_t	debit_vc2_force_cred : 1;
3391 		mmr_t	reserved_1           : 1;
3392 		mmr_t	debit_vc2_withhold   : 6;
3393 		mmr_t	debit_vc0_force_cred : 1;
3394 		mmr_t	reserved_0           : 1;
3395 		mmr_t	debit_vc0_withhold   : 6;
3406 	mmr_t	sh_xnni1_llp_to_fifo13_flow_regval;
3408 		mmr_t	debit_vc0_withhold   : 6;
3409 		mmr_t	reserved_0           : 1;
3410 		mmr_t	debit_vc0_force_cred : 1;
3411 		mmr_t	debit_vc2_withhold   : 6;
3412 		mmr_t	reserved_1           : 1;
3413 		mmr_t	debit_vc2_force_cred : 1;
3414 		mmr_t	reserved_2           : 8;
3415 		mmr_t	credit_vc0_dyn       : 6;
3416 		mmr_t	reserved_3           : 2;
3417 		mmr_t	credit_vc0_cap       : 6;
3418 		mmr_t	reserved_4           : 10;
3419 		mmr_t	credit_vc2_dyn       : 6;
3420 		mmr_t	reserved_5           : 2;
3421 		mmr_t	credit_vc2_cap       : 6;
3422 		mmr_t	reserved_6           : 2;
3427 	mmr_t	sh_xnni1_llp_to_fifo13_flow_regval;
3429 		mmr_t	reserved_6           : 2;
3430 		mmr_t	credit_vc2_cap       : 6;
3431 		mmr_t	reserved_5           : 2;
3432 		mmr_t	credit_vc2_dyn       : 6;
3433 		mmr_t	reserved_4           : 10;
3434 		mmr_t	credit_vc0_cap       : 6;
3435 		mmr_t	reserved_3           : 2;
3436 		mmr_t	credit_vc0_dyn       : 6;
3437 		mmr_t	reserved_2           : 8;
3438 		mmr_t	debit_vc2_force_cred : 1;
3439 		mmr_t	reserved_1           : 1;
3440 		mmr_t	debit_vc2_withhold   : 6;
3441 		mmr_t	debit_vc0_force_cred : 1;
3442 		mmr_t	reserved_0           : 1;
3443 		mmr_t	debit_vc0_withhold   : 6;
3454 	mmr_t	sh_xnni1_llp_debit_flow_regval;
3456 		mmr_t	debit_vc0_dyn : 5;
3457 		mmr_t	reserved_0    : 3;
3458 		mmr_t	debit_vc0_cap : 5;
3459 		mmr_t	reserved_1    : 3;
3460 		mmr_t	debit_vc1_dyn : 5;
3461 		mmr_t	reserved_2    : 3;
3462 		mmr_t	debit_vc1_cap : 5;
3463 		mmr_t	reserved_3    : 3;
3464 		mmr_t	debit_vc2_dyn : 5;
3465 		mmr_t	reserved_4    : 3;
3466 		mmr_t	debit_vc2_cap : 5;
3467 		mmr_t	reserved_5    : 3;
3468 		mmr_t	debit_vc3_dyn : 5;
3469 		mmr_t	reserved_6    : 3;
3470 		mmr_t	debit_vc3_cap : 5;
3471 		mmr_t	reserved_7    : 3;
3476 	mmr_t	sh_xnni1_llp_debit_flow_regval;
3478 		mmr_t	reserved_7    : 3;
3479 		mmr_t	debit_vc3_cap : 5;
3480 		mmr_t	reserved_6    : 3;
3481 		mmr_t	debit_vc3_dyn : 5;
3482 		mmr_t	reserved_5    : 3;
3483 		mmr_t	debit_vc2_cap : 5;
3484 		mmr_t	reserved_4    : 3;
3485 		mmr_t	debit_vc2_dyn : 5;
3486 		mmr_t	reserved_3    : 3;
3487 		mmr_t	debit_vc1_cap : 5;
3488 		mmr_t	reserved_2    : 3;
3489 		mmr_t	debit_vc1_dyn : 5;
3490 		mmr_t	reserved_1    : 3;
3491 		mmr_t	debit_vc0_cap : 5;
3492 		mmr_t	reserved_0    : 3;
3493 		mmr_t	debit_vc0_dyn : 5;
3504 	mmr_t	sh_xnni1_link_0_flow_regval;
3506 		mmr_t	debit_vc0_withhold   : 6;
3507 		mmr_t	reserved_0           : 1;
3508 		mmr_t	debit_vc0_force_cred : 1;
3509 		mmr_t	credit_vc0_test      : 7;
3510 		mmr_t	reserved_1           : 1;
3511 		mmr_t	credit_vc0_dyn       : 7;
3512 		mmr_t	reserved_2           : 1;
3513 		mmr_t	credit_vc0_cap       : 7;
3514 		mmr_t	reserved_3           : 33;
3519 	mmr_t	sh_xnni1_link_0_flow_regval;
3521 		mmr_t	reserved_3           : 33;
3522 		mmr_t	credit_vc0_cap       : 7;
3523 		mmr_t	reserved_2           : 1;
3524 		mmr_t	credit_vc0_dyn       : 7;
3525 		mmr_t	reserved_1           : 1;
3526 		mmr_t	credit_vc0_test      : 7;
3527 		mmr_t	debit_vc0_force_cred : 1;
3528 		mmr_t	reserved_0           : 1;
3529 		mmr_t	debit_vc0_withhold   : 6;
3540 	mmr_t	sh_xnni1_link_1_flow_regval;
3542 		mmr_t	debit_vc1_withhold   : 6;
3543 		mmr_t	reserved_0           : 1;
3544 		mmr_t	debit_vc1_force_cred : 1;
3545 		mmr_t	credit_vc1_test      : 7;
3546 		mmr_t	reserved_1           : 1;
3547 		mmr_t	credit_vc1_dyn       : 7;
3548 		mmr_t	reserved_2           : 1;
3549 		mmr_t	credit_vc1_cap       : 7;
3550 		mmr_t	reserved_3           : 33;
3555 	mmr_t	sh_xnni1_link_1_flow_regval;
3557 		mmr_t	reserved_3           : 33;
3558 		mmr_t	credit_vc1_cap       : 7;
3559 		mmr_t	reserved_2           : 1;
3560 		mmr_t	credit_vc1_dyn       : 7;
3561 		mmr_t	reserved_1           : 1;
3562 		mmr_t	credit_vc1_test      : 7;
3563 		mmr_t	debit_vc1_force_cred : 1;
3564 		mmr_t	reserved_0           : 1;
3565 		mmr_t	debit_vc1_withhold   : 6;
3576 	mmr_t	sh_xnni1_link_2_flow_regval;
3578 		mmr_t	debit_vc2_withhold   : 6;
3579 		mmr_t	reserved_0           : 1;
3580 		mmr_t	debit_vc2_force_cred : 1;
3581 		mmr_t	credit_vc2_test      : 7;
3582 		mmr_t	reserved_1           : 1;
3583 		mmr_t	credit_vc2_dyn       : 7;
3584 		mmr_t	reserved_2           : 1;
3585 		mmr_t	credit_vc2_cap       : 7;
3586 		mmr_t	reserved_3           : 33;
3591 	mmr_t	sh_xnni1_link_2_flow_regval;
3593 		mmr_t	reserved_3           : 33;
3594 		mmr_t	credit_vc2_cap       : 7;
3595 		mmr_t	reserved_2           : 1;
3596 		mmr_t	credit_vc2_dyn       : 7;
3597 		mmr_t	reserved_1           : 1;
3598 		mmr_t	credit_vc2_test      : 7;
3599 		mmr_t	debit_vc2_force_cred : 1;
3600 		mmr_t	reserved_0           : 1;
3601 		mmr_t	debit_vc2_withhold   : 6;
3612 	mmr_t	sh_xnni1_link_3_flow_regval;
3614 		mmr_t	debit_vc3_withhold   : 6;
3615 		mmr_t	reserved_0           : 1;
3616 		mmr_t	debit_vc3_force_cred : 1;
3617 		mmr_t	credit_vc3_test      : 7;
3618 		mmr_t	reserved_1           : 1;
3619 		mmr_t	credit_vc3_dyn       : 7;
3620 		mmr_t	reserved_2           : 1;
3621 		mmr_t	credit_vc3_cap       : 7;
3622 		mmr_t	reserved_3           : 33;
3627 	mmr_t	sh_xnni1_link_3_flow_regval;
3629 		mmr_t	reserved_3           : 33;
3630 		mmr_t	credit_vc3_cap       : 7;
3631 		mmr_t	reserved_2           : 1;
3632 		mmr_t	credit_vc3_dyn       : 7;
3633 		mmr_t	reserved_1           : 1;
3634 		mmr_t	credit_vc3_test      : 7;
3635 		mmr_t	debit_vc3_force_cred : 1;
3636 		mmr_t	reserved_0           : 1;
3637 		mmr_t	debit_vc3_withhold   : 6;
3649 	mmr_t	sh_iilb_local_table_regval;
3651 		mmr_t	dir0        : 4;
3652 		mmr_t	v0          : 1;
3653 		mmr_t	ni_sel0     : 1;
3654 		mmr_t	reserved_0  : 57;
3655 		mmr_t	valid       : 1;
3660 	mmr_t	sh_iilb_local_table_regval;
3662 		mmr_t	valid       : 1;
3663 		mmr_t	reserved_0  : 57;
3664 		mmr_t	ni_sel0     : 1;
3665 		mmr_t	v0          : 1;
3666 		mmr_t	dir0        : 4;
3678 	mmr_t	sh_iilb_global_table_regval;
3680 		mmr_t	dir0        : 4;
3681 		mmr_t	v0          : 1;
3682 		mmr_t	ni_sel0     : 1;
3683 		mmr_t	reserved_0  : 57;
3684 		mmr_t	valid       : 1;
3689 	mmr_t	sh_iilb_global_table_regval;
3691 		mmr_t	valid       : 1;
3692 		mmr_t	reserved_0  : 57;
3693 		mmr_t	ni_sel0     : 1;
3694 		mmr_t	v0          : 1;
3695 		mmr_t	dir0        : 4;
3707 	mmr_t	sh_iilb_over_ride_table_regval;
3709 		mmr_t	dir0        : 4;
3710 		mmr_t	v0          : 1;
3711 		mmr_t	ni_sel0     : 1;
3712 		mmr_t	reserved_0  : 57;
3713 		mmr_t	enable      : 1;
3718 	mmr_t	sh_iilb_over_ride_table_regval;
3720 		mmr_t	enable      : 1;
3721 		mmr_t	reserved_0  : 57;
3722 		mmr_t	ni_sel0     : 1;
3723 		mmr_t	v0          : 1;
3724 		mmr_t	dir0        : 4;
3736 	mmr_t	sh_iilb_rsp_plane_hint_regval;
3738 		mmr_t	reserved_0  : 64;
3743 	mmr_t	sh_iilb_rsp_plane_hint_regval;
3745 		mmr_t	reserved_0  : 64;
3757 	mmr_t	sh_pi_local_table_regval;
3759 		mmr_t	dir0        : 4;
3760 		mmr_t	v0          : 1;
3761 		mmr_t	ni_sel0     : 1;
3762 		mmr_t	reserved_0  : 2;
3763 		mmr_t	dir1        : 4;
3764 		mmr_t	v1          : 1;
3765 		mmr_t	ni_sel1     : 1;
3766 		mmr_t	reserved_1  : 49;
3767 		mmr_t	valid       : 1;
3772 	mmr_t	sh_pi_local_table_regval;
3774 		mmr_t	valid       : 1;
3775 		mmr_t	reserved_1  : 49;
3776 		mmr_t	ni_sel1     : 1;
3777 		mmr_t	v1          : 1;
3778 		mmr_t	dir1        : 4;
3779 		mmr_t	reserved_0  : 2;
3780 		mmr_t	ni_sel0     : 1;
3781 		mmr_t	v0          : 1;
3782 		mmr_t	dir0        : 4;
3794 	mmr_t	sh_pi_global_table_regval;
3796 		mmr_t	dir0        : 4;
3797 		mmr_t	v0          : 1;
3798 		mmr_t	ni_sel0     : 1;
3799 		mmr_t	reserved_0  : 2;
3800 		mmr_t	dir1        : 4;
3801 		mmr_t	v1          : 1;
3802 		mmr_t	ni_sel1     : 1;
3803 		mmr_t	reserved_1  : 49;
3804 		mmr_t	valid       : 1;
3809 	mmr_t	sh_pi_global_table_regval;
3811 		mmr_t	valid       : 1;
3812 		mmr_t	reserved_1  : 49;
3813 		mmr_t	ni_sel1     : 1;
3814 		mmr_t	v1          : 1;
3815 		mmr_t	dir1        : 4;
3816 		mmr_t	reserved_0  : 2;
3817 		mmr_t	ni_sel0     : 1;
3818 		mmr_t	v0          : 1;
3819 		mmr_t	dir0        : 4;
3831 	mmr_t	sh_pi_over_ride_table_regval;
3833 		mmr_t	dir0        : 4;
3834 		mmr_t	v0          : 1;
3835 		mmr_t	ni_sel0     : 1;
3836 		mmr_t	reserved_0  : 2;
3837 		mmr_t	dir1        : 4;
3838 		mmr_t	v1          : 1;
3839 		mmr_t	ni_sel1     : 1;
3840 		mmr_t	reserved_1  : 49;
3841 		mmr_t	enable      : 1;
3846 	mmr_t	sh_pi_over_ride_table_regval;
3848 		mmr_t	enable      : 1;
3849 		mmr_t	reserved_1  : 49;
3850 		mmr_t	ni_sel1     : 1;
3851 		mmr_t	v1          : 1;
3852 		mmr_t	dir1        : 4;
3853 		mmr_t	reserved_0  : 2;
3854 		mmr_t	ni_sel0     : 1;
3855 		mmr_t	v0          : 1;
3856 		mmr_t	dir0        : 4;
3868 	mmr_t	sh_pi_rsp_plane_hint_regval;
3870 		mmr_t	invert      : 1;
3871 		mmr_t	reserved_0  : 63;
3876 	mmr_t	sh_pi_rsp_plane_hint_regval;
3878 		mmr_t	reserved_0  : 63;
3879 		mmr_t	invert      : 1;
3891 	mmr_t	sh_ni0_local_table_regval;
3893 		mmr_t	dir0        : 4;
3894 		mmr_t	v0          : 1;
3895 		mmr_t	reserved_0  : 58;
3896 		mmr_t	valid       : 1;
3901 	mmr_t	sh_ni0_local_table_regval;
3903 		mmr_t	valid       : 1;
3904 		mmr_t	reserved_0  : 58;
3905 		mmr_t	v0          : 1;
3906 		mmr_t	dir0        : 4;
3918 	mmr_t	sh_ni0_global_table_regval;
3920 		mmr_t	dir0        : 4;
3921 		mmr_t	v0          : 1;
3922 		mmr_t	reserved_0  : 58;
3923 		mmr_t	valid       : 1;
3928 	mmr_t	sh_ni0_global_table_regval;
3930 		mmr_t	valid       : 1;
3931 		mmr_t	reserved_0  : 58;
3932 		mmr_t	v0          : 1;
3933 		mmr_t	dir0        : 4;
3945 	mmr_t	sh_ni0_over_ride_table_regval;
3947 		mmr_t	dir0        : 4;
3948 		mmr_t	v0          : 1;
3949 		mmr_t	reserved_0  : 58;
3950 		mmr_t	enable      : 1;
3955 	mmr_t	sh_ni0_over_ride_table_regval;
3957 		mmr_t	enable      : 1;
3958 		mmr_t	reserved_0  : 58;
3959 		mmr_t	v0          : 1;
3960 		mmr_t	dir0        : 4;
3972 	mmr_t	sh_ni0_rsp_plane_hint_regval;
3974 		mmr_t	reserved_0  : 64;
3979 	mmr_t	sh_ni0_rsp_plane_hint_regval;
3981 		mmr_t	reserved_0  : 64;
3993 	mmr_t	sh_ni1_local_table_regval;
3995 		mmr_t	dir0        : 4;
3996 		mmr_t	v0          : 1;
3997 		mmr_t	reserved_0  : 58;
3998 		mmr_t	valid       : 1;
4003 	mmr_t	sh_ni1_local_table_regval;
4005 		mmr_t	valid       : 1;
4006 		mmr_t	reserved_0  : 58;
4007 		mmr_t	v0          : 1;
4008 		mmr_t	dir0        : 4;
4020 	mmr_t	sh_ni1_global_table_regval;
4022 		mmr_t	dir0        : 4;
4023 		mmr_t	v0          : 1;
4024 		mmr_t	reserved_0  : 58;
4025 		mmr_t	valid       : 1;
4030 	mmr_t	sh_ni1_global_table_regval;
4032 		mmr_t	valid       : 1;
4033 		mmr_t	reserved_0  : 58;
4034 		mmr_t	v0          : 1;
4035 		mmr_t	dir0        : 4;
4047 	mmr_t	sh_ni1_over_ride_table_regval;
4049 		mmr_t	dir0        : 4;
4050 		mmr_t	v0          : 1;
4051 		mmr_t	reserved_0  : 58;
4052 		mmr_t	enable      : 1;
4057 	mmr_t	sh_ni1_over_ride_table_regval;
4059 		mmr_t	enable      : 1;
4060 		mmr_t	reserved_0  : 58;
4061 		mmr_t	v0          : 1;
4062 		mmr_t	dir0        : 4;
4074 	mmr_t	sh_ni1_rsp_plane_hint_regval;
4076 		mmr_t	reserved_0  : 64;
4081 	mmr_t	sh_ni1_rsp_plane_hint_regval;
4083 		mmr_t	reserved_0  : 64;
4095 	mmr_t	sh_md_local_table_regval;
4097 		mmr_t	dir0        : 4;
4098 		mmr_t	v0          : 1;
4099 		mmr_t	ni_sel0     : 1;
4100 		mmr_t	reserved_0  : 2;
4101 		mmr_t	dir1        : 4;
4102 		mmr_t	v1          : 1;
4103 		mmr_t	ni_sel1     : 1;
4104 		mmr_t	reserved_1  : 49;
4105 		mmr_t	valid       : 1;
4110 	mmr_t	sh_md_local_table_regval;
4112 		mmr_t	valid       : 1;
4113 		mmr_t	reserved_1  : 49;
4114 		mmr_t	ni_sel1     : 1;
4115 		mmr_t	v1          : 1;
4116 		mmr_t	dir1        : 4;
4117 		mmr_t	reserved_0  : 2;
4118 		mmr_t	ni_sel0     : 1;
4119 		mmr_t	v0          : 1;
4120 		mmr_t	dir0        : 4;
4132 	mmr_t	sh_md_global_table_regval;
4134 		mmr_t	dir0        : 4;
4135 		mmr_t	v0          : 1;
4136 		mmr_t	ni_sel0     : 1;
4137 		mmr_t	reserved_0  : 2;
4138 		mmr_t	dir1        : 4;
4139 		mmr_t	v1          : 1;
4140 		mmr_t	ni_sel1     : 1;
4141 		mmr_t	reserved_1  : 49;
4142 		mmr_t	valid       : 1;
4147 	mmr_t	sh_md_global_table_regval;
4149 		mmr_t	valid       : 1;
4150 		mmr_t	reserved_1  : 49;
4151 		mmr_t	ni_sel1     : 1;
4152 		mmr_t	v1          : 1;
4153 		mmr_t	dir1        : 4;
4154 		mmr_t	reserved_0  : 2;
4155 		mmr_t	ni_sel0     : 1;
4156 		mmr_t	v0          : 1;
4157 		mmr_t	dir0        : 4;
4169 	mmr_t	sh_md_over_ride_table_regval;
4171 		mmr_t	dir0        : 4;
4172 		mmr_t	v0          : 1;
4173 		mmr_t	ni_sel0     : 1;
4174 		mmr_t	reserved_0  : 2;
4175 		mmr_t	dir1        : 4;
4176 		mmr_t	v1          : 1;
4177 		mmr_t	ni_sel1     : 1;
4178 		mmr_t	reserved_1  : 49;
4179 		mmr_t	enable      : 1;
4184 	mmr_t	sh_md_over_ride_table_regval;
4186 		mmr_t	enable      : 1;
4187 		mmr_t	reserved_1  : 49;
4188 		mmr_t	ni_sel1     : 1;
4189 		mmr_t	v1          : 1;
4190 		mmr_t	dir1        : 4;
4191 		mmr_t	reserved_0  : 2;
4192 		mmr_t	ni_sel0     : 1;
4193 		mmr_t	v0          : 1;
4194 		mmr_t	dir0        : 4;
4206 	mmr_t	sh_md_rsp_plane_hint_regval;
4208 		mmr_t	invert      : 1;
4209 		mmr_t	reserved_0  : 63;
4214 	mmr_t	sh_md_rsp_plane_hint_regval;
4216 		mmr_t	reserved_0  : 63;
4217 		mmr_t	invert      : 1;
4229 	mmr_t	sh_lb_liq_ctl_regval;
4231 		mmr_t	liq_req_ctl        : 5;
4232 		mmr_t	reserved_0         : 3;
4233 		mmr_t	liq_rpl_ctl        : 4;
4234 		mmr_t	reserved_1         : 4;
4235 		mmr_t	force_rq_credit    : 1;
4236 		mmr_t	force_rp_credit    : 1;
4237 		mmr_t	force_linvv_credit : 1;
4238 		mmr_t	reserved_2         : 45;
4243 	mmr_t	sh_lb_liq_ctl_regval;
4245 		mmr_t	reserved_2         : 45;
4246 		mmr_t	force_linvv_credit : 1;
4247 		mmr_t	force_rp_credit    : 1;
4248 		mmr_t	force_rq_credit    : 1;
4249 		mmr_t	reserved_1         : 4;
4250 		mmr_t	liq_rpl_ctl        : 4;
4251 		mmr_t	reserved_0         : 3;
4252 		mmr_t	liq_req_ctl        : 5;
4264 	mmr_t	sh_lb_loq_ctl_regval;
4266 		mmr_t	loq_req_ctl : 1;
4267 		mmr_t	loq_rpl_ctl : 1;
4268 		mmr_t	reserved_0  : 62;
4273 	mmr_t	sh_lb_loq_ctl_regval;
4275 		mmr_t	reserved_0  : 62;
4276 		mmr_t	loq_rpl_ctl : 1;
4277 		mmr_t	loq_req_ctl : 1;
4289 	mmr_t	sh_lb_max_rep_credit_cnt_regval;
4291 		mmr_t	max_cnt     : 5;
4292 		mmr_t	reserved_0  : 59;
4297 	mmr_t	sh_lb_max_rep_credit_cnt_regval;
4299 		mmr_t	reserved_0  : 59;
4300 		mmr_t	max_cnt     : 5;
4312 	mmr_t	sh_lb_max_req_credit_cnt_regval;
4314 		mmr_t	max_cnt     : 5;
4315 		mmr_t	reserved_0  : 59;
4320 	mmr_t	sh_lb_max_req_credit_cnt_regval;
4322 		mmr_t	reserved_0  : 59;
4323 		mmr_t	max_cnt     : 5;
4335 	mmr_t	sh_pio_time_out_regval;
4337 		mmr_t	value       : 16;
4338 		mmr_t	reserved_0  : 48;
4343 	mmr_t	sh_pio_time_out_regval;
4345 		mmr_t	reserved_0  : 48;
4346 		mmr_t	value       : 16;
4358 	mmr_t	sh_pio_nack_reset_regval;
4360 		mmr_t	pulse       : 1;
4361 		mmr_t	reserved_0  : 63;
4366 	mmr_t	sh_pio_nack_reset_regval;
4368 		mmr_t	reserved_0  : 63;
4369 		mmr_t	pulse       : 1;
4381 	mmr_t	sh_conveyor_belt_time_out_regval;
4383 		mmr_t	value       : 12;
4384 		mmr_t	reserved_0  : 52;
4389 	mmr_t	sh_conveyor_belt_time_out_regval;
4391 		mmr_t	reserved_0  : 52;
4392 		mmr_t	value       : 12;
4404 	mmr_t	sh_lb_credit_status_regval;
4406 		mmr_t	liq_rq_credit : 5;
4407 		mmr_t	reserved_0    : 1;
4408 		mmr_t	liq_rp_credit : 4;
4409 		mmr_t	reserved_1    : 2;
4410 		mmr_t	linvv_credit  : 6;
4411 		mmr_t	loq_rq_credit : 5;
4412 		mmr_t	loq_rp_credit : 5;
4413 		mmr_t	reserved_2    : 36;
4418 	mmr_t	sh_lb_credit_status_regval;
4420 		mmr_t	reserved_2    : 36;
4421 		mmr_t	loq_rp_credit : 5;
4422 		mmr_t	loq_rq_credit : 5;
4423 		mmr_t	linvv_credit  : 6;
4424 		mmr_t	reserved_1    : 2;
4425 		mmr_t	liq_rp_credit : 4;
4426 		mmr_t	reserved_0    : 1;
4427 		mmr_t	liq_rq_credit : 5;
4439 	mmr_t	sh_lb_debug_local_sel_regval;
4441 		mmr_t	nibble0_chiplet_sel : 3;
4442 		mmr_t	reserved_0          : 1;
4443 		mmr_t	nibble0_nibble_sel  : 3;
4444 		mmr_t	reserved_1          : 1;
4445 		mmr_t	nibble1_chiplet_sel : 3;
4446 		mmr_t	reserved_2          : 1;
4447 		mmr_t	nibble1_nibble_sel  : 3;
4448 		mmr_t	reserved_3          : 1;
4449 		mmr_t	nibble2_chiplet_sel : 3;
4450 		mmr_t	reserved_4          : 1;
4451 		mmr_t	nibble2_nibble_sel  : 3;
4452 		mmr_t	reserved_5          : 1;
4453 		mmr_t	nibble3_chiplet_sel : 3;
4454 		mmr_t	reserved_6          : 1;
4455 		mmr_t	nibble3_nibble_sel  : 3;
4456 		mmr_t	reserved_7          : 1;
4457 		mmr_t	nibble4_chiplet_sel : 3;
4458 		mmr_t	reserved_8          : 1;
4459 		mmr_t	nibble4_nibble_sel  : 3;
4460 		mmr_t	reserved_9          : 1;
4461 		mmr_t	nibble5_chiplet_sel : 3;
4462 		mmr_t	reserved_10         : 1;
4463 		mmr_t	nibble5_nibble_sel  : 3;
4464 		mmr_t	reserved_11         : 1;
4465 		mmr_t	nibble6_chiplet_sel : 3;
4466 		mmr_t	reserved_12         : 1;
4467 		mmr_t	nibble6_nibble_sel  : 3;
4468 		mmr_t	reserved_13         : 1;
4469 		mmr_t	nibble7_chiplet_sel : 3;
4470 		mmr_t	reserved_14         : 1;
4471 		mmr_t	nibble7_nibble_sel  : 3;
4472 		mmr_t	trigger_enable      : 1;
4477 	mmr_t	sh_lb_debug_local_sel_regval;
4479 		mmr_t	trigger_enable      : 1;
4480 		mmr_t	nibble7_nibble_sel  : 3;
4481 		mmr_t	reserved_14         : 1;
4482 		mmr_t	nibble7_chiplet_sel : 3;
4483 		mmr_t	reserved_13         : 1;
4484 		mmr_t	nibble6_nibble_sel  : 3;
4485 		mmr_t	reserved_12         : 1;
4486 		mmr_t	nibble6_chiplet_sel : 3;
4487 		mmr_t	reserved_11         : 1;
4488 		mmr_t	nibble5_nibble_sel  : 3;
4489 		mmr_t	reserved_10         : 1;
4490 		mmr_t	nibble5_chiplet_sel : 3;
4491 		mmr_t	reserved_9          : 1;
4492 		mmr_t	nibble4_nibble_sel  : 3;
4493 		mmr_t	reserved_8          : 1;
4494 		mmr_t	nibble4_chiplet_sel : 3;
4495 		mmr_t	reserved_7          : 1;
4496 		mmr_t	nibble3_nibble_sel  : 3;
4497 		mmr_t	reserved_6          : 1;
4498 		mmr_t	nibble3_chiplet_sel : 3;
4499 		mmr_t	reserved_5          : 1;
4500 		mmr_t	nibble2_nibble_sel  : 3;
4501 		mmr_t	reserved_4          : 1;
4502 		mmr_t	nibble2_chiplet_sel : 3;
4503 		mmr_t	reserved_3          : 1;
4504 		mmr_t	nibble1_nibble_sel  : 3;
4505 		mmr_t	reserved_2          : 1;
4506 		mmr_t	nibble1_chiplet_sel : 3;
4507 		mmr_t	reserved_1          : 1;
4508 		mmr_t	nibble0_nibble_sel  : 3;
4509 		mmr_t	reserved_0          : 1;
4510 		mmr_t	nibble0_chiplet_sel : 3;
4522 	mmr_t	sh_lb_debug_perf_sel_regval;
4524 		mmr_t	nibble0_chiplet_sel : 3;
4525 		mmr_t	reserved_0          : 1;
4526 		mmr_t	nibble0_nibble_sel  : 3;
4527 		mmr_t	reserved_1          : 1;
4528 		mmr_t	nibble1_chiplet_sel : 3;
4529 		mmr_t	reserved_2          : 1;
4530 		mmr_t	nibble1_nibble_sel  : 3;
4531 		mmr_t	reserved_3          : 1;
4532 		mmr_t	nibble2_chiplet_sel : 3;
4533 		mmr_t	reserved_4          : 1;
4534 		mmr_t	nibble2_nibble_sel  : 3;
4535 		mmr_t	reserved_5          : 1;
4536 		mmr_t	nibble3_chiplet_sel : 3;
4537 		mmr_t	reserved_6          : 1;
4538 		mmr_t	nibble3_nibble_sel  : 3;
4539 		mmr_t	reserved_7          : 1;
4540 		mmr_t	nibble4_chiplet_sel : 3;
4541 		mmr_t	reserved_8          : 1;
4542 		mmr_t	nibble4_nibble_sel  : 3;
4543 		mmr_t	reserved_9          : 1;
4544 		mmr_t	nibble5_chiplet_sel : 3;
4545 		mmr_t	reserved_10         : 1;
4546 		mmr_t	nibble5_nibble_sel  : 3;
4547 		mmr_t	reserved_11         : 1;
4548 		mmr_t	nibble6_chiplet_sel : 3;
4549 		mmr_t	reserved_12         : 1;
4550 		mmr_t	nibble6_nibble_sel  : 3;
4551 		mmr_t	reserved_13         : 1;
4552 		mmr_t	nibble7_chiplet_sel : 3;
4553 		mmr_t	reserved_14         : 1;
4554 		mmr_t	nibble7_nibble_sel  : 3;
4555 		mmr_t	reserved_15         : 1;
4560 	mmr_t	sh_lb_debug_perf_sel_regval;
4562 		mmr_t	reserved_15         : 1;
4563 		mmr_t	nibble7_nibble_sel  : 3;
4564 		mmr_t	reserved_14         : 1;
4565 		mmr_t	nibble7_chiplet_sel : 3;
4566 		mmr_t	reserved_13         : 1;
4567 		mmr_t	nibble6_nibble_sel  : 3;
4568 		mmr_t	reserved_12         : 1;
4569 		mmr_t	nibble6_chiplet_sel : 3;
4570 		mmr_t	reserved_11         : 1;
4571 		mmr_t	nibble5_nibble_sel  : 3;
4572 		mmr_t	reserved_10         : 1;
4573 		mmr_t	nibble5_chiplet_sel : 3;
4574 		mmr_t	reserved_9          : 1;
4575 		mmr_t	nibble4_nibble_sel  : 3;
4576 		mmr_t	reserved_8          : 1;
4577 		mmr_t	nibble4_chiplet_sel : 3;
4578 		mmr_t	reserved_7          : 1;
4579 		mmr_t	nibble3_nibble_sel  : 3;
4580 		mmr_t	reserved_6          : 1;
4581 		mmr_t	nibble3_chiplet_sel : 3;
4582 		mmr_t	reserved_5          : 1;
4583 		mmr_t	nibble2_nibble_sel  : 3;
4584 		mmr_t	reserved_4          : 1;
4585 		mmr_t	nibble2_chiplet_sel : 3;
4586 		mmr_t	reserved_3          : 1;
4587 		mmr_t	nibble1_nibble_sel  : 3;
4588 		mmr_t	reserved_2          : 1;
4589 		mmr_t	nibble1_chiplet_sel : 3;
4590 		mmr_t	reserved_1          : 1;
4591 		mmr_t	nibble0_nibble_sel  : 3;
4592 		mmr_t	reserved_0          : 1;
4593 		mmr_t	nibble0_chiplet_sel : 3;
4605 	mmr_t	sh_lb_debug_trig_sel_regval;
4607 		mmr_t	trigger0_chiplet_sel : 3;
4608 		mmr_t	reserved_0           : 1;
4609 		mmr_t	trigger0_nibble_sel  : 3;
4610 		mmr_t	reserved_1           : 1;
4611 		mmr_t	trigger1_chiplet_sel : 3;
4612 		mmr_t	reserved_2           : 1;
4613 		mmr_t	trigger1_nibble_sel  : 3;
4614 		mmr_t	reserved_3           : 1;
4615 		mmr_t	trigger2_chiplet_sel : 3;
4616 		mmr_t	reserved_4           : 1;
4617 		mmr_t	trigger2_nibble_sel  : 3;
4618 		mmr_t	reserved_5           : 1;
4619 		mmr_t	trigger3_chiplet_sel : 3;
4620 		mmr_t	reserved_6           : 1;
4621 		mmr_t	trigger3_nibble_sel  : 3;
4622 		mmr_t	reserved_7           : 1;
4623 		mmr_t	trigger4_chiplet_sel : 3;
4624 		mmr_t	reserved_8           : 1;
4625 		mmr_t	trigger4_nibble_sel  : 3;
4626 		mmr_t	reserved_9           : 1;
4627 		mmr_t	trigger5_chiplet_sel : 3;
4628 		mmr_t	reserved_10          : 1;
4629 		mmr_t	trigger5_nibble_sel  : 3;
4630 		mmr_t	reserved_11          : 1;
4631 		mmr_t	trigger6_chiplet_sel : 3;
4632 		mmr_t	reserved_12          : 1;
4633 		mmr_t	trigger6_nibble_sel  : 3;
4634 		mmr_t	reserved_13          : 1;
4635 		mmr_t	trigger7_chiplet_sel : 3;
4636 		mmr_t	reserved_14          : 1;
4637 		mmr_t	trigger7_nibble_sel  : 3;
4638 		mmr_t	reserved_15          : 1;
4643 	mmr_t	sh_lb_debug_trig_sel_regval;
4645 		mmr_t	reserved_15          : 1;
4646 		mmr_t	trigger7_nibble_sel  : 3;
4647 		mmr_t	reserved_14          : 1;
4648 		mmr_t	trigger7_chiplet_sel : 3;
4649 		mmr_t	reserved_13          : 1;
4650 		mmr_t	trigger6_nibble_sel  : 3;
4651 		mmr_t	reserved_12          : 1;
4652 		mmr_t	trigger6_chiplet_sel : 3;
4653 		mmr_t	reserved_11          : 1;
4654 		mmr_t	trigger5_nibble_sel  : 3;
4655 		mmr_t	reserved_10          : 1;
4656 		mmr_t	trigger5_chiplet_sel : 3;
4657 		mmr_t	reserved_9           : 1;
4658 		mmr_t	trigger4_nibble_sel  : 3;
4659 		mmr_t	reserved_8           : 1;
4660 		mmr_t	trigger4_chiplet_sel : 3;
4661 		mmr_t	reserved_7           : 1;
4662 		mmr_t	trigger3_nibble_sel  : 3;
4663 		mmr_t	reserved_6           : 1;
4664 		mmr_t	trigger3_chiplet_sel : 3;
4665 		mmr_t	reserved_5           : 1;
4666 		mmr_t	trigger2_nibble_sel  : 3;
4667 		mmr_t	reserved_4           : 1;
4668 		mmr_t	trigger2_chiplet_sel : 3;
4669 		mmr_t	reserved_3           : 1;
4670 		mmr_t	trigger1_nibble_sel  : 3;
4671 		mmr_t	reserved_2           : 1;
4672 		mmr_t	trigger1_chiplet_sel : 3;
4673 		mmr_t	reserved_1           : 1;
4674 		mmr_t	trigger0_nibble_sel  : 3;
4675 		mmr_t	reserved_0           : 1;
4676 		mmr_t	trigger0_chiplet_sel : 3;
4688 	mmr_t	sh_lb_error_detail_1_regval;
4690 		mmr_t	command     : 8;
4691 		mmr_t	suppl       : 14;
4692 		mmr_t	reserved_0  : 2;
4693 		mmr_t	source      : 14;
4694 		mmr_t	reserved_1  : 2;
4695 		mmr_t	dest        : 3;
4696 		mmr_t	reserved_2  : 5;
4697 		mmr_t	hdr_err     : 1;
4698 		mmr_t	data_err    : 1;
4699 		mmr_t	reserved_3  : 13;
4700 		mmr_t	valid       : 1;
4705 	mmr_t	sh_lb_error_detail_1_regval;
4707 		mmr_t	valid       : 1;
4708 		mmr_t	reserved_3  : 13;
4709 		mmr_t	data_err    : 1;
4710 		mmr_t	hdr_err     : 1;
4711 		mmr_t	reserved_2  : 5;
4712 		mmr_t	dest        : 3;
4713 		mmr_t	reserved_1  : 2;
4714 		mmr_t	source      : 14;
4715 		mmr_t	reserved_0  : 2;
4716 		mmr_t	suppl       : 14;
4717 		mmr_t	command     : 8;
4729 	mmr_t	sh_lb_error_detail_2_regval;
4731 		mmr_t	address     : 47;
4732 		mmr_t	reserved_0  : 17;
4737 	mmr_t	sh_lb_error_detail_2_regval;
4739 		mmr_t	reserved_0  : 17;
4740 		mmr_t	address     : 47;
4752 	mmr_t	sh_lb_error_detail_3_regval;
4754 		mmr_t	data        : 64;
4759 	mmr_t	sh_lb_error_detail_3_regval;
4761 		mmr_t	data        : 64;
4773 	mmr_t	sh_lb_error_detail_4_regval;
4775 		mmr_t	route       : 64;
4780 	mmr_t	sh_lb_error_detail_4_regval;
4782 		mmr_t	route       : 64;
4794 	mmr_t	sh_lb_error_detail_5_regval;
4796 		mmr_t	read_retry       : 1;
4797 		mmr_t	ptc1_write       : 1;
4798 		mmr_t	write_retry      : 1;
4799 		mmr_t	count_a_overflow : 1;
4800 		mmr_t	count_b_overflow : 1;
4801 		mmr_t	nack_a_timeout   : 1;
4802 		mmr_t	nack_b_timeout   : 1;
4803 		mmr_t	reserved_0       : 57;
4808 	mmr_t	sh_lb_error_detail_5_regval;
4810 		mmr_t	reserved_0       : 57;
4811 		mmr_t	nack_b_timeout   : 1;
4812 		mmr_t	nack_a_timeout   : 1;
4813 		mmr_t	count_b_overflow : 1;
4814 		mmr_t	count_a_overflow : 1;
4815 		mmr_t	write_retry      : 1;
4816 		mmr_t	ptc1_write       : 1;
4817 		mmr_t	read_retry       : 1;
4829 	mmr_t	sh_lb_error_mask_regval;
4831 		mmr_t	rq_bad_cmd            : 1;
4832 		mmr_t	rp_bad_cmd            : 1;
4833 		mmr_t	rq_short              : 1;
4834 		mmr_t	rp_short              : 1;
4835 		mmr_t	rq_long               : 1;
4836 		mmr_t	rp_long               : 1;
4837 		mmr_t	rq_bad_data           : 1;
4838 		mmr_t	rp_bad_data           : 1;
4839 		mmr_t	rq_bad_addr           : 1;
4840 		mmr_t	rq_time_out           : 1;
4841 		mmr_t	linvv_overflow        : 1;
4842 		mmr_t	unexpected_linv       : 1;
4843 		mmr_t	ptc_1_timeout         : 1;
4844 		mmr_t	junk_bus_err          : 1;
4845 		mmr_t	pio_cb_err            : 1;
4846 		mmr_t	vector_rq_route_error : 1;
4847 		mmr_t	vector_rp_route_error : 1;
4848 		mmr_t	gclk_drop             : 1;
4849 		mmr_t	rq_fifo_error         : 1;
4850 		mmr_t	rp_fifo_error         : 1;
4851 		mmr_t	unexp_valid           : 1;
4852 		mmr_t	rq_credit_overflow    : 1;
4853 		mmr_t	rp_credit_overflow    : 1;
4854 		mmr_t	reserved_0            : 41;
4859 	mmr_t	sh_lb_error_mask_regval;
4861 		mmr_t	reserved_0            : 41;
4862 		mmr_t	rp_credit_overflow    : 1;
4863 		mmr_t	rq_credit_overflow    : 1;
4864 		mmr_t	unexp_valid           : 1;
4865 		mmr_t	rp_fifo_error         : 1;
4866 		mmr_t	rq_fifo_error         : 1;
4867 		mmr_t	gclk_drop             : 1;
4868 		mmr_t	vector_rp_route_error : 1;
4869 		mmr_t	vector_rq_route_error : 1;
4870 		mmr_t	pio_cb_err            : 1;
4871 		mmr_t	junk_bus_err          : 1;
4872 		mmr_t	ptc_1_timeout         : 1;
4873 		mmr_t	unexpected_linv       : 1;
4874 		mmr_t	linvv_overflow        : 1;
4875 		mmr_t	rq_time_out           : 1;
4876 		mmr_t	rq_bad_addr           : 1;
4877 		mmr_t	rp_bad_data           : 1;
4878 		mmr_t	rq_bad_data           : 1;
4879 		mmr_t	rp_long               : 1;
4880 		mmr_t	rq_long               : 1;
4881 		mmr_t	rp_short              : 1;
4882 		mmr_t	rq_short              : 1;
4883 		mmr_t	rp_bad_cmd            : 1;
4884 		mmr_t	rq_bad_cmd            : 1;
4896 	mmr_t	sh_lb_error_overflow_regval;
4898 		mmr_t	rq_bad_cmd_ovrfl            : 1;
4899 		mmr_t	rp_bad_cmd_ovrfl            : 1;
4900 		mmr_t	rq_short_ovrfl              : 1;
4901 		mmr_t	rp_short_ovrfl              : 1;
4902 		mmr_t	rq_long_ovrfl               : 1;
4903 		mmr_t	rp_long_ovrfl               : 1;
4904 		mmr_t	rq_bad_data_ovrfl           : 1;
4905 		mmr_t	rp_bad_data_ovrfl           : 1;
4906 		mmr_t	rq_bad_addr_ovrfl           : 1;
4907 		mmr_t	rq_time_out_ovrfl           : 1;
4908 		mmr_t	linvv_overflow_ovrfl        : 1;
4909 		mmr_t	unexpected_linv_ovrfl       : 1;
4910 		mmr_t	ptc_1_timeout_ovrfl         : 1;
4911 		mmr_t	junk_bus_err_ovrfl          : 1;
4912 		mmr_t	pio_cb_err_ovrfl            : 1;
4913 		mmr_t	vector_rq_route_error_ovrfl : 1;
4914 		mmr_t	vector_rp_route_error_ovrfl : 1;
4915 		mmr_t	gclk_drop_ovrfl             : 1;
4916 		mmr_t	rq_fifo_error_ovrfl         : 1;
4917 		mmr_t	rp_fifo_error_ovrfl         : 1;
4918 		mmr_t	unexp_valid_ovrfl           : 1;
4919 		mmr_t	rq_credit_overflow_ovrfl    : 1;
4920 		mmr_t	rp_credit_overflow_ovrfl    : 1;
4921 		mmr_t	reserved_0                  : 41;
4926 	mmr_t	sh_lb_error_overflow_regval;
4928 		mmr_t	reserved_0                  : 41;
4929 		mmr_t	rp_credit_overflow_ovrfl    : 1;
4930 		mmr_t	rq_credit_overflow_ovrfl    : 1;
4931 		mmr_t	unexp_valid_ovrfl           : 1;
4932 		mmr_t	rp_fifo_error_ovrfl         : 1;
4933 		mmr_t	rq_fifo_error_ovrfl         : 1;
4934 		mmr_t	gclk_drop_ovrfl             : 1;
4935 		mmr_t	vector_rp_route_error_ovrfl : 1;
4936 		mmr_t	vector_rq_route_error_ovrfl : 1;
4937 		mmr_t	pio_cb_err_ovrfl            : 1;
4938 		mmr_t	junk_bus_err_ovrfl          : 1;
4939 		mmr_t	ptc_1_timeout_ovrfl         : 1;
4940 		mmr_t	unexpected_linv_ovrfl       : 1;
4941 		mmr_t	linvv_overflow_ovrfl        : 1;
4942 		mmr_t	rq_time_out_ovrfl           : 1;
4943 		mmr_t	rq_bad_addr_ovrfl           : 1;
4944 		mmr_t	rp_bad_data_ovrfl           : 1;
4945 		mmr_t	rq_bad_data_ovrfl           : 1;
4946 		mmr_t	rp_long_ovrfl               : 1;
4947 		mmr_t	rq_long_ovrfl               : 1;
4948 		mmr_t	rp_short_ovrfl              : 1;
4949 		mmr_t	rq_short_ovrfl              : 1;
4950 		mmr_t	rp_bad_cmd_ovrfl            : 1;
4951 		mmr_t	rq_bad_cmd_ovrfl            : 1;
4963 	mmr_t	sh_lb_error_summary_regval;
4965 		mmr_t	rq_bad_cmd            : 1;
4966 		mmr_t	rp_bad_cmd            : 1;
4967 		mmr_t	rq_short              : 1;
4968 		mmr_t	rp_short              : 1;
4969 		mmr_t	rq_long               : 1;
4970 		mmr_t	rp_long               : 1;
4971 		mmr_t	rq_bad_data           : 1;
4972 		mmr_t	rp_bad_data           : 1;
4973 		mmr_t	rq_bad_addr           : 1;
4974 		mmr_t	rq_time_out           : 1;
4975 		mmr_t	linvv_overflow        : 1;
4976 		mmr_t	unexpected_linv       : 1;
4977 		mmr_t	ptc_1_timeout         : 1;
4978 		mmr_t	junk_bus_err          : 1;
4979 		mmr_t	pio_cb_err            : 1;
4980 		mmr_t	vector_rq_route_error : 1;
4981 		mmr_t	vector_rp_route_error : 1;
4982 		mmr_t	gclk_drop             : 1;
4983 		mmr_t	rq_fifo_error         : 1;
4984 		mmr_t	rp_fifo_error         : 1;
4985 		mmr_t	unexp_valid           : 1;
4986 		mmr_t	rq_credit_overflow    : 1;
4987 		mmr_t	rp_credit_overflow    : 1;
4988 		mmr_t	reserved_0            : 41;
4993 	mmr_t	sh_lb_error_summary_regval;
4995 		mmr_t	reserved_0            : 41;
4996 		mmr_t	rp_credit_overflow    : 1;
4997 		mmr_t	rq_credit_overflow    : 1;
4998 		mmr_t	unexp_valid           : 1;
4999 		mmr_t	rp_fifo_error         : 1;
5000 		mmr_t	rq_fifo_error         : 1;
5001 		mmr_t	gclk_drop             : 1;
5002 		mmr_t	vector_rp_route_error : 1;
5003 		mmr_t	vector_rq_route_error : 1;
5004 		mmr_t	pio_cb_err            : 1;
5005 		mmr_t	junk_bus_err          : 1;
5006 		mmr_t	ptc_1_timeout         : 1;
5007 		mmr_t	unexpected_linv       : 1;
5008 		mmr_t	linvv_overflow        : 1;
5009 		mmr_t	rq_time_out           : 1;
5010 		mmr_t	rq_bad_addr           : 1;
5011 		mmr_t	rp_bad_data           : 1;
5012 		mmr_t	rq_bad_data           : 1;
5013 		mmr_t	rp_long               : 1;
5014 		mmr_t	rq_long               : 1;
5015 		mmr_t	rp_short              : 1;
5016 		mmr_t	rq_short              : 1;
5017 		mmr_t	rp_bad_cmd            : 1;
5018 		mmr_t	rq_bad_cmd            : 1;
5030 	mmr_t	sh_lb_first_error_regval;
5032 		mmr_t	rq_bad_cmd            : 1;
5033 		mmr_t	rp_bad_cmd            : 1;
5034 		mmr_t	rq_short              : 1;
5035 		mmr_t	rp_short              : 1;
5036 		mmr_t	rq_long               : 1;
5037 		mmr_t	rp_long               : 1;
5038 		mmr_t	rq_bad_data           : 1;
5039 		mmr_t	rp_bad_data           : 1;
5040 		mmr_t	rq_bad_addr           : 1;
5041 		mmr_t	rq_time_out           : 1;
5042 		mmr_t	linvv_overflow        : 1;
5043 		mmr_t	unexpected_linv       : 1;
5044 		mmr_t	ptc_1_timeout         : 1;
5045 		mmr_t	junk_bus_err          : 1;
5046 		mmr_t	pio_cb_err            : 1;
5047 		mmr_t	vector_rq_route_error : 1;
5048 		mmr_t	vector_rp_route_error : 1;
5049 		mmr_t	gclk_drop             : 1;
5050 		mmr_t	rq_fifo_error         : 1;
5051 		mmr_t	rp_fifo_error         : 1;
5052 		mmr_t	unexp_valid           : 1;
5053 		mmr_t	rq_credit_overflow    : 1;
5054 		mmr_t	rp_credit_overflow    : 1;
5055 		mmr_t	reserved_0            : 41;
5060 	mmr_t	sh_lb_first_error_regval;
5062 		mmr_t	reserved_0            : 41;
5063 		mmr_t	rp_credit_overflow    : 1;
5064 		mmr_t	rq_credit_overflow    : 1;
5065 		mmr_t	unexp_valid           : 1;
5066 		mmr_t	rp_fifo_error         : 1;
5067 		mmr_t	rq_fifo_error         : 1;
5068 		mmr_t	gclk_drop             : 1;
5069 		mmr_t	vector_rp_route_error : 1;
5070 		mmr_t	vector_rq_route_error : 1;
5071 		mmr_t	pio_cb_err            : 1;
5072 		mmr_t	junk_bus_err          : 1;
5073 		mmr_t	ptc_1_timeout         : 1;
5074 		mmr_t	unexpected_linv       : 1;
5075 		mmr_t	linvv_overflow        : 1;
5076 		mmr_t	rq_time_out           : 1;
5077 		mmr_t	rq_bad_addr           : 1;
5078 		mmr_t	rp_bad_data           : 1;
5079 		mmr_t	rq_bad_data           : 1;
5080 		mmr_t	rp_long               : 1;
5081 		mmr_t	rq_long               : 1;
5082 		mmr_t	rp_short              : 1;
5083 		mmr_t	rq_short              : 1;
5084 		mmr_t	rp_bad_cmd            : 1;
5085 		mmr_t	rq_bad_cmd            : 1;
5097 	mmr_t	sh_lb_last_credit_regval;
5099 		mmr_t	liq_rq_credit : 5;
5100 		mmr_t	reserved_0    : 1;
5101 		mmr_t	liq_rp_credit : 4;
5102 		mmr_t	reserved_1    : 2;
5103 		mmr_t	linvv_credit  : 6;
5104 		mmr_t	loq_rq_credit : 5;
5105 		mmr_t	loq_rp_credit : 5;
5106 		mmr_t	reserved_2    : 36;
5111 	mmr_t	sh_lb_last_credit_regval;
5113 		mmr_t	reserved_2    : 36;
5114 		mmr_t	loq_rp_credit : 5;
5115 		mmr_t	loq_rq_credit : 5;
5116 		mmr_t	linvv_credit  : 6;
5117 		mmr_t	reserved_1    : 2;
5118 		mmr_t	liq_rp_credit : 4;
5119 		mmr_t	reserved_0    : 1;
5120 		mmr_t	liq_rq_credit : 5;
5132 	mmr_t	sh_lb_nack_status_regval;
5134 		mmr_t	pio_nack_a       : 12;
5135 		mmr_t	reserved_0       : 4;
5136 		mmr_t	pio_nack_b       : 12;
5137 		mmr_t	reserved_1       : 4;
5138 		mmr_t	junk_nack        : 16;
5139 		mmr_t	cb_timeout_count : 12;
5140 		mmr_t	cb_state         : 2;
5141 		mmr_t	reserved_2       : 2;
5146 	mmr_t	sh_lb_nack_status_regval;
5148 		mmr_t	reserved_2       : 2;
5149 		mmr_t	cb_state         : 2;
5150 		mmr_t	cb_timeout_count : 12;
5151 		mmr_t	junk_nack        : 16;
5152 		mmr_t	reserved_1       : 4;
5153 		mmr_t	pio_nack_b       : 12;
5154 		mmr_t	reserved_0       : 4;
5155 		mmr_t	pio_nack_a       : 12;
5167 	mmr_t	sh_lb_trigger_compare_regval;
5169 		mmr_t	mask        : 32;
5170 		mmr_t	reserved_0  : 32;
5175 	mmr_t	sh_lb_trigger_compare_regval;
5177 		mmr_t	reserved_0  : 32;
5178 		mmr_t	mask        : 32;
5190 	mmr_t	sh_lb_trigger_data_regval;
5192 		mmr_t	compare_pattern : 32;
5193 		mmr_t	reserved_0      : 32;
5198 	mmr_t	sh_lb_trigger_data_regval;
5200 		mmr_t	reserved_0      : 32;
5201 		mmr_t	compare_pattern : 32;
5213 	mmr_t	sh_pi_aec_config_regval;
5215 		mmr_t	mode        : 3;
5216 		mmr_t	reserved_0  : 61;
5221 	mmr_t	sh_pi_aec_config_regval;
5223 		mmr_t	reserved_0  : 61;
5224 		mmr_t	mode        : 3;
5236 	mmr_t	sh_pi_afi_error_mask_regval;
5238 		mmr_t	reserved_0   : 21;
5239 		mmr_t	hung_bus     : 1;
5240 		mmr_t	rsp_parity   : 1;
5241 		mmr_t	ioq_overrun  : 1;
5242 		mmr_t	req_format   : 1;
5243 		mmr_t	addr_access  : 1;
5244 		mmr_t	req_parity   : 1;
5245 		mmr_t	addr_parity  : 1;
5246 		mmr_t	shub_fsb_dqe : 1;
5247 		mmr_t	shub_fsb_uce : 1;
5248 		mmr_t	shub_fsb_ce  : 1;
5249 		mmr_t	livelock     : 1;
5250 		mmr_t	bad_snoop    : 1;
5251 		mmr_t	fsb_tbl_miss : 1;
5252 		mmr_t	msg_len      : 1;
5253 		mmr_t	reserved_1   : 29;
5258 	mmr_t	sh_pi_afi_error_mask_regval;
5260 		mmr_t	reserved_1   : 29;
5261 		mmr_t	msg_len      : 1;
5262 		mmr_t	fsb_tbl_miss : 1;
5263 		mmr_t	bad_snoop    : 1;
5264 		mmr_t	livelock     : 1;
5265 		mmr_t	shub_fsb_ce  : 1;
5266 		mmr_t	shub_fsb_uce : 1;
5267 		mmr_t	shub_fsb_dqe : 1;
5268 		mmr_t	addr_parity  : 1;
5269 		mmr_t	req_parity   : 1;
5270 		mmr_t	addr_access  : 1;
5271 		mmr_t	req_format   : 1;
5272 		mmr_t	ioq_overrun  : 1;
5273 		mmr_t	rsp_parity   : 1;
5274 		mmr_t	hung_bus     : 1;
5275 		mmr_t	reserved_0   : 21;
5287 	mmr_t	sh_pi_afi_test_point_compare_regval;
5289 		mmr_t	compare_mask    : 32;
5290 		mmr_t	compare_pattern : 32;
5295 	mmr_t	sh_pi_afi_test_point_compare_regval;
5297 		mmr_t	compare_pattern : 32;
5298 		mmr_t	compare_mask    : 32;
5310 	mmr_t	sh_pi_afi_test_point_select_regval;
5312 		mmr_t	nibble0_chiplet_sel : 4;
5313 		mmr_t	nibble0_nibble_sel  : 3;
5314 		mmr_t	reserved_0          : 1;
5315 		mmr_t	nibble1_chiplet_sel : 4;
5316 		mmr_t	nibble1_nibble_sel  : 3;
5317 		mmr_t	reserved_1          : 1;
5318 		mmr_t	nibble2_chiplet_sel : 4;
5319 		mmr_t	nibble2_nibble_sel  : 3;
5320 		mmr_t	reserved_2          : 1;
5321 		mmr_t	nibble3_chiplet_sel : 4;
5322 		mmr_t	nibble3_nibble_sel  : 3;
5323 		mmr_t	reserved_3          : 1;
5324 		mmr_t	nibble4_chiplet_sel : 4;
5325 		mmr_t	nibble4_nibble_sel  : 3;
5326 		mmr_t	reserved_4          : 1;
5327 		mmr_t	nibble5_chiplet_sel : 4;
5328 		mmr_t	nibble5_nibble_sel  : 3;
5329 		mmr_t	reserved_5          : 1;
5330 		mmr_t	nibble6_chiplet_sel : 4;
5331 		mmr_t	nibble6_nibble_sel  : 3;
5332 		mmr_t	reserved_6          : 1;
5333 		mmr_t	nibble7_chiplet_sel : 4;
5334 		mmr_t	nibble7_nibble_sel  : 3;
5335 		mmr_t	trigger_enable      : 1;
5340 	mmr_t	sh_pi_afi_test_point_select_regval;
5342 		mmr_t	trigger_enable      : 1;
5343 		mmr_t	nibble7_nibble_sel  : 3;
5344 		mmr_t	nibble7_chiplet_sel : 4;
5345 		mmr_t	reserved_6          : 1;
5346 		mmr_t	nibble6_nibble_sel  : 3;
5347 		mmr_t	nibble6_chiplet_sel : 4;
5348 		mmr_t	reserved_5          : 1;
5349 		mmr_t	nibble5_nibble_sel  : 3;
5350 		mmr_t	nibble5_chiplet_sel : 4;
5351 		mmr_t	reserved_4          : 1;
5352 		mmr_t	nibble4_nibble_sel  : 3;
5353 		mmr_t	nibble4_chiplet_sel : 4;
5354 		mmr_t	reserved_3          : 1;
5355 		mmr_t	nibble3_nibble_sel  : 3;
5356 		mmr_t	nibble3_chiplet_sel : 4;
5357 		mmr_t	reserved_2          : 1;
5358 		mmr_t	nibble2_nibble_sel  : 3;
5359 		mmr_t	nibble2_chiplet_sel : 4;
5360 		mmr_t	reserved_1          : 1;
5361 		mmr_t	nibble1_nibble_sel  : 3;
5362 		mmr_t	nibble1_chiplet_sel : 4;
5363 		mmr_t	reserved_0          : 1;
5364 		mmr_t	nibble0_nibble_sel  : 3;
5365 		mmr_t	nibble0_chiplet_sel : 4;
5377 	mmr_t	sh_pi_afi_test_point_trigger_select_regval;
5379 		mmr_t	trigger0_chiplet_sel : 4;
5380 		mmr_t	trigger0_nibble_sel  : 3;
5381 		mmr_t	reserved_0           : 1;
5382 		mmr_t	trigger1_chiplet_sel : 4;
5383 		mmr_t	trigger1_nibble_sel  : 3;
5384 		mmr_t	reserved_1           : 1;
5385 		mmr_t	trigger2_chiplet_sel : 4;
5386 		mmr_t	trigger2_nibble_sel  : 3;
5387 		mmr_t	reserved_2           : 1;
5388 		mmr_t	trigger3_chiplet_sel : 4;
5389 		mmr_t	trigger3_nibble_sel  : 3;
5390 		mmr_t	reserved_3           : 1;
5391 		mmr_t	trigger4_chiplet_sel : 4;
5392 		mmr_t	trigger4_nibble_sel  : 3;
5393 		mmr_t	reserved_4           : 1;
5394 		mmr_t	trigger5_chiplet_sel : 4;
5395 		mmr_t	trigger5_nibble_sel  : 3;
5396 		mmr_t	reserved_5           : 1;
5397 		mmr_t	trigger6_chiplet_sel : 4;
5398 		mmr_t	trigger6_nibble_sel  : 3;
5399 		mmr_t	reserved_6           : 1;
5400 		mmr_t	trigger7_chiplet_sel : 4;
5401 		mmr_t	trigger7_nibble_sel  : 3;
5402 		mmr_t	reserved_7           : 1;
5407 	mmr_t	sh_pi_afi_test_point_trigger_select_regval;
5409 		mmr_t	reserved_7           : 1;
5410 		mmr_t	trigger7_nibble_sel  : 3;
5411 		mmr_t	trigger7_chiplet_sel : 4;
5412 		mmr_t	reserved_6           : 1;
5413 		mmr_t	trigger6_nibble_sel  : 3;
5414 		mmr_t	trigger6_chiplet_sel : 4;
5415 		mmr_t	reserved_5           : 1;
5416 		mmr_t	trigger5_nibble_sel  : 3;
5417 		mmr_t	trigger5_chiplet_sel : 4;
5418 		mmr_t	reserved_4           : 1;
5419 		mmr_t	trigger4_nibble_sel  : 3;
5420 		mmr_t	trigger4_chiplet_sel : 4;
5421 		mmr_t	reserved_3           : 1;
5422 		mmr_t	trigger3_nibble_sel  : 3;
5423 		mmr_t	trigger3_chiplet_sel : 4;
5424 		mmr_t	reserved_2           : 1;
5425 		mmr_t	trigger2_nibble_sel  : 3;
5426 		mmr_t	trigger2_chiplet_sel : 4;
5427 		mmr_t	reserved_1           : 1;
5428 		mmr_t	trigger1_nibble_sel  : 3;
5429 		mmr_t	trigger1_chiplet_sel : 4;
5430 		mmr_t	reserved_0           : 1;
5431 		mmr_t	trigger0_nibble_sel  : 3;
5432 		mmr_t	trigger0_chiplet_sel : 4;
5444 	mmr_t	sh_pi_auto_reply_enable_regval;
5446 		mmr_t	auto_reply_enable : 1;
5447 		mmr_t	reserved_0        : 63;
5452 	mmr_t	sh_pi_auto_reply_enable_regval;
5454 		mmr_t	reserved_0        : 63;
5455 		mmr_t	auto_reply_enable : 1;
5467 	mmr_t	sh_pi_cam_control_regval;
5469 		mmr_t	cam_indx          : 7;
5470 		mmr_t	reserved_0        : 1;
5471 		mmr_t	cam_write         : 1;
5472 		mmr_t	rrb_rd_xfer_clear : 1;
5473 		mmr_t	reserved_1        : 53;
5474 		mmr_t	start             : 1;
5479 	mmr_t	sh_pi_cam_control_regval;
5481 		mmr_t	start             : 1;
5482 		mmr_t	reserved_1        : 53;
5483 		mmr_t	rrb_rd_xfer_clear : 1;
5484 		mmr_t	cam_write         : 1;
5485 		mmr_t	reserved_0        : 1;
5486 		mmr_t	cam_indx          : 7;
5498 	mmr_t	sh_pi_crbc_test_point_compare_regval;
5500 		mmr_t	compare_mask    : 32;
5501 		mmr_t	compare_pattern : 32;
5506 	mmr_t	sh_pi_crbc_test_point_compare_regval;
5508 		mmr_t	compare_pattern : 32;
5509 		mmr_t	compare_mask    : 32;
5521 	mmr_t	sh_pi_crbc_test_point_select_regval;
5523 		mmr_t	nibble0_chiplet_sel : 3;
5524 		mmr_t	reserved_0          : 1;
5525 		mmr_t	nibble0_nibble_sel  : 3;
5526 		mmr_t	reserved_1          : 1;
5527 		mmr_t	nibble1_chiplet_sel : 3;
5528 		mmr_t	reserved_2          : 1;
5529 		mmr_t	nibble1_nibble_sel  : 3;
5530 		mmr_t	reserved_3          : 1;
5531 		mmr_t	nibble2_chiplet_sel : 3;
5532 		mmr_t	reserved_4          : 1;
5533 		mmr_t	nibble2_nibble_sel  : 3;
5534 		mmr_t	reserved_5          : 1;
5535 		mmr_t	nibble3_chiplet_sel : 3;
5536 		mmr_t	reserved_6          : 1;
5537 		mmr_t	nibble3_nibble_sel  : 3;
5538 		mmr_t	reserved_7          : 1;
5539 		mmr_t	nibble4_chiplet_sel : 3;
5540 		mmr_t	reserved_8          : 1;
5541 		mmr_t	nibble4_nibble_sel  : 3;
5542 		mmr_t	reserved_9          : 1;
5543 		mmr_t	nibble5_chiplet_sel : 3;
5544 		mmr_t	reserved_10         : 1;
5545 		mmr_t	nibble5_nibble_sel  : 3;
5546 		mmr_t	reserved_11         : 1;
5547 		mmr_t	nibble6_chiplet_sel : 3;
5548 		mmr_t	reserved_12         : 1;
5549 		mmr_t	nibble6_nibble_sel  : 3;
5550 		mmr_t	reserved_13         : 1;
5551 		mmr_t	nibble7_chiplet_sel : 3;
5552 		mmr_t	reserved_14         : 1;
5553 		mmr_t	nibble7_nibble_sel  : 3;
5554 		mmr_t	trigger_enable      : 1;
5559 	mmr_t	sh_pi_crbc_test_point_select_regval;
5561 		mmr_t	trigger_enable      : 1;
5562 		mmr_t	nibble7_nibble_sel  : 3;
5563 		mmr_t	reserved_14         : 1;
5564 		mmr_t	nibble7_chiplet_sel : 3;
5565 		mmr_t	reserved_13         : 1;
5566 		mmr_t	nibble6_nibble_sel  : 3;
5567 		mmr_t	reserved_12         : 1;
5568 		mmr_t	nibble6_chiplet_sel : 3;
5569 		mmr_t	reserved_11         : 1;
5570 		mmr_t	nibble5_nibble_sel  : 3;
5571 		mmr_t	reserved_10         : 1;
5572 		mmr_t	nibble5_chiplet_sel : 3;
5573 		mmr_t	reserved_9          : 1;
5574 		mmr_t	nibble4_nibble_sel  : 3;
5575 		mmr_t	reserved_8          : 1;
5576 		mmr_t	nibble4_chiplet_sel : 3;
5577 		mmr_t	reserved_7          : 1;
5578 		mmr_t	nibble3_nibble_sel  : 3;
5579 		mmr_t	reserved_6          : 1;
5580 		mmr_t	nibble3_chiplet_sel : 3;
5581 		mmr_t	reserved_5          : 1;
5582 		mmr_t	nibble2_nibble_sel  : 3;
5583 		mmr_t	reserved_4          : 1;
5584 		mmr_t	nibble2_chiplet_sel : 3;
5585 		mmr_t	reserved_3          : 1;
5586 		mmr_t	nibble1_nibble_sel  : 3;
5587 		mmr_t	reserved_2          : 1;
5588 		mmr_t	nibble1_chiplet_sel : 3;
5589 		mmr_t	reserved_1          : 1;
5590 		mmr_t	nibble0_nibble_sel  : 3;
5591 		mmr_t	reserved_0          : 1;
5592 		mmr_t	nibble0_chiplet_sel : 3;
5604 	mmr_t	sh_pi_crbc_test_point_trigger_select_regval;
5606 		mmr_t	trigger0_chiplet_sel : 3;
5607 		mmr_t	reserved_0           : 1;
5608 		mmr_t	trigger0_nibble_sel  : 3;
5609 		mmr_t	reserved_1           : 1;
5610 		mmr_t	trigger1_chiplet_sel : 3;
5611 		mmr_t	reserved_2           : 1;
5612 		mmr_t	trigger1_nibble_sel  : 3;
5613 		mmr_t	reserved_3           : 1;
5614 		mmr_t	trigger2_chiplet_sel : 3;
5615 		mmr_t	reserved_4           : 1;
5616 		mmr_t	trigger2_nibble_sel  : 3;
5617 		mmr_t	reserved_5           : 1;
5618 		mmr_t	trigger3_chiplet_sel : 3;
5619 		mmr_t	reserved_6           : 1;
5620 		mmr_t	trigger3_nibble_sel  : 3;
5621 		mmr_t	reserved_7           : 1;
5622 		mmr_t	trigger4_chiplet_sel : 3;
5623 		mmr_t	reserved_8           : 1;
5624 		mmr_t	trigger4_nibble_sel  : 3;
5625 		mmr_t	reserved_9           : 1;
5626 		mmr_t	trigger5_chiplet_sel : 3;
5627 		mmr_t	reserved_10          : 1;
5628 		mmr_t	trigger5_nibble_sel  : 3;
5629 		mmr_t	reserved_11          : 1;
5630 		mmr_t	trigger6_chiplet_sel : 3;
5631 		mmr_t	reserved_12          : 1;
5632 		mmr_t	trigger6_nibble_sel  : 3;
5633 		mmr_t	reserved_13          : 1;
5634 		mmr_t	trigger7_chiplet_sel : 3;
5635 		mmr_t	reserved_14          : 1;
5636 		mmr_t	trigger7_nibble_sel  : 3;
5637 		mmr_t	reserved_15          : 1;
5642 	mmr_t	sh_pi_crbc_test_point_trigger_select_regval;
5644 		mmr_t	reserved_15          : 1;
5645 		mmr_t	trigger7_nibble_sel  : 3;
5646 		mmr_t	reserved_14          : 1;
5647 		mmr_t	trigger7_chiplet_sel : 3;
5648 		mmr_t	reserved_13          : 1;
5649 		mmr_t	trigger6_nibble_sel  : 3;
5650 		mmr_t	reserved_12          : 1;
5651 		mmr_t	trigger6_chiplet_sel : 3;
5652 		mmr_t	reserved_11          : 1;
5653 		mmr_t	trigger5_nibble_sel  : 3;
5654 		mmr_t	reserved_10          : 1;
5655 		mmr_t	trigger5_chiplet_sel : 3;
5656 		mmr_t	reserved_9           : 1;
5657 		mmr_t	trigger4_nibble_sel  : 3;
5658 		mmr_t	reserved_8           : 1;
5659 		mmr_t	trigger4_chiplet_sel : 3;
5660 		mmr_t	reserved_7           : 1;
5661 		mmr_t	trigger3_nibble_sel  : 3;
5662 		mmr_t	reserved_6           : 1;
5663 		mmr_t	trigger3_chiplet_sel : 3;
5664 		mmr_t	reserved_5           : 1;
5665 		mmr_t	trigger2_nibble_sel  : 3;
5666 		mmr_t	reserved_4           : 1;
5667 		mmr_t	trigger2_chiplet_sel : 3;
5668 		mmr_t	reserved_3           : 1;
5669 		mmr_t	trigger1_nibble_sel  : 3;
5670 		mmr_t	reserved_2           : 1;
5671 		mmr_t	trigger1_chiplet_sel : 3;
5672 		mmr_t	reserved_1           : 1;
5673 		mmr_t	trigger0_nibble_sel  : 3;
5674 		mmr_t	reserved_0           : 1;
5675 		mmr_t	trigger0_chiplet_sel : 3;
5687 	mmr_t	sh_pi_crbp_error_mask_regval;
5689 		mmr_t	fsb_proto_err   : 1;
5690 		mmr_t	gfx_rp_err      : 1;
5691 		mmr_t	xb_proto_err    : 1;
5692 		mmr_t	mem_rp_err      : 1;
5693 		mmr_t	pio_rp_err      : 1;
5694 		mmr_t	mem_to_err      : 1;
5695 		mmr_t	pio_to_err      : 1;
5696 		mmr_t	fsb_shub_uce    : 1;
5697 		mmr_t	fsb_shub_ce     : 1;
5698 		mmr_t	msg_color_err   : 1;
5699 		mmr_t	md_rq_q_oflow   : 1;
5700 		mmr_t	md_rp_q_oflow   : 1;
5701 		mmr_t	xn_rq_q_oflow   : 1;
5702 		mmr_t	xn_rp_q_oflow   : 1;
5703 		mmr_t	nack_oflow      : 1;
5704 		mmr_t	gfx_int_0       : 1;
5705 		mmr_t	gfx_int_1       : 1;
5706 		mmr_t	md_rq_crd_oflow : 1;
5707 		mmr_t	md_rp_crd_oflow : 1;
5708 		mmr_t	xn_rq_crd_oflow : 1;
5709 		mmr_t	xn_rp_crd_oflow : 1;
5710 		mmr_t	reserved_0      : 43;
5715 	mmr_t	sh_pi_crbp_error_mask_regval;
5717 		mmr_t	reserved_0      : 43;
5718 		mmr_t	xn_rp_crd_oflow : 1;
5719 		mmr_t	xn_rq_crd_oflow : 1;
5720 		mmr_t	md_rp_crd_oflow : 1;
5721 		mmr_t	md_rq_crd_oflow : 1;
5722 		mmr_t	gfx_int_1       : 1;
5723 		mmr_t	gfx_int_0       : 1;
5724 		mmr_t	nack_oflow      : 1;
5725 		mmr_t	xn_rp_q_oflow   : 1;
5726 		mmr_t	xn_rq_q_oflow   : 1;
5727 		mmr_t	md_rp_q_oflow   : 1;
5728 		mmr_t	md_rq_q_oflow   : 1;
5729 		mmr_t	msg_color_err   : 1;
5730 		mmr_t	fsb_shub_ce     : 1;
5731 		mmr_t	fsb_shub_uce    : 1;
5732 		mmr_t	pio_to_err      : 1;
5733 		mmr_t	mem_to_err      : 1;
5734 		mmr_t	pio_rp_err      : 1;
5735 		mmr_t	mem_rp_err      : 1;
5736 		mmr_t	xb_proto_err    : 1;
5737 		mmr_t	gfx_rp_err      : 1;
5738 		mmr_t	fsb_proto_err   : 1;
5750 	mmr_t	sh_pi_crbp_fsb_pipe_compare_regval;
5752 		mmr_t	compare_address : 47;
5753 		mmr_t	compare_req     : 6;
5754 		mmr_t	reserved_0      : 11;
5759 	mmr_t	sh_pi_crbp_fsb_pipe_compare_regval;
5761 		mmr_t	reserved_0      : 11;
5762 		mmr_t	compare_req     : 6;
5763 		mmr_t	compare_address : 47;
5775 	mmr_t	sh_pi_crbp_fsb_pipe_mask_regval;
5777 		mmr_t	compare_address_mask : 47;
5778 		mmr_t	compare_req_mask     : 6;
5779 		mmr_t	reserved_0           : 11;
5784 	mmr_t	sh_pi_crbp_fsb_pipe_mask_regval;
5786 		mmr_t	reserved_0           : 11;
5787 		mmr_t	compare_req_mask     : 6;
5788 		mmr_t	compare_address_mask : 47;
5800 	mmr_t	sh_pi_crbp_test_point_compare_regval;
5802 		mmr_t	compare_mask    : 32;
5803 		mmr_t	compare_pattern : 32;
5808 	mmr_t	sh_pi_crbp_test_point_compare_regval;
5810 		mmr_t	compare_pattern : 32;
5811 		mmr_t	compare_mask    : 32;
5823 	mmr_t	sh_pi_crbp_test_point_select_regval;
5825 		mmr_t	nibble0_chiplet_sel : 3;
5826 		mmr_t	reserved_0          : 1;
5827 		mmr_t	nibble0_nibble_sel  : 3;
5828 		mmr_t	reserved_1          : 1;
5829 		mmr_t	nibble1_chiplet_sel : 3;
5830 		mmr_t	reserved_2          : 1;
5831 		mmr_t	nibble1_nibble_sel  : 3;
5832 		mmr_t	reserved_3          : 1;
5833 		mmr_t	nibble2_chiplet_sel : 3;
5834 		mmr_t	reserved_4          : 1;
5835 		mmr_t	nibble2_nibble_sel  : 3;
5836 		mmr_t	reserved_5          : 1;
5837 		mmr_t	nibble3_chiplet_sel : 3;
5838 		mmr_t	reserved_6          : 1;
5839 		mmr_t	nibble3_nibble_sel  : 3;
5840 		mmr_t	reserved_7          : 1;
5841 		mmr_t	nibble4_chiplet_sel : 3;
5842 		mmr_t	reserved_8          : 1;
5843 		mmr_t	nibble4_nibble_sel  : 3;
5844 		mmr_t	reserved_9          : 1;
5845 		mmr_t	nibble5_chiplet_sel : 3;
5846 		mmr_t	reserved_10         : 1;
5847 		mmr_t	nibble5_nibble_sel  : 3;
5848 		mmr_t	reserved_11         : 1;
5849 		mmr_t	nibble6_chiplet_sel : 3;
5850 		mmr_t	reserved_12         : 1;
5851 		mmr_t	nibble6_nibble_sel  : 3;
5852 		mmr_t	reserved_13         : 1;
5853 		mmr_t	nibble7_chiplet_sel : 3;
5854 		mmr_t	reserved_14         : 1;
5855 		mmr_t	nibble7_nibble_sel  : 3;
5856 		mmr_t	trigger_enable      : 1;
5861 	mmr_t	sh_pi_crbp_test_point_select_regval;
5863 		mmr_t	trigger_enable      : 1;
5864 		mmr_t	nibble7_nibble_sel  : 3;
5865 		mmr_t	reserved_14         : 1;
5866 		mmr_t	nibble7_chiplet_sel : 3;
5867 		mmr_t	reserved_13         : 1;
5868 		mmr_t	nibble6_nibble_sel  : 3;
5869 		mmr_t	reserved_12         : 1;
5870 		mmr_t	nibble6_chiplet_sel : 3;
5871 		mmr_t	reserved_11         : 1;
5872 		mmr_t	nibble5_nibble_sel  : 3;
5873 		mmr_t	reserved_10         : 1;
5874 		mmr_t	nibble5_chiplet_sel : 3;
5875 		mmr_t	reserved_9          : 1;
5876 		mmr_t	nibble4_nibble_sel  : 3;
5877 		mmr_t	reserved_8          : 1;
5878 		mmr_t	nibble4_chiplet_sel : 3;
5879 		mmr_t	reserved_7          : 1;
5880 		mmr_t	nibble3_nibble_sel  : 3;
5881 		mmr_t	reserved_6          : 1;
5882 		mmr_t	nibble3_chiplet_sel : 3;
5883 		mmr_t	reserved_5          : 1;
5884 		mmr_t	nibble2_nibble_sel  : 3;
5885 		mmr_t	reserved_4          : 1;
5886 		mmr_t	nibble2_chiplet_sel : 3;
5887 		mmr_t	reserved_3          : 1;
5888 		mmr_t	nibble1_nibble_sel  : 3;
5889 		mmr_t	reserved_2          : 1;
5890 		mmr_t	nibble1_chiplet_sel : 3;
5891 		mmr_t	reserved_1          : 1;
5892 		mmr_t	nibble0_nibble_sel  : 3;
5893 		mmr_t	reserved_0          : 1;
5894 		mmr_t	nibble0_chiplet_sel : 3;
5906 	mmr_t	sh_pi_crbp_test_point_trigger_select_regval;
5908 		mmr_t	trigger0_chiplet_sel : 3;
5909 		mmr_t	reserved_0           : 1;
5910 		mmr_t	trigger0_nibble_sel  : 3;
5911 		mmr_t	reserved_1           : 1;
5912 		mmr_t	trigger1_chiplet_sel : 3;
5913 		mmr_t	reserved_2           : 1;
5914 		mmr_t	trigger1_nibble_sel  : 3;
5915 		mmr_t	reserved_3           : 1;
5916 		mmr_t	trigger2_chiplet_sel : 3;
5917 		mmr_t	reserved_4           : 1;
5918 		mmr_t	trigger2_nibble_sel  : 3;
5919 		mmr_t	reserved_5           : 1;
5920 		mmr_t	trigger3_chiplet_sel : 3;
5921 		mmr_t	reserved_6           : 1;
5922 		mmr_t	trigger3_nibble_sel  : 3;
5923 		mmr_t	reserved_7           : 1;
5924 		mmr_t	trigger4_chiplet_sel : 3;
5925 		mmr_t	reserved_8           : 1;
5926 		mmr_t	trigger4_nibble_sel  : 3;
5927 		mmr_t	reserved_9           : 1;
5928 		mmr_t	trigger5_chiplet_sel : 3;
5929 		mmr_t	reserved_10          : 1;
5930 		mmr_t	trigger5_nibble_sel  : 3;
5931 		mmr_t	reserved_11          : 1;
5932 		mmr_t	trigger6_chiplet_sel : 3;
5933 		mmr_t	reserved_12          : 1;
5934 		mmr_t	trigger6_nibble_sel  : 3;
5935 		mmr_t	reserved_13          : 1;
5936 		mmr_t	trigger7_chiplet_sel : 3;
5937 		mmr_t	reserved_14          : 1;
5938 		mmr_t	trigger7_nibble_sel  : 3;
5939 		mmr_t	reserved_15          : 1;
5944 	mmr_t	sh_pi_crbp_test_point_trigger_select_regval;
5946 		mmr_t	reserved_15          : 1;
5947 		mmr_t	trigger7_nibble_sel  : 3;
5948 		mmr_t	reserved_14          : 1;
5949 		mmr_t	trigger7_chiplet_sel : 3;
5950 		mmr_t	reserved_13          : 1;
5951 		mmr_t	trigger6_nibble_sel  : 3;
5952 		mmr_t	reserved_12          : 1;
5953 		mmr_t	trigger6_chiplet_sel : 3;
5954 		mmr_t	reserved_11          : 1;
5955 		mmr_t	trigger5_nibble_sel  : 3;
5956 		mmr_t	reserved_10          : 1;
5957 		mmr_t	trigger5_chiplet_sel : 3;
5958 		mmr_t	reserved_9           : 1;
5959 		mmr_t	trigger4_nibble_sel  : 3;
5960 		mmr_t	reserved_8           : 1;
5961 		mmr_t	trigger4_chiplet_sel : 3;
5962 		mmr_t	reserved_7           : 1;
5963 		mmr_t	trigger3_nibble_sel  : 3;
5964 		mmr_t	reserved_6           : 1;
5965 		mmr_t	trigger3_chiplet_sel : 3;
5966 		mmr_t	reserved_5           : 1;
5967 		mmr_t	trigger2_nibble_sel  : 3;
5968 		mmr_t	reserved_4           : 1;
5969 		mmr_t	trigger2_chiplet_sel : 3;
5970 		mmr_t	reserved_3           : 1;
5971 		mmr_t	trigger1_nibble_sel  : 3;
5972 		mmr_t	reserved_2           : 1;
5973 		mmr_t	trigger1_chiplet_sel : 3;
5974 		mmr_t	reserved_1           : 1;
5975 		mmr_t	trigger0_nibble_sel  : 3;
5976 		mmr_t	reserved_0           : 1;
5977 		mmr_t	trigger0_chiplet_sel : 3;
5989 	mmr_t	sh_pi_crbp_xb_pipe_compare_0_regval;
5991 		mmr_t	compare_address : 47;
5992 		mmr_t	compare_command : 8;
5993 		mmr_t	reserved_0      : 9;
5998 	mmr_t	sh_pi_crbp_xb_pipe_compare_0_regval;
6000 		mmr_t	reserved_0      : 9;
6001 		mmr_t	compare_command : 8;
6002 		mmr_t	compare_address : 47;
6014 	mmr_t	sh_pi_crbp_xb_pipe_compare_1_regval;
6016 		mmr_t	compare_source       : 14;
6017 		mmr_t	reserved_0           : 2;
6018 		mmr_t	compare_supplemental : 14;
6019 		mmr_t	reserved_1           : 2;
6020 		mmr_t	compare_echo         : 9;
6021 		mmr_t	reserved_2           : 23;
6026 	mmr_t	sh_pi_crbp_xb_pipe_compare_1_regval;
6028 		mmr_t	reserved_2           : 23;
6029 		mmr_t	compare_echo         : 9;
6030 		mmr_t	reserved_1           : 2;
6031 		mmr_t	compare_supplemental : 14;
6032 		mmr_t	reserved_0           : 2;
6033 		mmr_t	compare_source       : 14;
6045 	mmr_t	sh_pi_crbp_xb_pipe_mask_0_regval;
6047 		mmr_t	compare_address_mask : 47;
6048 		mmr_t	compare_command_mask : 8;
6049 		mmr_t	reserved_0           : 9;
6054 	mmr_t	sh_pi_crbp_xb_pipe_mask_0_regval;
6056 		mmr_t	reserved_0           : 9;
6057 		mmr_t	compare_command_mask : 8;
6058 		mmr_t	compare_address_mask : 47;
6070 	mmr_t	sh_pi_crbp_xb_pipe_mask_1_regval;
6072 		mmr_t	compare_source_mask       : 14;
6073 		mmr_t	reserved_0                : 2;
6074 		mmr_t	compare_supplemental_mask : 14;
6075 		mmr_t	reserved_1                : 2;
6076 		mmr_t	compare_echo_mask         : 9;
6077 		mmr_t	reserved_2                : 23;
6082 	mmr_t	sh_pi_crbp_xb_pipe_mask_1_regval;
6084 		mmr_t	reserved_2                : 23;
6085 		mmr_t	compare_echo_mask         : 9;
6086 		mmr_t	reserved_1                : 2;
6087 		mmr_t	compare_supplemental_mask : 14;
6088 		mmr_t	reserved_0                : 2;
6089 		mmr_t	compare_source_mask       : 14;
6101 	mmr_t	sh_pi_dpc_queue_config_regval;
6103 		mmr_t	dwcq_ae_level  : 5;
6104 		mmr_t	reserved_0     : 3;
6105 		mmr_t	dwcq_af_thresh : 5;
6106 		mmr_t	reserved_1     : 3;
6107 		mmr_t	fwcq_ae_level  : 5;
6108 		mmr_t	reserved_2     : 3;
6109 		mmr_t	fwcq_af_thresh : 5;
6110 		mmr_t	reserved_3     : 35;
6115 	mmr_t	sh_pi_dpc_queue_config_regval;
6117 		mmr_t	reserved_3     : 35;
6118 		mmr_t	fwcq_af_thresh : 5;
6119 		mmr_t	reserved_2     : 3;
6120 		mmr_t	fwcq_ae_level  : 5;
6121 		mmr_t	reserved_1     : 3;
6122 		mmr_t	dwcq_af_thresh : 5;
6123 		mmr_t	reserved_0     : 3;
6124 		mmr_t	dwcq_ae_level  : 5;
6136 	mmr_t	sh_pi_error_mask_regval;
6138 		mmr_t	fsb_proto_err   : 1;
6139 		mmr_t	gfx_rp_err      : 1;
6140 		mmr_t	xb_proto_err    : 1;
6141 		mmr_t	mem_rp_err      : 1;
6142 		mmr_t	pio_rp_err      : 1;
6143 		mmr_t	mem_to_err      : 1;
6144 		mmr_t	pio_to_err      : 1;
6145 		mmr_t	fsb_shub_uce    : 1;
6146 		mmr_t	fsb_shub_ce     : 1;
6147 		mmr_t	msg_color_err   : 1;
6148 		mmr_t	md_rq_q_oflow   : 1;
6149 		mmr_t	md_rp_q_oflow   : 1;
6150 		mmr_t	xn_rq_q_oflow   : 1;
6151 		mmr_t	xn_rp_q_oflow   : 1;
6152 		mmr_t	nack_oflow      : 1;
6153 		mmr_t	gfx_int_0       : 1;
6154 		mmr_t	gfx_int_1       : 1;
6155 		mmr_t	md_rq_crd_oflow : 1;
6156 		mmr_t	md_rp_crd_oflow : 1;
6157 		mmr_t	xn_rq_crd_oflow : 1;
6158 		mmr_t	xn_rp_crd_oflow : 1;
6159 		mmr_t	hung_bus        : 1;
6160 		mmr_t	rsp_parity      : 1;
6161 		mmr_t	ioq_overrun     : 1;
6162 		mmr_t	req_format      : 1;
6163 		mmr_t	addr_access     : 1;
6164 		mmr_t	req_parity      : 1;
6165 		mmr_t	addr_parity     : 1;
6166 		mmr_t	shub_fsb_dqe    : 1;
6167 		mmr_t	shub_fsb_uce    : 1;
6168 		mmr_t	shub_fsb_ce     : 1;
6169 		mmr_t	livelock        : 1;
6170 		mmr_t	bad_snoop       : 1;
6171 		mmr_t	fsb_tbl_miss    : 1;
6172 		mmr_t	msg_length      : 1;
6173 		mmr_t	reserved_0      : 29;
6178 	mmr_t	sh_pi_error_mask_regval;
6180 		mmr_t	reserved_0      : 29;
6181 		mmr_t	msg_length      : 1;
6182 		mmr_t	fsb_tbl_miss    : 1;
6183 		mmr_t	bad_snoop       : 1;
6184 		mmr_t	livelock        : 1;
6185 		mmr_t	shub_fsb_ce     : 1;
6186 		mmr_t	shub_fsb_uce    : 1;
6187 		mmr_t	shub_fsb_dqe    : 1;
6188 		mmr_t	addr_parity     : 1;
6189 		mmr_t	req_parity      : 1;
6190 		mmr_t	addr_access     : 1;
6191 		mmr_t	req_format      : 1;
6192 		mmr_t	ioq_overrun     : 1;
6193 		mmr_t	rsp_parity      : 1;
6194 		mmr_t	hung_bus        : 1;
6195 		mmr_t	xn_rp_crd_oflow : 1;
6196 		mmr_t	xn_rq_crd_oflow : 1;
6197 		mmr_t	md_rp_crd_oflow : 1;
6198 		mmr_t	md_rq_crd_oflow : 1;
6199 		mmr_t	gfx_int_1       : 1;
6200 		mmr_t	gfx_int_0       : 1;
6201 		mmr_t	nack_oflow      : 1;
6202 		mmr_t	xn_rp_q_oflow   : 1;
6203 		mmr_t	xn_rq_q_oflow   : 1;
6204 		mmr_t	md_rp_q_oflow   : 1;
6205 		mmr_t	md_rq_q_oflow   : 1;
6206 		mmr_t	msg_color_err   : 1;
6207 		mmr_t	fsb_shub_ce     : 1;
6208 		mmr_t	fsb_shub_uce    : 1;
6209 		mmr_t	pio_to_err      : 1;
6210 		mmr_t	mem_to_err      : 1;
6211 		mmr_t	pio_rp_err      : 1;
6212 		mmr_t	mem_rp_err      : 1;
6213 		mmr_t	xb_proto_err    : 1;
6214 		mmr_t	gfx_rp_err      : 1;
6215 		mmr_t	fsb_proto_err   : 1;
6227 	mmr_t	sh_pi_express_reply_config_regval;
6229 		mmr_t	mode        : 3;
6230 		mmr_t	reserved_0  : 61;
6235 	mmr_t	sh_pi_express_reply_config_regval;
6237 		mmr_t	reserved_0  : 61;
6238 		mmr_t	mode        : 3;
6250 	mmr_t	sh_pi_fsb_compare_value_regval;
6252 		mmr_t	compare_value : 64;
6257 	mmr_t	sh_pi_fsb_compare_value_regval;
6259 		mmr_t	compare_value : 64;
6271 	mmr_t	sh_pi_fsb_compare_mask_regval;
6273 		mmr_t	mask_value  : 64;
6278 	mmr_t	sh_pi_fsb_compare_mask_regval;
6280 		mmr_t	mask_value  : 64;
6292 	mmr_t	sh_pi_fsb_error_injection_regval;
6294 		mmr_t	rp_pe_to_fsb     : 1;
6295 		mmr_t	ap0_pe_to_fsb    : 1;
6296 		mmr_t	ap1_pe_to_fsb    : 1;
6297 		mmr_t	rsp_pe_to_fsb    : 1;
6298 		mmr_t	dw0_ce_to_fsb    : 1;
6299 		mmr_t	dw0_uce_to_fsb   : 1;
6300 		mmr_t	dw1_ce_to_fsb    : 1;
6301 		mmr_t	dw1_uce_to_fsb   : 1;
6302 		mmr_t	ip0_pe_to_fsb    : 1;
6303 		mmr_t	ip1_pe_to_fsb    : 1;
6304 		mmr_t	reserved_0       : 6;
6305 		mmr_t	rp_pe_from_fsb   : 1;
6306 		mmr_t	ap0_pe_from_fsb  : 1;
6307 		mmr_t	ap1_pe_from_fsb  : 1;
6308 		mmr_t	rsp_pe_from_fsb  : 1;
6309 		mmr_t	dw0_ce_from_fsb  : 1;
6310 		mmr_t	dw0_uce_from_fsb : 1;
6311 		mmr_t	dw1_ce_from_fsb  : 1;
6312 		mmr_t	dw1_uce_from_fsb : 1;
6313 		mmr_t	dw2_ce_from_fsb  : 1;
6314 		mmr_t	dw2_uce_from_fsb : 1;
6315 		mmr_t	dw3_ce_from_fsb  : 1;
6316 		mmr_t	dw3_uce_from_fsb : 1;
6317 		mmr_t	reserved_1       : 4;
6318 		mmr_t	ioq_overrun      : 1;
6319 		mmr_t	livelock         : 1;
6320 		mmr_t	bus_hang         : 1;
6321 		mmr_t	reserved_2       : 29;
6326 	mmr_t	sh_pi_fsb_error_injection_regval;
6328 		mmr_t	reserved_2       : 29;
6329 		mmr_t	bus_hang         : 1;
6330 		mmr_t	livelock         : 1;
6331 		mmr_t	ioq_overrun      : 1;
6332 		mmr_t	reserved_1       : 4;
6333 		mmr_t	dw3_uce_from_fsb : 1;
6334 		mmr_t	dw3_ce_from_fsb  : 1;
6335 		mmr_t	dw2_uce_from_fsb : 1;
6336 		mmr_t	dw2_ce_from_fsb  : 1;
6337 		mmr_t	dw1_uce_from_fsb : 1;
6338 		mmr_t	dw1_ce_from_fsb  : 1;
6339 		mmr_t	dw0_uce_from_fsb : 1;
6340 		mmr_t	dw0_ce_from_fsb  : 1;
6341 		mmr_t	rsp_pe_from_fsb  : 1;
6342 		mmr_t	ap1_pe_from_fsb  : 1;
6343 		mmr_t	ap0_pe_from_fsb  : 1;
6344 		mmr_t	rp_pe_from_fsb   : 1;
6345 		mmr_t	reserved_0       : 6;
6346 		mmr_t	ip1_pe_to_fsb    : 1;
6347 		mmr_t	ip0_pe_to_fsb    : 1;
6348 		mmr_t	dw1_uce_to_fsb   : 1;
6349 		mmr_t	dw1_ce_to_fsb    : 1;
6350 		mmr_t	dw0_uce_to_fsb   : 1;
6351 		mmr_t	dw0_ce_to_fsb    : 1;
6352 		mmr_t	rsp_pe_to_fsb    : 1;
6353 		mmr_t	ap1_pe_to_fsb    : 1;
6354 		mmr_t	ap0_pe_to_fsb    : 1;
6355 		mmr_t	rp_pe_to_fsb     : 1;
6367 	mmr_t	sh_pi_md2pi_reply_vc_config_regval;
6369 		mmr_t	hdr_depth             : 4;
6370 		mmr_t	data_depth            : 4;
6371 		mmr_t	max_credits           : 6;
6372 		mmr_t	reserved_0            : 48;
6373 		mmr_t	force_credit          : 1;
6374 		mmr_t	capture_credit_status : 1;
6379 	mmr_t	sh_pi_md2pi_reply_vc_config_regval;
6381 		mmr_t	capture_credit_status : 1;
6382 		mmr_t	force_credit          : 1;
6383 		mmr_t	reserved_0            : 48;
6384 		mmr_t	max_credits           : 6;
6385 		mmr_t	data_depth            : 4;
6386 		mmr_t	hdr_depth             : 4;
6398 	mmr_t	sh_pi_md2pi_request_vc_config_regval;
6400 		mmr_t	hdr_depth             : 4;
6401 		mmr_t	data_depth            : 4;
6402 		mmr_t	max_credits           : 6;
6403 		mmr_t	reserved_0            : 48;
6404 		mmr_t	force_credit          : 1;
6405 		mmr_t	capture_credit_status : 1;
6410 	mmr_t	sh_pi_md2pi_request_vc_config_regval;
6412 		mmr_t	capture_credit_status : 1;
6413 		mmr_t	force_credit          : 1;
6414 		mmr_t	reserved_0            : 48;
6415 		mmr_t	max_credits           : 6;
6416 		mmr_t	data_depth            : 4;
6417 		mmr_t	hdr_depth             : 4;
6429 	mmr_t	sh_pi_queue_error_injection_regval;
6431 		mmr_t	dat_dfr_q      : 1;
6432 		mmr_t	dxb_wtl_cmnd_q : 1;
6433 		mmr_t	fsb_wtl_cmnd_q : 1;
6434 		mmr_t	mdpi_rpy_bfr   : 1;
6435 		mmr_t	ptc_intr       : 1;
6436 		mmr_t	rxl_kill_q     : 1;
6437 		mmr_t	rxl_rdy_q      : 1;
6438 		mmr_t	xnpi_rpy_bfr   : 1;
6439 		mmr_t	reserved_0     : 56;
6444 	mmr_t	sh_pi_queue_error_injection_regval;
6446 		mmr_t	reserved_0     : 56;
6447 		mmr_t	xnpi_rpy_bfr   : 1;
6448 		mmr_t	rxl_rdy_q      : 1;
6449 		mmr_t	rxl_kill_q     : 1;
6450 		mmr_t	ptc_intr       : 1;
6451 		mmr_t	mdpi_rpy_bfr   : 1;
6452 		mmr_t	fsb_wtl_cmnd_q : 1;
6453 		mmr_t	dxb_wtl_cmnd_q : 1;
6454 		mmr_t	dat_dfr_q      : 1;
6466 	mmr_t	sh_pi_test_point_compare_regval;
6468 		mmr_t	compare_mask    : 32;
6469 		mmr_t	compare_pattern : 32;
6474 	mmr_t	sh_pi_test_point_compare_regval;
6476 		mmr_t	compare_pattern : 32;
6477 		mmr_t	compare_mask    : 32;
6489 	mmr_t	sh_pi_test_point_select_regval;
6491 		mmr_t	nibble0_chiplet_sel : 3;
6492 		mmr_t	reserved_0          : 1;
6493 		mmr_t	nibble0_nibble_sel  : 3;
6494 		mmr_t	reserved_1          : 1;
6495 		mmr_t	nibble1_chiplet_sel : 3;
6496 		mmr_t	reserved_2          : 1;
6497 		mmr_t	nibble1_nibble_sel  : 3;
6498 		mmr_t	reserved_3          : 1;
6499 		mmr_t	nibble2_chiplet_sel : 3;
6500 		mmr_t	reserved_4          : 1;
6501 		mmr_t	nibble2_nibble_sel  : 3;
6502 		mmr_t	reserved_5          : 1;
6503 		mmr_t	nibble3_chiplet_sel : 3;
6504 		mmr_t	reserved_6          : 1;
6505 		mmr_t	nibble3_nibble_sel  : 3;
6506 		mmr_t	reserved_7          : 1;
6507 		mmr_t	nibble4_chiplet_sel : 3;
6508 		mmr_t	reserved_8          : 1;
6509 		mmr_t	nibble4_nibble_sel  : 3;
6510 		mmr_t	reserved_9          : 1;
6511 		mmr_t	nibble5_chiplet_sel : 3;
6512 		mmr_t	reserved_10         : 1;
6513 		mmr_t	nibble5_nibble_sel  : 3;
6514 		mmr_t	reserved_11         : 1;
6515 		mmr_t	nibble6_chiplet_sel : 3;
6516 		mmr_t	reserved_12         : 1;
6517 		mmr_t	nibble6_nibble_sel  : 3;
6518 		mmr_t	reserved_13         : 1;
6519 		mmr_t	nibble7_chiplet_sel : 3;
6520 		mmr_t	reserved_14         : 1;
6521 		mmr_t	nibble7_nibble_sel  : 3;
6522 		mmr_t	trigger_enable      : 1;
6527 	mmr_t	sh_pi_test_point_select_regval;
6529 		mmr_t	trigger_enable      : 1;
6530 		mmr_t	nibble7_nibble_sel  : 3;
6531 		mmr_t	reserved_14         : 1;
6532 		mmr_t	nibble7_chiplet_sel : 3;
6533 		mmr_t	reserved_13         : 1;
6534 		mmr_t	nibble6_nibble_sel  : 3;
6535 		mmr_t	reserved_12         : 1;
6536 		mmr_t	nibble6_chiplet_sel : 3;
6537 		mmr_t	reserved_11         : 1;
6538 		mmr_t	nibble5_nibble_sel  : 3;
6539 		mmr_t	reserved_10         : 1;
6540 		mmr_t	nibble5_chiplet_sel : 3;
6541 		mmr_t	reserved_9          : 1;
6542 		mmr_t	nibble4_nibble_sel  : 3;
6543 		mmr_t	reserved_8          : 1;
6544 		mmr_t	nibble4_chiplet_sel : 3;
6545 		mmr_t	reserved_7          : 1;
6546 		mmr_t	nibble3_nibble_sel  : 3;
6547 		mmr_t	reserved_6          : 1;
6548 		mmr_t	nibble3_chiplet_sel : 3;
6549 		mmr_t	reserved_5          : 1;
6550 		mmr_t	nibble2_nibble_sel  : 3;
6551 		mmr_t	reserved_4          : 1;
6552 		mmr_t	nibble2_chiplet_sel : 3;
6553 		mmr_t	reserved_3          : 1;
6554 		mmr_t	nibble1_nibble_sel  : 3;
6555 		mmr_t	reserved_2          : 1;
6556 		mmr_t	nibble1_chiplet_sel : 3;
6557 		mmr_t	reserved_1          : 1;
6558 		mmr_t	nibble0_nibble_sel  : 3;
6559 		mmr_t	reserved_0          : 1;
6560 		mmr_t	nibble0_chiplet_sel : 3;
6572 	mmr_t	sh_pi_test_point_trigger_select_regval;
6574 		mmr_t	trigger0_chiplet_sel : 3;
6575 		mmr_t	reserved_0           : 1;
6576 		mmr_t	trigger0_nibble_sel  : 3;
6577 		mmr_t	reserved_1           : 1;
6578 		mmr_t	trigger1_chiplet_sel : 3;
6579 		mmr_t	reserved_2           : 1;
6580 		mmr_t	trigger1_nibble_sel  : 3;
6581 		mmr_t	reserved_3           : 1;
6582 		mmr_t	trigger2_chiplet_sel : 3;
6583 		mmr_t	reserved_4           : 1;
6584 		mmr_t	trigger2_nibble_sel  : 3;
6585 		mmr_t	reserved_5           : 1;
6586 		mmr_t	trigger3_chiplet_sel : 3;
6587 		mmr_t	reserved_6           : 1;
6588 		mmr_t	trigger3_nibble_sel  : 3;
6589 		mmr_t	reserved_7           : 1;
6590 		mmr_t	trigger4_chiplet_sel : 3;
6591 		mmr_t	reserved_8           : 1;
6592 		mmr_t	trigger4_nibble_sel  : 3;
6593 		mmr_t	reserved_9           : 1;
6594 		mmr_t	trigger5_chiplet_sel : 3;
6595 		mmr_t	reserved_10          : 1;
6596 		mmr_t	trigger5_nibble_sel  : 3;
6597 		mmr_t	reserved_11          : 1;
6598 		mmr_t	trigger6_chiplet_sel : 3;
6599 		mmr_t	reserved_12          : 1;
6600 		mmr_t	trigger6_nibble_sel  : 3;
6601 		mmr_t	reserved_13          : 1;
6602 		mmr_t	trigger7_chiplet_sel : 3;
6603 		mmr_t	reserved_14          : 1;
6604 		mmr_t	trigger7_nibble_sel  : 3;
6605 		mmr_t	reserved_15          : 1;
6610 	mmr_t	sh_pi_test_point_trigger_select_regval;
6612 		mmr_t	reserved_15          : 1;
6613 		mmr_t	trigger7_nibble_sel  : 3;
6614 		mmr_t	reserved_14          : 1;
6615 		mmr_t	trigger7_chiplet_sel : 3;
6616 		mmr_t	reserved_13          : 1;
6617 		mmr_t	trigger6_nibble_sel  : 3;
6618 		mmr_t	reserved_12          : 1;
6619 		mmr_t	trigger6_chiplet_sel : 3;
6620 		mmr_t	reserved_11          : 1;
6621 		mmr_t	trigger5_nibble_sel  : 3;
6622 		mmr_t	reserved_10          : 1;
6623 		mmr_t	trigger5_chiplet_sel : 3;
6624 		mmr_t	reserved_9           : 1;
6625 		mmr_t	trigger4_nibble_sel  : 3;
6626 		mmr_t	reserved_8           : 1;
6627 		mmr_t	trigger4_chiplet_sel : 3;
6628 		mmr_t	reserved_7           : 1;
6629 		mmr_t	trigger3_nibble_sel  : 3;
6630 		mmr_t	reserved_6           : 1;
6631 		mmr_t	trigger3_chiplet_sel : 3;
6632 		mmr_t	reserved_5           : 1;
6633 		mmr_t	trigger2_nibble_sel  : 3;
6634 		mmr_t	reserved_4           : 1;
6635 		mmr_t	trigger2_chiplet_sel : 3;
6636 		mmr_t	reserved_3           : 1;
6637 		mmr_t	trigger1_nibble_sel  : 3;
6638 		mmr_t	reserved_2           : 1;
6639 		mmr_t	trigger1_chiplet_sel : 3;
6640 		mmr_t	reserved_1           : 1;
6641 		mmr_t	trigger0_nibble_sel  : 3;
6642 		mmr_t	reserved_0           : 1;
6643 		mmr_t	trigger0_chiplet_sel : 3;
6655 	mmr_t	sh_pi_xn2pi_reply_vc_config_regval;
6657 		mmr_t	hdr_depth             : 4;
6658 		mmr_t	data_depth            : 4;
6659 		mmr_t	max_credits           : 6;
6660 		mmr_t	reserved_0            : 48;
6661 		mmr_t	force_credit          : 1;
6662 		mmr_t	capture_credit_status : 1;
6667 	mmr_t	sh_pi_xn2pi_reply_vc_config_regval;
6669 		mmr_t	capture_credit_status : 1;
6670 		mmr_t	force_credit          : 1;
6671 		mmr_t	reserved_0            : 48;
6672 		mmr_t	max_credits           : 6;
6673 		mmr_t	data_depth            : 4;
6674 		mmr_t	hdr_depth             : 4;
6686 	mmr_t	sh_pi_xn2pi_request_vc_config_regval;
6688 		mmr_t	hdr_depth             : 4;
6689 		mmr_t	data_depth            : 4;
6690 		mmr_t	max_credits           : 6;
6691 		mmr_t	reserved_0            : 48;
6692 		mmr_t	force_credit          : 1;
6693 		mmr_t	capture_credit_status : 1;
6698 	mmr_t	sh_pi_xn2pi_request_vc_config_regval;
6700 		mmr_t	capture_credit_status : 1;
6701 		mmr_t	force_credit          : 1;
6702 		mmr_t	reserved_0            : 48;
6703 		mmr_t	max_credits           : 6;
6704 		mmr_t	data_depth            : 4;
6705 		mmr_t	hdr_depth             : 4;
6717 	mmr_t	sh_pi_aec_status_regval;
6719 		mmr_t	state       : 3;
6720 		mmr_t	reserved_0  : 61;
6725 	mmr_t	sh_pi_aec_status_regval;
6727 		mmr_t	reserved_0  : 61;
6728 		mmr_t	state       : 3;
6740 	mmr_t	sh_pi_afi_first_error_regval;
6742 		mmr_t	reserved_0   : 7;
6743 		mmr_t	fsb_shub_uce : 1;
6744 		mmr_t	fsb_shub_ce  : 1;
6745 		mmr_t	reserved_1   : 12;
6746 		mmr_t	hung_bus     : 1;
6747 		mmr_t	rsp_parity   : 1;
6748 		mmr_t	ioq_overrun  : 1;
6749 		mmr_t	req_format   : 1;
6750 		mmr_t	addr_access  : 1;
6751 		mmr_t	req_parity   : 1;
6752 		mmr_t	addr_parity  : 1;
6753 		mmr_t	shub_fsb_dqe : 1;
6754 		mmr_t	shub_fsb_uce : 1;
6755 		mmr_t	shub_fsb_ce  : 1;
6756 		mmr_t	livelock     : 1;
6757 		mmr_t	bad_snoop    : 1;
6758 		mmr_t	fsb_tbl_miss : 1;
6759 		mmr_t	msg_len      : 1;
6760 		mmr_t	reserved_2   : 29;
6765 	mmr_t	sh_pi_afi_first_error_regval;
6767 		mmr_t	reserved_2   : 29;
6768 		mmr_t	msg_len      : 1;
6769 		mmr_t	fsb_tbl_miss : 1;
6770 		mmr_t	bad_snoop    : 1;
6771 		mmr_t	livelock     : 1;
6772 		mmr_t	shub_fsb_ce  : 1;
6773 		mmr_t	shub_fsb_uce : 1;
6774 		mmr_t	shub_fsb_dqe : 1;
6775 		mmr_t	addr_parity  : 1;
6776 		mmr_t	req_parity   : 1;
6777 		mmr_t	addr_access  : 1;
6778 		mmr_t	req_format   : 1;
6779 		mmr_t	ioq_overrun  : 1;
6780 		mmr_t	rsp_parity   : 1;
6781 		mmr_t	hung_bus     : 1;
6782 		mmr_t	reserved_1   : 12;
6783 		mmr_t	fsb_shub_ce  : 1;
6784 		mmr_t	fsb_shub_uce : 1;
6785 		mmr_t	reserved_0   : 7;
6797 	mmr_t	sh_pi_cam_address_read_data_regval;
6799 		mmr_t	cam_addr     : 48;
6800 		mmr_t	reserved_0   : 15;
6801 		mmr_t	cam_addr_val : 1;
6806 	mmr_t	sh_pi_cam_address_read_data_regval;
6808 		mmr_t	cam_addr_val : 1;
6809 		mmr_t	reserved_0   : 15;
6810 		mmr_t	cam_addr     : 48;
6822 	mmr_t	sh_pi_cam_lpra_read_data_regval;
6824 		mmr_t	cam_lpra    : 64;
6829 	mmr_t	sh_pi_cam_lpra_read_data_regval;
6831 		mmr_t	cam_lpra    : 64;
6843 	mmr_t	sh_pi_cam_state_read_data_regval;
6845 		mmr_t	cam_state         : 4;
6846 		mmr_t	cam_to            : 1;
6847 		mmr_t	cam_state_rd_pend : 1;
6848 		mmr_t	reserved_0        : 26;
6849 		mmr_t	cam_lpra          : 18;
6850 		mmr_t	reserved_1        : 13;
6851 		mmr_t	cam_rd_data_val   : 1;
6856 	mmr_t	sh_pi_cam_state_read_data_regval;
6858 		mmr_t	cam_rd_data_val   : 1;
6859 		mmr_t	reserved_1        : 13;
6860 		mmr_t	cam_lpra          : 18;
6861 		mmr_t	reserved_0        : 26;
6862 		mmr_t	cam_state_rd_pend : 1;
6863 		mmr_t	cam_to            : 1;
6864 		mmr_t	cam_state         : 4;
6876 	mmr_t	sh_pi_corrected_detail_1_regval;
6878 		mmr_t	address     : 48;
6879 		mmr_t	syndrome    : 8;
6880 		mmr_t	dep         : 8;
6885 	mmr_t	sh_pi_corrected_detail_1_regval;
6887 		mmr_t	dep         : 8;
6888 		mmr_t	syndrome    : 8;
6889 		mmr_t	address     : 48;
6901 	mmr_t	sh_pi_corrected_detail_2_regval;
6903 		mmr_t	data        : 64;
6908 	mmr_t	sh_pi_corrected_detail_2_regval;
6910 		mmr_t	data        : 64;
6922 	mmr_t	sh_pi_corrected_detail_3_regval;
6924 		mmr_t	address     : 48;
6925 		mmr_t	syndrome    : 8;
6926 		mmr_t	dep         : 8;
6931 	mmr_t	sh_pi_corrected_detail_3_regval;
6933 		mmr_t	dep         : 8;
6934 		mmr_t	syndrome    : 8;
6935 		mmr_t	address     : 48;
6947 	mmr_t	sh_pi_corrected_detail_4_regval;
6949 		mmr_t	data        : 64;
6954 	mmr_t	sh_pi_corrected_detail_4_regval;
6956 		mmr_t	data        : 64;
6968 	mmr_t	sh_pi_crbp_first_error_regval;
6970 		mmr_t	fsb_proto_err   : 1;
6971 		mmr_t	gfx_rp_err      : 1;
6972 		mmr_t	xb_proto_err    : 1;
6973 		mmr_t	mem_rp_err      : 1;
6974 		mmr_t	pio_rp_err      : 1;
6975 		mmr_t	mem_to_err      : 1;
6976 		mmr_t	pio_to_err      : 1;
6977 		mmr_t	fsb_shub_uce    : 1;
6978 		mmr_t	fsb_shub_ce     : 1;
6979 		mmr_t	msg_color_err   : 1;
6980 		mmr_t	md_rq_q_oflow   : 1;
6981 		mmr_t	md_rp_q_oflow   : 1;
6982 		mmr_t	xn_rq_q_oflow   : 1;
6983 		mmr_t	xn_rp_q_oflow   : 1;
6984 		mmr_t	nack_oflow      : 1;
6985 		mmr_t	gfx_int_0       : 1;
6986 		mmr_t	gfx_int_1       : 1;
6987 		mmr_t	md_rq_crd_oflow : 1;
6988 		mmr_t	md_rp_crd_oflow : 1;
6989 		mmr_t	xn_rq_crd_oflow : 1;
6990 		mmr_t	xn_rp_crd_oflow : 1;
6991 		mmr_t	reserved_0      : 43;
6996 	mmr_t	sh_pi_crbp_first_error_regval;
6998 		mmr_t	reserved_0      : 43;
6999 		mmr_t	xn_rp_crd_oflow : 1;
7000 		mmr_t	xn_rq_crd_oflow : 1;
7001 		mmr_t	md_rp_crd_oflow : 1;
7002 		mmr_t	md_rq_crd_oflow : 1;
7003 		mmr_t	gfx_int_1       : 1;
7004 		mmr_t	gfx_int_0       : 1;
7005 		mmr_t	nack_oflow      : 1;
7006 		mmr_t	xn_rp_q_oflow   : 1;
7007 		mmr_t	xn_rq_q_oflow   : 1;
7008 		mmr_t	md_rp_q_oflow   : 1;
7009 		mmr_t	md_rq_q_oflow   : 1;
7010 		mmr_t	msg_color_err   : 1;
7011 		mmr_t	fsb_shub_ce     : 1;
7012 		mmr_t	fsb_shub_uce    : 1;
7013 		mmr_t	pio_to_err      : 1;
7014 		mmr_t	mem_to_err      : 1;
7015 		mmr_t	pio_rp_err      : 1;
7016 		mmr_t	mem_rp_err      : 1;
7017 		mmr_t	xb_proto_err    : 1;
7018 		mmr_t	gfx_rp_err      : 1;
7019 		mmr_t	fsb_proto_err   : 1;
7031 	mmr_t	sh_pi_error_detail_1_regval;
7033 		mmr_t	status      : 64;
7038 	mmr_t	sh_pi_error_detail_1_regval;
7040 		mmr_t	status      : 64;
7052 	mmr_t	sh_pi_error_detail_2_regval;
7054 		mmr_t	status      : 64;
7059 	mmr_t	sh_pi_error_detail_2_regval;
7061 		mmr_t	status      : 64;
7073 	mmr_t	sh_pi_error_overflow_regval;
7075 		mmr_t	fsb_proto_err   : 1;
7076 		mmr_t	gfx_rp_err      : 1;
7077 		mmr_t	xb_proto_err    : 1;
7078 		mmr_t	mem_rp_err      : 1;
7079 		mmr_t	pio_rp_err      : 1;
7080 		mmr_t	mem_to_err      : 1;
7081 		mmr_t	pio_to_err      : 1;
7082 		mmr_t	fsb_shub_uce    : 1;
7083 		mmr_t	fsb_shub_ce     : 1;
7084 		mmr_t	msg_color_err   : 1;
7085 		mmr_t	md_rq_q_oflow   : 1;
7086 		mmr_t	md_rp_q_oflow   : 1;
7087 		mmr_t	xn_rq_q_oflow   : 1;
7088 		mmr_t	xn_rp_q_oflow   : 1;
7089 		mmr_t	nack_oflow      : 1;
7090 		mmr_t	gfx_int_0       : 1;
7091 		mmr_t	gfx_int_1       : 1;
7092 		mmr_t	md_rq_crd_oflow : 1;
7093 		mmr_t	md_rp_crd_oflow : 1;
7094 		mmr_t	xn_rq_crd_oflow : 1;
7095 		mmr_t	xn_rp_crd_oflow : 1;
7096 		mmr_t	hung_bus        : 1;
7097 		mmr_t	rsp_parity      : 1;
7098 		mmr_t	ioq_overrun     : 1;
7099 		mmr_t	req_format      : 1;
7100 		mmr_t	addr_access     : 1;
7101 		mmr_t	req_parity      : 1;
7102 		mmr_t	addr_parity     : 1;
7103 		mmr_t	shub_fsb_dqe    : 1;
7104 		mmr_t	shub_fsb_uce    : 1;
7105 		mmr_t	shub_fsb_ce     : 1;
7106 		mmr_t	livelock        : 1;
7107 		mmr_t	bad_snoop       : 1;
7108 		mmr_t	fsb_tbl_miss    : 1;
7109 		mmr_t	msg_length      : 1;
7110 		mmr_t	reserved_0      : 29;
7115 	mmr_t	sh_pi_error_overflow_regval;
7117 		mmr_t	reserved_0      : 29;
7118 		mmr_t	msg_length      : 1;
7119 		mmr_t	fsb_tbl_miss    : 1;
7120 		mmr_t	bad_snoop       : 1;
7121 		mmr_t	livelock        : 1;
7122 		mmr_t	shub_fsb_ce     : 1;
7123 		mmr_t	shub_fsb_uce    : 1;
7124 		mmr_t	shub_fsb_dqe    : 1;
7125 		mmr_t	addr_parity     : 1;
7126 		mmr_t	req_parity      : 1;
7127 		mmr_t	addr_access     : 1;
7128 		mmr_t	req_format      : 1;
7129 		mmr_t	ioq_overrun     : 1;
7130 		mmr_t	rsp_parity      : 1;
7131 		mmr_t	hung_bus        : 1;
7132 		mmr_t	xn_rp_crd_oflow : 1;
7133 		mmr_t	xn_rq_crd_oflow : 1;
7134 		mmr_t	md_rp_crd_oflow : 1;
7135 		mmr_t	md_rq_crd_oflow : 1;
7136 		mmr_t	gfx_int_1       : 1;
7137 		mmr_t	gfx_int_0       : 1;
7138 		mmr_t	nack_oflow      : 1;
7139 		mmr_t	xn_rp_q_oflow   : 1;
7140 		mmr_t	xn_rq_q_oflow   : 1;
7141 		mmr_t	md_rp_q_oflow   : 1;
7142 		mmr_t	md_rq_q_oflow   : 1;
7143 		mmr_t	msg_color_err   : 1;
7144 		mmr_t	fsb_shub_ce     : 1;
7145 		mmr_t	fsb_shub_uce    : 1;
7146 		mmr_t	pio_to_err      : 1;
7147 		mmr_t	mem_to_err      : 1;
7148 		mmr_t	pio_rp_err      : 1;
7149 		mmr_t	mem_rp_err      : 1;
7150 		mmr_t	xb_proto_err    : 1;
7151 		mmr_t	gfx_rp_err      : 1;
7152 		mmr_t	fsb_proto_err   : 1;
7164 	mmr_t	sh_pi_error_summary_regval;
7166 		mmr_t	fsb_proto_err   : 1;
7167 		mmr_t	gfx_rp_err      : 1;
7168 		mmr_t	xb_proto_err    : 1;
7169 		mmr_t	mem_rp_err      : 1;
7170 		mmr_t	pio_rp_err      : 1;
7171 		mmr_t	mem_to_err      : 1;
7172 		mmr_t	pio_to_err      : 1;
7173 		mmr_t	fsb_shub_uce    : 1;
7174 		mmr_t	fsb_shub_ce     : 1;
7175 		mmr_t	msg_color_err   : 1;
7176 		mmr_t	md_rq_q_oflow   : 1;
7177 		mmr_t	md_rp_q_oflow   : 1;
7178 		mmr_t	xn_rq_q_oflow   : 1;
7179 		mmr_t	xn_rp_q_oflow   : 1;
7180 		mmr_t	nack_oflow      : 1;
7181 		mmr_t	gfx_int_0       : 1;
7182 		mmr_t	gfx_int_1       : 1;
7183 		mmr_t	md_rq_crd_oflow : 1;
7184 		mmr_t	md_rp_crd_oflow : 1;
7185 		mmr_t	xn_rq_crd_oflow : 1;
7186 		mmr_t	xn_rp_crd_oflow : 1;
7187 		mmr_t	hung_bus        : 1;
7188 		mmr_t	rsp_parity      : 1;
7189 		mmr_t	ioq_overrun     : 1;
7190 		mmr_t	req_format      : 1;
7191 		mmr_t	addr_access     : 1;
7192 		mmr_t	req_parity      : 1;
7193 		mmr_t	addr_parity     : 1;
7194 		mmr_t	shub_fsb_dqe    : 1;
7195 		mmr_t	shub_fsb_uce    : 1;
7196 		mmr_t	shub_fsb_ce     : 1;
7197 		mmr_t	livelock        : 1;
7198 		mmr_t	bad_snoop       : 1;
7199 		mmr_t	fsb_tbl_miss    : 1;
7200 		mmr_t	msg_length      : 1;
7201 		mmr_t	reserved_0      : 29;
7206 	mmr_t	sh_pi_error_summary_regval;
7208 		mmr_t	reserved_0      : 29;
7209 		mmr_t	msg_length      : 1;
7210 		mmr_t	fsb_tbl_miss    : 1;
7211 		mmr_t	bad_snoop       : 1;
7212 		mmr_t	livelock        : 1;
7213 		mmr_t	shub_fsb_ce     : 1;
7214 		mmr_t	shub_fsb_uce    : 1;
7215 		mmr_t	shub_fsb_dqe    : 1;
7216 		mmr_t	addr_parity     : 1;
7217 		mmr_t	req_parity      : 1;
7218 		mmr_t	addr_access     : 1;
7219 		mmr_t	req_format      : 1;
7220 		mmr_t	ioq_overrun     : 1;
7221 		mmr_t	rsp_parity      : 1;
7222 		mmr_t	hung_bus        : 1;
7223 		mmr_t	xn_rp_crd_oflow : 1;
7224 		mmr_t	xn_rq_crd_oflow : 1;
7225 		mmr_t	md_rp_crd_oflow : 1;
7226 		mmr_t	md_rq_crd_oflow : 1;
7227 		mmr_t	gfx_int_1       : 1;
7228 		mmr_t	gfx_int_0       : 1;
7229 		mmr_t	nack_oflow      : 1;
7230 		mmr_t	xn_rp_q_oflow   : 1;
7231 		mmr_t	xn_rq_q_oflow   : 1;
7232 		mmr_t	md_rp_q_oflow   : 1;
7233 		mmr_t	md_rq_q_oflow   : 1;
7234 		mmr_t	msg_color_err   : 1;
7235 		mmr_t	fsb_shub_ce     : 1;
7236 		mmr_t	fsb_shub_uce    : 1;
7237 		mmr_t	pio_to_err      : 1;
7238 		mmr_t	mem_to_err      : 1;
7239 		mmr_t	pio_rp_err      : 1;
7240 		mmr_t	mem_rp_err      : 1;
7241 		mmr_t	xb_proto_err    : 1;
7242 		mmr_t	gfx_rp_err      : 1;
7243 		mmr_t	fsb_proto_err   : 1;
7255 	mmr_t	sh_pi_express_reply_status_regval;
7257 		mmr_t	state       : 3;
7258 		mmr_t	reserved_0  : 61;
7263 	mmr_t	sh_pi_express_reply_status_regval;
7265 		mmr_t	reserved_0  : 61;
7266 		mmr_t	state       : 3;
7278 	mmr_t	sh_pi_first_error_regval;
7280 		mmr_t	fsb_proto_err   : 1;
7281 		mmr_t	gfx_rp_err      : 1;
7282 		mmr_t	xb_proto_err    : 1;
7283 		mmr_t	mem_rp_err      : 1;
7284 		mmr_t	pio_rp_err      : 1;
7285 		mmr_t	mem_to_err      : 1;
7286 		mmr_t	pio_to_err      : 1;
7287 		mmr_t	fsb_shub_uce    : 1;
7288 		mmr_t	fsb_shub_ce     : 1;
7289 		mmr_t	msg_color_err   : 1;
7290 		mmr_t	md_rq_q_oflow   : 1;
7291 		mmr_t	md_rp_q_oflow   : 1;
7292 		mmr_t	xn_rq_q_oflow   : 1;
7293 		mmr_t	xn_rp_q_oflow   : 1;
7294 		mmr_t	nack_oflow      : 1;
7295 		mmr_t	gfx_int_0       : 1;
7296 		mmr_t	gfx_int_1       : 1;
7297 		mmr_t	md_rq_crd_oflow : 1;
7298 		mmr_t	md_rp_crd_oflow : 1;
7299 		mmr_t	xn_rq_crd_oflow : 1;
7300 		mmr_t	xn_rp_crd_oflow : 1;
7301 		mmr_t	hung_bus        : 1;
7302 		mmr_t	rsp_parity      : 1;
7303 		mmr_t	ioq_overrun     : 1;
7304 		mmr_t	req_format      : 1;
7305 		mmr_t	addr_access     : 1;
7306 		mmr_t	req_parity      : 1;
7307 		mmr_t	addr_parity     : 1;
7308 		mmr_t	shub_fsb_dqe    : 1;
7309 		mmr_t	shub_fsb_uce    : 1;
7310 		mmr_t	shub_fsb_ce     : 1;
7311 		mmr_t	livelock        : 1;
7312 		mmr_t	bad_snoop       : 1;
7313 		mmr_t	fsb_tbl_miss    : 1;
7314 		mmr_t	msg_length      : 1;
7315 		mmr_t	reserved_0      : 29;
7320 	mmr_t	sh_pi_first_error_regval;
7322 		mmr_t	reserved_0      : 29;
7323 		mmr_t	msg_length      : 1;
7324 		mmr_t	fsb_tbl_miss    : 1;
7325 		mmr_t	bad_snoop       : 1;
7326 		mmr_t	livelock        : 1;
7327 		mmr_t	shub_fsb_ce     : 1;
7328 		mmr_t	shub_fsb_uce    : 1;
7329 		mmr_t	shub_fsb_dqe    : 1;
7330 		mmr_t	addr_parity     : 1;
7331 		mmr_t	req_parity      : 1;
7332 		mmr_t	addr_access     : 1;
7333 		mmr_t	req_format      : 1;
7334 		mmr_t	ioq_overrun     : 1;
7335 		mmr_t	rsp_parity      : 1;
7336 		mmr_t	hung_bus        : 1;
7337 		mmr_t	xn_rp_crd_oflow : 1;
7338 		mmr_t	xn_rq_crd_oflow : 1;
7339 		mmr_t	md_rp_crd_oflow : 1;
7340 		mmr_t	md_rq_crd_oflow : 1;
7341 		mmr_t	gfx_int_1       : 1;
7342 		mmr_t	gfx_int_0       : 1;
7343 		mmr_t	nack_oflow      : 1;
7344 		mmr_t	xn_rp_q_oflow   : 1;
7345 		mmr_t	xn_rq_q_oflow   : 1;
7346 		mmr_t	md_rp_q_oflow   : 1;
7347 		mmr_t	md_rq_q_oflow   : 1;
7348 		mmr_t	msg_color_err   : 1;
7349 		mmr_t	fsb_shub_ce     : 1;
7350 		mmr_t	fsb_shub_uce    : 1;
7351 		mmr_t	pio_to_err      : 1;
7352 		mmr_t	mem_to_err      : 1;
7353 		mmr_t	pio_rp_err      : 1;
7354 		mmr_t	mem_rp_err      : 1;
7355 		mmr_t	xb_proto_err    : 1;
7356 		mmr_t	gfx_rp_err      : 1;
7357 		mmr_t	fsb_proto_err   : 1;
7369 	mmr_t	sh_pi_pi2md_reply_vc_status_regval;
7371 		mmr_t	output_crd_stat : 6;
7372 		mmr_t	reserved_0      : 58;
7377 	mmr_t	sh_pi_pi2md_reply_vc_status_regval;
7379 		mmr_t	reserved_0      : 58;
7380 		mmr_t	output_crd_stat : 6;
7392 	mmr_t	sh_pi_pi2md_request_vc_status_regval;
7394 		mmr_t	output_crd_stat : 6;
7395 		mmr_t	reserved_0      : 58;
7400 	mmr_t	sh_pi_pi2md_request_vc_status_regval;
7402 		mmr_t	reserved_0      : 58;
7403 		mmr_t	output_crd_stat : 6;
7415 	mmr_t	sh_pi_pi2xn_reply_vc_status_regval;
7417 		mmr_t	output_crd_stat : 6;
7418 		mmr_t	reserved_0      : 58;
7423 	mmr_t	sh_pi_pi2xn_reply_vc_status_regval;
7425 		mmr_t	reserved_0      : 58;
7426 		mmr_t	output_crd_stat : 6;
7438 	mmr_t	sh_pi_pi2xn_request_vc_status_regval;
7440 		mmr_t	output_crd_stat : 6;
7441 		mmr_t	reserved_0      : 58;
7446 	mmr_t	sh_pi_pi2xn_request_vc_status_regval;
7448 		mmr_t	reserved_0      : 58;
7449 		mmr_t	output_crd_stat : 6;
7461 	mmr_t	sh_pi_uncorrected_detail_1_regval;
7463 		mmr_t	address     : 48;
7464 		mmr_t	syndrome    : 8;
7465 		mmr_t	dep         : 8;
7470 	mmr_t	sh_pi_uncorrected_detail_1_regval;
7472 		mmr_t	dep         : 8;
7473 		mmr_t	syndrome    : 8;
7474 		mmr_t	address     : 48;
7486 	mmr_t	sh_pi_uncorrected_detail_2_regval;
7488 		mmr_t	data        : 64;
7493 	mmr_t	sh_pi_uncorrected_detail_2_regval;
7495 		mmr_t	data        : 64;
7507 	mmr_t	sh_pi_uncorrected_detail_3_regval;
7509 		mmr_t	address     : 48;
7510 		mmr_t	syndrome    : 8;
7511 		mmr_t	dep         : 8;
7516 	mmr_t	sh_pi_uncorrected_detail_3_regval;
7518 		mmr_t	dep         : 8;
7519 		mmr_t	syndrome    : 8;
7520 		mmr_t	address     : 48;
7532 	mmr_t	sh_pi_uncorrected_detail_4_regval;
7534 		mmr_t	data        : 64;
7539 	mmr_t	sh_pi_uncorrected_detail_4_regval;
7541 		mmr_t	data        : 64;
7553 	mmr_t	sh_pi_md2pi_reply_vc_status_regval;
7555 		mmr_t	input_hdr_crd_stat : 4;
7556 		mmr_t	input_dat_crd_stat : 4;
7557 		mmr_t	input_queue_stat   : 4;
7558 		mmr_t	reserved_0         : 52;
7563 	mmr_t	sh_pi_md2pi_reply_vc_status_regval;
7565 		mmr_t	reserved_0         : 52;
7566 		mmr_t	input_queue_stat   : 4;
7567 		mmr_t	input_dat_crd_stat : 4;
7568 		mmr_t	input_hdr_crd_stat : 4;
7580 	mmr_t	sh_pi_md2pi_request_vc_status_regval;
7582 		mmr_t	input_hdr_crd_stat : 4;
7583 		mmr_t	input_dat_crd_stat : 4;
7584 		mmr_t	input_queue_stat   : 4;
7585 		mmr_t	reserved_0         : 52;
7590 	mmr_t	sh_pi_md2pi_request_vc_status_regval;
7592 		mmr_t	reserved_0         : 52;
7593 		mmr_t	input_queue_stat   : 4;
7594 		mmr_t	input_dat_crd_stat : 4;
7595 		mmr_t	input_hdr_crd_stat : 4;
7607 	mmr_t	sh_pi_xn2pi_reply_vc_status_regval;
7609 		mmr_t	input_hdr_crd_stat : 4;
7610 		mmr_t	input_dat_crd_stat : 4;
7611 		mmr_t	input_queue_stat   : 4;
7612 		mmr_t	reserved_0         : 52;
7617 	mmr_t	sh_pi_xn2pi_reply_vc_status_regval;
7619 		mmr_t	reserved_0         : 52;
7620 		mmr_t	input_queue_stat   : 4;
7621 		mmr_t	input_dat_crd_stat : 4;
7622 		mmr_t	input_hdr_crd_stat : 4;
7634 	mmr_t	sh_pi_xn2pi_request_vc_status_regval;
7636 		mmr_t	input_hdr_crd_stat : 4;
7637 		mmr_t	input_dat_crd_stat : 4;
7638 		mmr_t	input_queue_stat   : 4;
7639 		mmr_t	reserved_0         : 52;
7644 	mmr_t	sh_pi_xn2pi_request_vc_status_regval;
7646 		mmr_t	reserved_0         : 52;
7647 		mmr_t	input_queue_stat   : 4;
7648 		mmr_t	input_dat_crd_stat : 4;
7649 		mmr_t	input_hdr_crd_stat : 4;
7660 	mmr_t	sh_xnpi_sic_flow_regval;
7662 		mmr_t	debit_vc0_withhold   : 5;
7663 		mmr_t	reserved_0           : 2;
7664 		mmr_t	debit_vc0_force_cred : 1;
7665 		mmr_t	debit_vc2_withhold   : 5;
7666 		mmr_t	reserved_1           : 2;
7667 		mmr_t	debit_vc2_force_cred : 1;
7668 		mmr_t	credit_vc0_test      : 5;
7669 		mmr_t	reserved_2           : 3;
7670 		mmr_t	credit_vc0_dyn       : 5;
7671 		mmr_t	reserved_3           : 3;
7672 		mmr_t	credit_vc0_cap       : 5;
7673 		mmr_t	reserved_4           : 3;
7674 		mmr_t	credit_vc2_test      : 5;
7675 		mmr_t	reserved_5           : 3;
7676 		mmr_t	credit_vc2_dyn       : 5;
7677 		mmr_t	reserved_6           : 3;
7678 		mmr_t	credit_vc2_cap       : 5;
7679 		mmr_t	reserved_7           : 2;
7680 		mmr_t	disable_bypass_out   : 1;
7685 	mmr_t	sh_xnpi_sic_flow_regval;
7687 		mmr_t	disable_bypass_out   : 1;
7688 		mmr_t	reserved_7           : 2;
7689 		mmr_t	credit_vc2_cap       : 5;
7690 		mmr_t	reserved_6           : 3;
7691 		mmr_t	credit_vc2_dyn       : 5;
7692 		mmr_t	reserved_5           : 3;
7693 		mmr_t	credit_vc2_test      : 5;
7694 		mmr_t	reserved_4           : 3;
7695 		mmr_t	credit_vc0_cap       : 5;
7696 		mmr_t	reserved_3           : 3;
7697 		mmr_t	credit_vc0_dyn       : 5;
7698 		mmr_t	reserved_2           : 3;
7699 		mmr_t	credit_vc0_test      : 5;
7700 		mmr_t	debit_vc2_force_cred : 1;
7701 		mmr_t	reserved_1           : 2;
7702 		mmr_t	debit_vc2_withhold   : 5;
7703 		mmr_t	debit_vc0_force_cred : 1;
7704 		mmr_t	reserved_0           : 2;
7705 		mmr_t	debit_vc0_withhold   : 5;
7716 	mmr_t	sh_xnpi_to_ni0_port_flow_regval;
7718 		mmr_t	debit_vc0_withhold   : 6;
7719 		mmr_t	reserved_0           : 1;
7720 		mmr_t	debit_vc0_force_cred : 1;
7721 		mmr_t	debit_vc2_withhold   : 6;
7722 		mmr_t	reserved_1           : 1;
7723 		mmr_t	debit_vc2_force_cred : 1;
7724 		mmr_t	reserved_2           : 8;
7725 		mmr_t	credit_vc0_dyn       : 6;
7726 		mmr_t	reserved_3           : 2;
7727 		mmr_t	credit_vc0_cap       : 6;
7728 		mmr_t	reserved_4           : 10;
7729 		mmr_t	credit_vc2_dyn       : 6;
7730 		mmr_t	reserved_5           : 2;
7731 		mmr_t	credit_vc2_cap       : 6;
7732 		mmr_t	reserved_6           : 2;
7737 	mmr_t	sh_xnpi_to_ni0_port_flow_regval;
7739 		mmr_t	reserved_6           : 2;
7740 		mmr_t	credit_vc2_cap       : 6;
7741 		mmr_t	reserved_5           : 2;
7742 		mmr_t	credit_vc2_dyn       : 6;
7743 		mmr_t	reserved_4           : 10;
7744 		mmr_t	credit_vc0_cap       : 6;
7745 		mmr_t	reserved_3           : 2;
7746 		mmr_t	credit_vc0_dyn       : 6;
7747 		mmr_t	reserved_2           : 8;
7748 		mmr_t	debit_vc2_force_cred : 1;
7749 		mmr_t	reserved_1           : 1;
7750 		mmr_t	debit_vc2_withhold   : 6;
7751 		mmr_t	debit_vc0_force_cred : 1;
7752 		mmr_t	reserved_0           : 1;
7753 		mmr_t	debit_vc0_withhold   : 6;
7764 	mmr_t	sh_xnpi_to_ni1_port_flow_regval;
7766 		mmr_t	debit_vc0_withhold   : 6;
7767 		mmr_t	reserved_0           : 1;
7768 		mmr_t	debit_vc0_force_cred : 1;
7769 		mmr_t	debit_vc2_withhold   : 6;
7770 		mmr_t	reserved_1           : 1;
7771 		mmr_t	debit_vc2_force_cred : 1;
7772 		mmr_t	reserved_2           : 8;
7773 		mmr_t	credit_vc0_dyn       : 6;
7774 		mmr_t	reserved_3           : 2;
7775 		mmr_t	credit_vc0_cap       : 6;
7776 		mmr_t	reserved_4           : 10;
7777 		mmr_t	credit_vc2_dyn       : 6;
7778 		mmr_t	reserved_5           : 2;
7779 		mmr_t	credit_vc2_cap       : 6;
7780 		mmr_t	reserved_6           : 2;
7785 	mmr_t	sh_xnpi_to_ni1_port_flow_regval;
7787 		mmr_t	reserved_6           : 2;
7788 		mmr_t	credit_vc2_cap       : 6;
7789 		mmr_t	reserved_5           : 2;
7790 		mmr_t	credit_vc2_dyn       : 6;
7791 		mmr_t	reserved_4           : 10;
7792 		mmr_t	credit_vc0_cap       : 6;
7793 		mmr_t	reserved_3           : 2;
7794 		mmr_t	credit_vc0_dyn       : 6;
7795 		mmr_t	reserved_2           : 8;
7796 		mmr_t	debit_vc2_force_cred : 1;
7797 		mmr_t	reserved_1           : 1;
7798 		mmr_t	debit_vc2_withhold   : 6;
7799 		mmr_t	debit_vc0_force_cred : 1;
7800 		mmr_t	reserved_0           : 1;
7801 		mmr_t	debit_vc0_withhold   : 6;
7812 	mmr_t	sh_xnpi_to_iilb_port_flow_regval;
7814 		mmr_t	debit_vc0_withhold   : 6;
7815 		mmr_t	reserved_0           : 1;
7816 		mmr_t	debit_vc0_force_cred : 1;
7817 		mmr_t	debit_vc2_withhold   : 6;
7818 		mmr_t	reserved_1           : 1;
7819 		mmr_t	debit_vc2_force_cred : 1;
7820 		mmr_t	reserved_2           : 8;
7821 		mmr_t	credit_vc0_dyn       : 6;
7822 		mmr_t	reserved_3           : 2;
7823 		mmr_t	credit_vc0_cap       : 6;
7824 		mmr_t	reserved_4           : 10;
7825 		mmr_t	credit_vc2_dyn       : 6;
7826 		mmr_t	reserved_5           : 2;
7827 		mmr_t	credit_vc2_cap       : 6;
7828 		mmr_t	reserved_6           : 2;
7833 	mmr_t	sh_xnpi_to_iilb_port_flow_regval;
7835 		mmr_t	reserved_6           : 2;
7836 		mmr_t	credit_vc2_cap       : 6;
7837 		mmr_t	reserved_5           : 2;
7838 		mmr_t	credit_vc2_dyn       : 6;
7839 		mmr_t	reserved_4           : 10;
7840 		mmr_t	credit_vc0_cap       : 6;
7841 		mmr_t	reserved_3           : 2;
7842 		mmr_t	credit_vc0_dyn       : 6;
7843 		mmr_t	reserved_2           : 8;
7844 		mmr_t	debit_vc2_force_cred : 1;
7845 		mmr_t	reserved_1           : 1;
7846 		mmr_t	debit_vc2_withhold   : 6;
7847 		mmr_t	debit_vc0_force_cred : 1;
7848 		mmr_t	reserved_0           : 1;
7849 		mmr_t	debit_vc0_withhold   : 6;
7860 	mmr_t	sh_xnpi_fr_ni0_port_flow_fifo_regval;
7862 		mmr_t	entry_vc0_dyn  : 6;
7863 		mmr_t	reserved_0     : 2;
7864 		mmr_t	entry_vc0_cap  : 6;
7865 		mmr_t	reserved_1     : 2;
7866 		mmr_t	entry_vc2_dyn  : 6;
7867 		mmr_t	reserved_2     : 2;
7868 		mmr_t	entry_vc2_cap  : 6;
7869 		mmr_t	reserved_3     : 2;
7870 		mmr_t	entry_vc0_test : 5;
7871 		mmr_t	reserved_4     : 3;
7872 		mmr_t	entry_vc2_test : 5;
7873 		mmr_t	reserved_5     : 19;
7878 	mmr_t	sh_xnpi_fr_ni0_port_flow_fifo_regval;
7880 		mmr_t	reserved_5     : 19;
7881 		mmr_t	entry_vc2_test : 5;
7882 		mmr_t	reserved_4     : 3;
7883 		mmr_t	entry_vc0_test : 5;
7884 		mmr_t	reserved_3     : 2;
7885 		mmr_t	entry_vc2_cap  : 6;
7886 		mmr_t	reserved_2     : 2;
7887 		mmr_t	entry_vc2_dyn  : 6;
7888 		mmr_t	reserved_1     : 2;
7889 		mmr_t	entry_vc0_cap  : 6;
7890 		mmr_t	reserved_0     : 2;
7891 		mmr_t	entry_vc0_dyn  : 6;
7902 	mmr_t	sh_xnpi_fr_ni1_port_flow_fifo_regval;
7904 		mmr_t	entry_vc0_dyn  : 6;
7905 		mmr_t	reserved_0     : 2;
7906 		mmr_t	entry_vc0_cap  : 6;
7907 		mmr_t	reserved_1     : 2;
7908 		mmr_t	entry_vc2_dyn  : 6;
7909 		mmr_t	reserved_2     : 2;
7910 		mmr_t	entry_vc2_cap  : 6;
7911 		mmr_t	reserved_3     : 2;
7912 		mmr_t	entry_vc0_test : 5;
7913 		mmr_t	reserved_4     : 3;
7914 		mmr_t	entry_vc2_test : 5;
7915 		mmr_t	reserved_5     : 19;
7920 	mmr_t	sh_xnpi_fr_ni1_port_flow_fifo_regval;
7922 		mmr_t	reserved_5     : 19;
7923 		mmr_t	entry_vc2_test : 5;
7924 		mmr_t	reserved_4     : 3;
7925 		mmr_t	entry_vc0_test : 5;
7926 		mmr_t	reserved_3     : 2;
7927 		mmr_t	entry_vc2_cap  : 6;
7928 		mmr_t	reserved_2     : 2;
7929 		mmr_t	entry_vc2_dyn  : 6;
7930 		mmr_t	reserved_1     : 2;
7931 		mmr_t	entry_vc0_cap  : 6;
7932 		mmr_t	reserved_0     : 2;
7933 		mmr_t	entry_vc0_dyn  : 6;
7944 	mmr_t	sh_xnpi_fr_iilb_port_flow_fifo_regval;
7946 		mmr_t	entry_vc0_dyn  : 6;
7947 		mmr_t	reserved_0     : 2;
7948 		mmr_t	entry_vc0_cap  : 6;
7949 		mmr_t	reserved_1     : 2;
7950 		mmr_t	entry_vc2_dyn  : 6;
7951 		mmr_t	reserved_2     : 2;
7952 		mmr_t	entry_vc2_cap  : 6;
7953 		mmr_t	reserved_3     : 2;
7954 		mmr_t	entry_vc0_test : 5;
7955 		mmr_t	reserved_4     : 3;
7956 		mmr_t	entry_vc2_test : 5;
7957 		mmr_t	reserved_5     : 19;
7962 	mmr_t	sh_xnpi_fr_iilb_port_flow_fifo_regval;
7964 		mmr_t	reserved_5     : 19;
7965 		mmr_t	entry_vc2_test : 5;
7966 		mmr_t	reserved_4     : 3;
7967 		mmr_t	entry_vc0_test : 5;
7968 		mmr_t	reserved_3     : 2;
7969 		mmr_t	entry_vc2_cap  : 6;
7970 		mmr_t	reserved_2     : 2;
7971 		mmr_t	entry_vc2_dyn  : 6;
7972 		mmr_t	reserved_1     : 2;
7973 		mmr_t	entry_vc0_cap  : 6;
7974 		mmr_t	reserved_0     : 2;
7975 		mmr_t	entry_vc0_dyn  : 6;
7986 	mmr_t	sh_xnmd_sic_flow_regval;
7988 		mmr_t	debit_vc0_withhold   : 5;
7989 		mmr_t	reserved_0           : 2;
7990 		mmr_t	debit_vc0_force_cred : 1;
7991 		mmr_t	debit_vc2_withhold   : 5;
7992 		mmr_t	reserved_1           : 2;
7993 		mmr_t	debit_vc2_force_cred : 1;
7994 		mmr_t	credit_vc0_test      : 5;
7995 		mmr_t	reserved_2           : 3;
7996 		mmr_t	credit_vc0_dyn       : 5;
7997 		mmr_t	reserved_3           : 3;
7998 		mmr_t	credit_vc0_cap       : 5;
7999 		mmr_t	reserved_4           : 3;
8000 		mmr_t	credit_vc2_test      : 5;
8001 		mmr_t	reserved_5           : 3;
8002 		mmr_t	credit_vc2_dyn       : 5;
8003 		mmr_t	reserved_6           : 3;
8004 		mmr_t	credit_vc2_cap       : 5;
8005 		mmr_t	reserved_7           : 2;
8006 		mmr_t	disable_bypass_out   : 1;
8011 	mmr_t	sh_xnmd_sic_flow_regval;
8013 		mmr_t	disable_bypass_out   : 1;
8014 		mmr_t	reserved_7           : 2;
8015 		mmr_t	credit_vc2_cap       : 5;
8016 		mmr_t	reserved_6           : 3;
8017 		mmr_t	credit_vc2_dyn       : 5;
8018 		mmr_t	reserved_5           : 3;
8019 		mmr_t	credit_vc2_test      : 5;
8020 		mmr_t	reserved_4           : 3;
8021 		mmr_t	credit_vc0_cap       : 5;
8022 		mmr_t	reserved_3           : 3;
8023 		mmr_t	credit_vc0_dyn       : 5;
8024 		mmr_t	reserved_2           : 3;
8025 		mmr_t	credit_vc0_test      : 5;
8026 		mmr_t	debit_vc2_force_cred : 1;
8027 		mmr_t	reserved_1           : 2;
8028 		mmr_t	debit_vc2_withhold   : 5;
8029 		mmr_t	debit_vc0_force_cred : 1;
8030 		mmr_t	reserved_0           : 2;
8031 		mmr_t	debit_vc0_withhold   : 5;
8042 	mmr_t	sh_xnmd_to_ni0_port_flow_regval;
8044 		mmr_t	debit_vc0_withhold   : 6;
8045 		mmr_t	reserved_0           : 1;
8046 		mmr_t	debit_vc0_force_cred : 1;
8047 		mmr_t	debit_vc2_withhold   : 6;
8048 		mmr_t	reserved_1           : 1;
8049 		mmr_t	debit_vc2_force_cred : 1;
8050 		mmr_t	reserved_2           : 8;
8051 		mmr_t	credit_vc0_dyn       : 6;
8052 		mmr_t	reserved_3           : 2;
8053 		mmr_t	credit_vc0_cap       : 6;
8054 		mmr_t	reserved_4           : 10;
8055 		mmr_t	credit_vc2_dyn       : 6;
8056 		mmr_t	reserved_5           : 2;
8057 		mmr_t	credit_vc2_cap       : 6;
8058 		mmr_t	reserved_6           : 2;
8063 	mmr_t	sh_xnmd_to_ni0_port_flow_regval;
8065 		mmr_t	reserved_6           : 2;
8066 		mmr_t	credit_vc2_cap       : 6;
8067 		mmr_t	reserved_5           : 2;
8068 		mmr_t	credit_vc2_dyn       : 6;
8069 		mmr_t	reserved_4           : 10;
8070 		mmr_t	credit_vc0_cap       : 6;
8071 		mmr_t	reserved_3           : 2;
8072 		mmr_t	credit_vc0_dyn       : 6;
8073 		mmr_t	reserved_2           : 8;
8074 		mmr_t	debit_vc2_force_cred : 1;
8075 		mmr_t	reserved_1           : 1;
8076 		mmr_t	debit_vc2_withhold   : 6;
8077 		mmr_t	debit_vc0_force_cred : 1;
8078 		mmr_t	reserved_0           : 1;
8079 		mmr_t	debit_vc0_withhold   : 6;
8090 	mmr_t	sh_xnmd_to_ni1_port_flow_regval;
8092 		mmr_t	debit_vc0_withhold   : 6;
8093 		mmr_t	reserved_0           : 1;
8094 		mmr_t	debit_vc0_force_cred : 1;
8095 		mmr_t	debit_vc2_withhold   : 6;
8096 		mmr_t	reserved_1           : 1;
8097 		mmr_t	debit_vc2_force_cred : 1;
8098 		mmr_t	reserved_2           : 8;
8099 		mmr_t	credit_vc0_dyn       : 6;
8100 		mmr_t	reserved_3           : 2;
8101 		mmr_t	credit_vc0_cap       : 6;
8102 		mmr_t	reserved_4           : 10;
8103 		mmr_t	credit_vc2_dyn       : 6;
8104 		mmr_t	reserved_5           : 2;
8105 		mmr_t	credit_vc2_cap       : 6;
8106 		mmr_t	reserved_6           : 2;
8111 	mmr_t	sh_xnmd_to_ni1_port_flow_regval;
8113 		mmr_t	reserved_6           : 2;
8114 		mmr_t	credit_vc2_cap       : 6;
8115 		mmr_t	reserved_5           : 2;
8116 		mmr_t	credit_vc2_dyn       : 6;
8117 		mmr_t	reserved_4           : 10;
8118 		mmr_t	credit_vc0_cap       : 6;
8119 		mmr_t	reserved_3           : 2;
8120 		mmr_t	credit_vc0_dyn       : 6;
8121 		mmr_t	reserved_2           : 8;
8122 		mmr_t	debit_vc2_force_cred : 1;
8123 		mmr_t	reserved_1           : 1;
8124 		mmr_t	debit_vc2_withhold   : 6;
8125 		mmr_t	debit_vc0_force_cred : 1;
8126 		mmr_t	reserved_0           : 1;
8127 		mmr_t	debit_vc0_withhold   : 6;
8138 	mmr_t	sh_xnmd_to_iilb_port_flow_regval;
8140 		mmr_t	debit_vc0_withhold   : 6;
8141 		mmr_t	reserved_0           : 1;
8142 		mmr_t	debit_vc0_force_cred : 1;
8143 		mmr_t	debit_vc2_withhold   : 6;
8144 		mmr_t	reserved_1           : 1;
8145 		mmr_t	debit_vc2_force_cred : 1;
8146 		mmr_t	reserved_2           : 8;
8147 		mmr_t	credit_vc0_dyn       : 6;
8148 		mmr_t	reserved_3           : 2;
8149 		mmr_t	credit_vc0_cap       : 6;
8150 		mmr_t	reserved_4           : 10;
8151 		mmr_t	credit_vc2_dyn       : 6;
8152 		mmr_t	reserved_5           : 2;
8153 		mmr_t	credit_vc2_cap       : 6;
8154 		mmr_t	reserved_6           : 2;
8159 	mmr_t	sh_xnmd_to_iilb_port_flow_regval;
8161 		mmr_t	reserved_6           : 2;
8162 		mmr_t	credit_vc2_cap       : 6;
8163 		mmr_t	reserved_5           : 2;
8164 		mmr_t	credit_vc2_dyn       : 6;
8165 		mmr_t	reserved_4           : 10;
8166 		mmr_t	credit_vc0_cap       : 6;
8167 		mmr_t	reserved_3           : 2;
8168 		mmr_t	credit_vc0_dyn       : 6;
8169 		mmr_t	reserved_2           : 8;
8170 		mmr_t	debit_vc2_force_cred : 1;
8171 		mmr_t	reserved_1           : 1;
8172 		mmr_t	debit_vc2_withhold   : 6;
8173 		mmr_t	debit_vc0_force_cred : 1;
8174 		mmr_t	reserved_0           : 1;
8175 		mmr_t	debit_vc0_withhold   : 6;
8186 	mmr_t	sh_xnmd_fr_ni0_port_flow_fifo_regval;
8188 		mmr_t	entry_vc0_dyn  : 6;
8189 		mmr_t	reserved_0     : 2;
8190 		mmr_t	entry_vc0_cap  : 6;
8191 		mmr_t	reserved_1     : 2;
8192 		mmr_t	entry_vc2_dyn  : 6;
8193 		mmr_t	reserved_2     : 2;
8194 		mmr_t	entry_vc2_cap  : 6;
8195 		mmr_t	reserved_3     : 2;
8196 		mmr_t	entry_vc0_test : 5;
8197 		mmr_t	reserved_4     : 3;
8198 		mmr_t	entry_vc2_test : 5;
8199 		mmr_t	reserved_5     : 19;
8204 	mmr_t	sh_xnmd_fr_ni0_port_flow_fifo_regval;
8206 		mmr_t	reserved_5     : 19;
8207 		mmr_t	entry_vc2_test : 5;
8208 		mmr_t	reserved_4     : 3;
8209 		mmr_t	entry_vc0_test : 5;
8210 		mmr_t	reserved_3     : 2;
8211 		mmr_t	entry_vc2_cap  : 6;
8212 		mmr_t	reserved_2     : 2;
8213 		mmr_t	entry_vc2_dyn  : 6;
8214 		mmr_t	reserved_1     : 2;
8215 		mmr_t	entry_vc0_cap  : 6;
8216 		mmr_t	reserved_0     : 2;
8217 		mmr_t	entry_vc0_dyn  : 6;
8228 	mmr_t	sh_xnmd_fr_ni1_port_flow_fifo_regval;
8230 		mmr_t	entry_vc0_dyn  : 6;
8231 		mmr_t	reserved_0     : 2;
8232 		mmr_t	entry_vc0_cap  : 6;
8233 		mmr_t	reserved_1     : 2;
8234 		mmr_t	entry_vc2_dyn  : 6;
8235 		mmr_t	reserved_2     : 2;
8236 		mmr_t	entry_vc2_cap  : 6;
8237 		mmr_t	reserved_3     : 2;
8238 		mmr_t	entry_vc0_test : 5;
8239 		mmr_t	reserved_4     : 3;
8240 		mmr_t	entry_vc2_test : 5;
8241 		mmr_t	reserved_5     : 19;
8246 	mmr_t	sh_xnmd_fr_ni1_port_flow_fifo_regval;
8248 		mmr_t	reserved_5     : 19;
8249 		mmr_t	entry_vc2_test : 5;
8250 		mmr_t	reserved_4     : 3;
8251 		mmr_t	entry_vc0_test : 5;
8252 		mmr_t	reserved_3     : 2;
8253 		mmr_t	entry_vc2_cap  : 6;
8254 		mmr_t	reserved_2     : 2;
8255 		mmr_t	entry_vc2_dyn  : 6;
8256 		mmr_t	reserved_1     : 2;
8257 		mmr_t	entry_vc0_cap  : 6;
8258 		mmr_t	reserved_0     : 2;
8259 		mmr_t	entry_vc0_dyn  : 6;
8270 	mmr_t	sh_xnmd_fr_iilb_port_flow_fifo_regval;
8272 		mmr_t	entry_vc0_dyn  : 6;
8273 		mmr_t	reserved_0     : 2;
8274 		mmr_t	entry_vc0_cap  : 6;
8275 		mmr_t	reserved_1     : 2;
8276 		mmr_t	entry_vc2_dyn  : 6;
8277 		mmr_t	reserved_2     : 2;
8278 		mmr_t	entry_vc2_cap  : 6;
8279 		mmr_t	reserved_3     : 2;
8280 		mmr_t	entry_vc0_test : 5;
8281 		mmr_t	reserved_4     : 3;
8282 		mmr_t	entry_vc2_test : 5;
8283 		mmr_t	reserved_5     : 19;
8288 	mmr_t	sh_xnmd_fr_iilb_port_flow_fifo_regval;
8290 		mmr_t	reserved_5     : 19;
8291 		mmr_t	entry_vc2_test : 5;
8292 		mmr_t	reserved_4     : 3;
8293 		mmr_t	entry_vc0_test : 5;
8294 		mmr_t	reserved_3     : 2;
8295 		mmr_t	entry_vc2_cap  : 6;
8296 		mmr_t	reserved_2     : 2;
8297 		mmr_t	entry_vc2_dyn  : 6;
8298 		mmr_t	reserved_1     : 2;
8299 		mmr_t	entry_vc0_cap  : 6;
8300 		mmr_t	reserved_0     : 2;
8301 		mmr_t	entry_vc0_dyn  : 6;
8312 	mmr_t	sh_xnii_intra_flow_regval;
8314 		mmr_t	debit_vc0_withhold   : 6;
8315 		mmr_t	reserved_0           : 1;
8316 		mmr_t	debit_vc0_force_cred : 1;
8317 		mmr_t	debit_vc2_withhold   : 6;
8318 		mmr_t	reserved_1           : 1;
8319 		mmr_t	debit_vc2_force_cred : 1;
8320 		mmr_t	credit_vc0_test      : 7;
8321 		mmr_t	reserved_2           : 1;
8322 		mmr_t	credit_vc0_dyn       : 7;
8323 		mmr_t	reserved_3           : 1;
8324 		mmr_t	credit_vc0_cap       : 7;
8325 		mmr_t	reserved_4           : 1;
8326 		mmr_t	credit_vc2_test      : 7;
8327 		mmr_t	reserved_5           : 1;
8328 		mmr_t	credit_vc2_dyn       : 7;
8329 		mmr_t	reserved_6           : 1;
8330 		mmr_t	credit_vc2_cap       : 7;
8331 		mmr_t	reserved_7           : 1;
8336 	mmr_t	sh_xnii_intra_flow_regval;
8338 		mmr_t	reserved_7           : 1;
8339 		mmr_t	credit_vc2_cap       : 7;
8340 		mmr_t	reserved_6           : 1;
8341 		mmr_t	credit_vc2_dyn       : 7;
8342 		mmr_t	reserved_5           : 1;
8343 		mmr_t	credit_vc2_test      : 7;
8344 		mmr_t	reserved_4           : 1;
8345 		mmr_t	credit_vc0_cap       : 7;
8346 		mmr_t	reserved_3           : 1;
8347 		mmr_t	credit_vc0_dyn       : 7;
8348 		mmr_t	reserved_2           : 1;
8349 		mmr_t	credit_vc0_test      : 7;
8350 		mmr_t	debit_vc2_force_cred : 1;
8351 		mmr_t	reserved_1           : 1;
8352 		mmr_t	debit_vc2_withhold   : 6;
8353 		mmr_t	debit_vc0_force_cred : 1;
8354 		mmr_t	reserved_0           : 1;
8355 		mmr_t	debit_vc0_withhold   : 6;
8366 	mmr_t	sh_xnlb_intra_flow_regval;
8368 		mmr_t	debit_vc0_withhold   : 6;
8369 		mmr_t	reserved_0           : 1;
8370 		mmr_t	debit_vc0_force_cred : 1;
8371 		mmr_t	debit_vc2_withhold   : 6;
8372 		mmr_t	reserved_1           : 1;
8373 		mmr_t	debit_vc2_force_cred : 1;
8374 		mmr_t	credit_vc0_test      : 7;
8375 		mmr_t	reserved_2           : 1;
8376 		mmr_t	credit_vc0_dyn       : 7;
8377 		mmr_t	reserved_3           : 1;
8378 		mmr_t	credit_vc0_cap       : 7;
8379 		mmr_t	reserved_4           : 1;
8380 		mmr_t	credit_vc2_test      : 7;
8381 		mmr_t	reserved_5           : 1;
8382 		mmr_t	credit_vc2_dyn       : 7;
8383 		mmr_t	reserved_6           : 1;
8384 		mmr_t	credit_vc2_cap       : 7;
8385 		mmr_t	disable_bypass_in    : 1;
8390 	mmr_t	sh_xnlb_intra_flow_regval;
8392 		mmr_t	disable_bypass_in    : 1;
8393 		mmr_t	credit_vc2_cap       : 7;
8394 		mmr_t	reserved_6           : 1;
8395 		mmr_t	credit_vc2_dyn       : 7;
8396 		mmr_t	reserved_5           : 1;
8397 		mmr_t	credit_vc2_test      : 7;
8398 		mmr_t	reserved_4           : 1;
8399 		mmr_t	credit_vc0_cap       : 7;
8400 		mmr_t	reserved_3           : 1;
8401 		mmr_t	credit_vc0_dyn       : 7;
8402 		mmr_t	reserved_2           : 1;
8403 		mmr_t	credit_vc0_test      : 7;
8404 		mmr_t	debit_vc2_force_cred : 1;
8405 		mmr_t	reserved_1           : 1;
8406 		mmr_t	debit_vc2_withhold   : 6;
8407 		mmr_t	debit_vc0_force_cred : 1;
8408 		mmr_t	reserved_0           : 1;
8409 		mmr_t	debit_vc0_withhold   : 6;
8420 	mmr_t	sh_xniilb_to_ni0_intra_flow_debit_regval;
8422 		mmr_t	vc0_withhold   : 6;
8423 		mmr_t	reserved_0     : 1;
8424 		mmr_t	vc0_force_cred : 1;
8425 		mmr_t	vc2_withhold   : 6;
8426 		mmr_t	reserved_1     : 1;
8427 		mmr_t	vc2_force_cred : 1;
8428 		mmr_t	reserved_2     : 8;
8429 		mmr_t	vc0_dyn        : 7;
8430 		mmr_t	reserved_3     : 1;
8431 		mmr_t	vc0_cap        : 7;
8432 		mmr_t	reserved_4     : 9;
8433 		mmr_t	vc2_dyn        : 7;
8434 		mmr_t	reserved_5     : 1;
8435 		mmr_t	vc2_cap        : 7;
8436 		mmr_t	reserved_6     : 1;
8441 	mmr_t	sh_xniilb_to_ni0_intra_flow_debit_regval;
8443 		mmr_t	reserved_6     : 1;
8444 		mmr_t	vc2_cap        : 7;
8445 		mmr_t	reserved_5     : 1;
8446 		mmr_t	vc2_dyn        : 7;
8447 		mmr_t	reserved_4     : 9;
8448 		mmr_t	vc0_cap        : 7;
8449 		mmr_t	reserved_3     : 1;
8450 		mmr_t	vc0_dyn        : 7;
8451 		mmr_t	reserved_2     : 8;
8452 		mmr_t	vc2_force_cred : 1;
8453 		mmr_t	reserved_1     : 1;
8454 		mmr_t	vc2_withhold   : 6;
8455 		mmr_t	vc0_force_cred : 1;
8456 		mmr_t	reserved_0     : 1;
8457 		mmr_t	vc0_withhold   : 6;
8468 	mmr_t	sh_xniilb_to_ni1_intra_flow_debit_regval;
8470 		mmr_t	vc0_withhold   : 6;
8471 		mmr_t	reserved_0     : 1;
8472 		mmr_t	vc0_force_cred : 1;
8473 		mmr_t	vc2_withhold   : 6;
8474 		mmr_t	reserved_1     : 1;
8475 		mmr_t	vc2_force_cred : 1;
8476 		mmr_t	reserved_2     : 8;
8477 		mmr_t	vc0_dyn        : 7;
8478 		mmr_t	reserved_3     : 1;
8479 		mmr_t	vc0_cap        : 7;
8480 		mmr_t	reserved_4     : 9;
8481 		mmr_t	vc2_dyn        : 7;
8482 		mmr_t	reserved_5     : 1;
8483 		mmr_t	vc2_cap        : 7;
8484 		mmr_t	reserved_6     : 1;
8489 	mmr_t	sh_xniilb_to_ni1_intra_flow_debit_regval;
8491 		mmr_t	reserved_6     : 1;
8492 		mmr_t	vc2_cap        : 7;
8493 		mmr_t	reserved_5     : 1;
8494 		mmr_t	vc2_dyn        : 7;
8495 		mmr_t	reserved_4     : 9;
8496 		mmr_t	vc0_cap        : 7;
8497 		mmr_t	reserved_3     : 1;
8498 		mmr_t	vc0_dyn        : 7;
8499 		mmr_t	reserved_2     : 8;
8500 		mmr_t	vc2_force_cred : 1;
8501 		mmr_t	reserved_1     : 1;
8502 		mmr_t	vc2_withhold   : 6;
8503 		mmr_t	vc0_force_cred : 1;
8504 		mmr_t	reserved_0     : 1;
8505 		mmr_t	vc0_withhold   : 6;
8516 	mmr_t	sh_xniilb_to_md_intra_flow_debit_regval;
8518 		mmr_t	vc0_withhold   : 6;
8519 		mmr_t	reserved_0     : 1;
8520 		mmr_t	vc0_force_cred : 1;
8521 		mmr_t	vc2_withhold   : 6;
8522 		mmr_t	reserved_1     : 1;
8523 		mmr_t	vc2_force_cred : 1;
8524 		mmr_t	reserved_2     : 8;
8525 		mmr_t	vc0_dyn        : 7;
8526 		mmr_t	reserved_3     : 1;
8527 		mmr_t	vc0_cap        : 7;
8528 		mmr_t	reserved_4     : 9;
8529 		mmr_t	vc2_dyn        : 7;
8530 		mmr_t	reserved_5     : 1;
8531 		mmr_t	vc2_cap        : 7;
8532 		mmr_t	reserved_6     : 1;
8537 	mmr_t	sh_xniilb_to_md_intra_flow_debit_regval;
8539 		mmr_t	reserved_6     : 1;
8540 		mmr_t	vc2_cap        : 7;
8541 		mmr_t	reserved_5     : 1;
8542 		mmr_t	vc2_dyn        : 7;
8543 		mmr_t	reserved_4     : 9;
8544 		mmr_t	vc0_cap        : 7;
8545 		mmr_t	reserved_3     : 1;
8546 		mmr_t	vc0_dyn        : 7;
8547 		mmr_t	reserved_2     : 8;
8548 		mmr_t	vc2_force_cred : 1;
8549 		mmr_t	reserved_1     : 1;
8550 		mmr_t	vc2_withhold   : 6;
8551 		mmr_t	vc0_force_cred : 1;
8552 		mmr_t	reserved_0     : 1;
8553 		mmr_t	vc0_withhold   : 6;
8564 	mmr_t	sh_xniilb_to_iilb_intra_flow_debit_regval;
8566 		mmr_t	vc0_withhold   : 6;
8567 		mmr_t	reserved_0     : 1;
8568 		mmr_t	vc0_force_cred : 1;
8569 		mmr_t	vc2_withhold   : 6;
8570 		mmr_t	reserved_1     : 1;
8571 		mmr_t	vc2_force_cred : 1;
8572 		mmr_t	reserved_2     : 8;
8573 		mmr_t	vc0_dyn        : 7;
8574 		mmr_t	reserved_3     : 1;
8575 		mmr_t	vc0_cap        : 7;
8576 		mmr_t	reserved_4     : 9;
8577 		mmr_t	vc2_dyn        : 7;
8578 		mmr_t	reserved_5     : 1;
8579 		mmr_t	vc2_cap        : 7;
8580 		mmr_t	reserved_6     : 1;
8585 	mmr_t	sh_xniilb_to_iilb_intra_flow_debit_regval;
8587 		mmr_t	reserved_6     : 1;
8588 		mmr_t	vc2_cap        : 7;
8589 		mmr_t	reserved_5     : 1;
8590 		mmr_t	vc2_dyn        : 7;
8591 		mmr_t	reserved_4     : 9;
8592 		mmr_t	vc0_cap        : 7;
8593 		mmr_t	reserved_3     : 1;
8594 		mmr_t	vc0_dyn        : 7;
8595 		mmr_t	reserved_2     : 8;
8596 		mmr_t	vc2_force_cred : 1;
8597 		mmr_t	reserved_1     : 1;
8598 		mmr_t	vc2_withhold   : 6;
8599 		mmr_t	vc0_force_cred : 1;
8600 		mmr_t	reserved_0     : 1;
8601 		mmr_t	vc0_withhold   : 6;
8612 	mmr_t	sh_xniilb_to_pi_intra_flow_debit_regval;
8614 		mmr_t	vc0_withhold   : 6;
8615 		mmr_t	reserved_0     : 1;
8616 		mmr_t	vc0_force_cred : 1;
8617 		mmr_t	vc2_withhold   : 6;
8618 		mmr_t	reserved_1     : 1;
8619 		mmr_t	vc2_force_cred : 1;
8620 		mmr_t	reserved_2     : 8;
8621 		mmr_t	vc0_dyn        : 7;
8622 		mmr_t	reserved_3     : 1;
8623 		mmr_t	vc0_cap        : 7;
8624 		mmr_t	reserved_4     : 9;
8625 		mmr_t	vc2_dyn        : 7;
8626 		mmr_t	reserved_5     : 1;
8627 		mmr_t	vc2_cap        : 7;
8628 		mmr_t	reserved_6     : 1;
8633 	mmr_t	sh_xniilb_to_pi_intra_flow_debit_regval;
8635 		mmr_t	reserved_6     : 1;
8636 		mmr_t	vc2_cap        : 7;
8637 		mmr_t	reserved_5     : 1;
8638 		mmr_t	vc2_dyn        : 7;
8639 		mmr_t	reserved_4     : 9;
8640 		mmr_t	vc0_cap        : 7;
8641 		mmr_t	reserved_3     : 1;
8642 		mmr_t	vc0_dyn        : 7;
8643 		mmr_t	reserved_2     : 8;
8644 		mmr_t	vc2_force_cred : 1;
8645 		mmr_t	reserved_1     : 1;
8646 		mmr_t	vc2_withhold   : 6;
8647 		mmr_t	vc0_force_cred : 1;
8648 		mmr_t	reserved_0     : 1;
8649 		mmr_t	vc0_withhold   : 6;
8660 	mmr_t	sh_xniilb_fr_ni0_intra_flow_credit_regval;
8662 		mmr_t	vc0_test    : 7;
8663 		mmr_t	reserved_0  : 1;
8664 		mmr_t	vc0_dyn     : 7;
8665 		mmr_t	reserved_1  : 1;
8666 		mmr_t	vc0_cap     : 7;
8667 		mmr_t	reserved_2  : 1;
8668 		mmr_t	vc2_test    : 7;
8669 		mmr_t	reserved_3  : 1;
8670 		mmr_t	vc2_dyn     : 7;
8671 		mmr_t	reserved_4  : 1;
8672 		mmr_t	vc2_cap     : 7;
8673 		mmr_t	reserved_5  : 17;
8678 	mmr_t	sh_xniilb_fr_ni0_intra_flow_credit_regval;
8680 		mmr_t	reserved_5  : 17;
8681 		mmr_t	vc2_cap     : 7;
8682 		mmr_t	reserved_4  : 1;
8683 		mmr_t	vc2_dyn     : 7;
8684 		mmr_t	reserved_3  : 1;
8685 		mmr_t	vc2_test    : 7;
8686 		mmr_t	reserved_2  : 1;
8687 		mmr_t	vc0_cap     : 7;
8688 		mmr_t	reserved_1  : 1;
8689 		mmr_t	vc0_dyn     : 7;
8690 		mmr_t	reserved_0  : 1;
8691 		mmr_t	vc0_test    : 7;
8702 	mmr_t	sh_xniilb_fr_ni1_intra_flow_credit_regval;
8704 		mmr_t	vc0_test    : 7;
8705 		mmr_t	reserved_0  : 1;
8706 		mmr_t	vc0_dyn     : 7;
8707 		mmr_t	reserved_1  : 1;
8708 		mmr_t	vc0_cap     : 7;
8709 		mmr_t	reserved_2  : 1;
8710 		mmr_t	vc2_test    : 7;
8711 		mmr_t	reserved_3  : 1;
8712 		mmr_t	vc2_dyn     : 7;
8713 		mmr_t	reserved_4  : 1;
8714 		mmr_t	vc2_cap     : 7;
8715 		mmr_t	reserved_5  : 17;
8720 	mmr_t	sh_xniilb_fr_ni1_intra_flow_credit_regval;
8722 		mmr_t	reserved_5  : 17;
8723 		mmr_t	vc2_cap     : 7;
8724 		mmr_t	reserved_4  : 1;
8725 		mmr_t	vc2_dyn     : 7;
8726 		mmr_t	reserved_3  : 1;
8727 		mmr_t	vc2_test    : 7;
8728 		mmr_t	reserved_2  : 1;
8729 		mmr_t	vc0_cap     : 7;
8730 		mmr_t	reserved_1  : 1;
8731 		mmr_t	vc0_dyn     : 7;
8732 		mmr_t	reserved_0  : 1;
8733 		mmr_t	vc0_test    : 7;
8744 	mmr_t	sh_xniilb_fr_md_intra_flow_credit_regval;
8746 		mmr_t	vc0_test    : 7;
8747 		mmr_t	reserved_0  : 1;
8748 		mmr_t	vc0_dyn     : 7;
8749 		mmr_t	reserved_1  : 1;
8750 		mmr_t	vc0_cap     : 7;
8751 		mmr_t	reserved_2  : 1;
8752 		mmr_t	vc2_test    : 7;
8753 		mmr_t	reserved_3  : 1;
8754 		mmr_t	vc2_dyn     : 7;
8755 		mmr_t	reserved_4  : 1;
8756 		mmr_t	vc2_cap     : 7;
8757 		mmr_t	reserved_5  : 17;
8762 	mmr_t	sh_xniilb_fr_md_intra_flow_credit_regval;
8764 		mmr_t	reserved_5  : 17;
8765 		mmr_t	vc2_cap     : 7;
8766 		mmr_t	reserved_4  : 1;
8767 		mmr_t	vc2_dyn     : 7;
8768 		mmr_t	reserved_3  : 1;
8769 		mmr_t	vc2_test    : 7;
8770 		mmr_t	reserved_2  : 1;
8771 		mmr_t	vc0_cap     : 7;
8772 		mmr_t	reserved_1  : 1;
8773 		mmr_t	vc0_dyn     : 7;
8774 		mmr_t	reserved_0  : 1;
8775 		mmr_t	vc0_test    : 7;
8786 	mmr_t	sh_xniilb_fr_iilb_intra_flow_credit_regval;
8788 		mmr_t	vc0_test    : 7;
8789 		mmr_t	reserved_0  : 1;
8790 		mmr_t	vc0_dyn     : 7;
8791 		mmr_t	reserved_1  : 1;
8792 		mmr_t	vc0_cap     : 7;
8793 		mmr_t	reserved_2  : 1;
8794 		mmr_t	vc2_test    : 7;
8795 		mmr_t	reserved_3  : 1;
8796 		mmr_t	vc2_dyn     : 7;
8797 		mmr_t	reserved_4  : 1;
8798 		mmr_t	vc2_cap     : 7;
8799 		mmr_t	reserved_5  : 17;
8804 	mmr_t	sh_xniilb_fr_iilb_intra_flow_credit_regval;
8806 		mmr_t	reserved_5  : 17;
8807 		mmr_t	vc2_cap     : 7;
8808 		mmr_t	reserved_4  : 1;
8809 		mmr_t	vc2_dyn     : 7;
8810 		mmr_t	reserved_3  : 1;
8811 		mmr_t	vc2_test    : 7;
8812 		mmr_t	reserved_2  : 1;
8813 		mmr_t	vc0_cap     : 7;
8814 		mmr_t	reserved_1  : 1;
8815 		mmr_t	vc0_dyn     : 7;
8816 		mmr_t	reserved_0  : 1;
8817 		mmr_t	vc0_test    : 7;
8828 	mmr_t	sh_xniilb_fr_pi_intra_flow_credit_regval;
8830 		mmr_t	vc0_test    : 7;
8831 		mmr_t	reserved_0  : 1;
8832 		mmr_t	vc0_dyn     : 7;
8833 		mmr_t	reserved_1  : 1;
8834 		mmr_t	vc0_cap     : 7;
8835 		mmr_t	reserved_2  : 1;
8836 		mmr_t	vc2_test    : 7;
8837 		mmr_t	reserved_3  : 1;
8838 		mmr_t	vc2_dyn     : 7;
8839 		mmr_t	reserved_4  : 1;
8840 		mmr_t	vc2_cap     : 7;
8841 		mmr_t	reserved_5  : 17;
8846 	mmr_t	sh_xniilb_fr_pi_intra_flow_credit_regval;
8848 		mmr_t	reserved_5  : 17;
8849 		mmr_t	vc2_cap     : 7;
8850 		mmr_t	reserved_4  : 1;
8851 		mmr_t	vc2_dyn     : 7;
8852 		mmr_t	reserved_3  : 1;
8853 		mmr_t	vc2_test    : 7;
8854 		mmr_t	reserved_2  : 1;
8855 		mmr_t	vc0_cap     : 7;
8856 		mmr_t	reserved_1  : 1;
8857 		mmr_t	vc0_dyn     : 7;
8858 		mmr_t	reserved_0  : 1;
8859 		mmr_t	vc0_test    : 7;
8870 	mmr_t	sh_xnni0_to_pi_intra_flow_debit_regval;
8872 		mmr_t	vc0_withhold   : 6;
8873 		mmr_t	reserved_0     : 1;
8874 		mmr_t	vc0_force_cred : 1;
8875 		mmr_t	vc2_withhold   : 6;
8876 		mmr_t	reserved_1     : 1;
8877 		mmr_t	vc2_force_cred : 1;
8878 		mmr_t	reserved_2     : 8;
8879 		mmr_t	vc0_dyn        : 7;
8880 		mmr_t	reserved_3     : 1;
8881 		mmr_t	vc0_cap        : 7;
8882 		mmr_t	reserved_4     : 9;
8883 		mmr_t	vc2_dyn        : 7;
8884 		mmr_t	reserved_5     : 1;
8885 		mmr_t	vc2_cap        : 7;
8886 		mmr_t	reserved_6     : 1;
8891 	mmr_t	sh_xnni0_to_pi_intra_flow_debit_regval;
8893 		mmr_t	reserved_6     : 1;
8894 		mmr_t	vc2_cap        : 7;
8895 		mmr_t	reserved_5     : 1;
8896 		mmr_t	vc2_dyn        : 7;
8897 		mmr_t	reserved_4     : 9;
8898 		mmr_t	vc0_cap        : 7;
8899 		mmr_t	reserved_3     : 1;
8900 		mmr_t	vc0_dyn        : 7;
8901 		mmr_t	reserved_2     : 8;
8902 		mmr_t	vc2_force_cred : 1;
8903 		mmr_t	reserved_1     : 1;
8904 		mmr_t	vc2_withhold   : 6;
8905 		mmr_t	vc0_force_cred : 1;
8906 		mmr_t	reserved_0     : 1;
8907 		mmr_t	vc0_withhold   : 6;
8918 	mmr_t	sh_xnni0_to_md_intra_flow_debit_regval;
8920 		mmr_t	vc0_withhold   : 6;
8921 		mmr_t	reserved_0     : 1;
8922 		mmr_t	vc0_force_cred : 1;
8923 		mmr_t	vc2_withhold   : 6;
8924 		mmr_t	reserved_1     : 1;
8925 		mmr_t	vc2_force_cred : 1;
8926 		mmr_t	reserved_2     : 8;
8927 		mmr_t	vc0_dyn        : 7;
8928 		mmr_t	reserved_3     : 1;
8929 		mmr_t	vc0_cap        : 7;
8930 		mmr_t	reserved_4     : 9;
8931 		mmr_t	vc2_dyn        : 7;
8932 		mmr_t	reserved_5     : 1;
8933 		mmr_t	vc2_cap        : 7;
8934 		mmr_t	reserved_6     : 1;
8939 	mmr_t	sh_xnni0_to_md_intra_flow_debit_regval;
8941 		mmr_t	reserved_6     : 1;
8942 		mmr_t	vc2_cap        : 7;
8943 		mmr_t	reserved_5     : 1;
8944 		mmr_t	vc2_dyn        : 7;
8945 		mmr_t	reserved_4     : 9;
8946 		mmr_t	vc0_cap        : 7;
8947 		mmr_t	reserved_3     : 1;
8948 		mmr_t	vc0_dyn        : 7;
8949 		mmr_t	reserved_2     : 8;
8950 		mmr_t	vc2_force_cred : 1;
8951 		mmr_t	reserved_1     : 1;
8952 		mmr_t	vc2_withhold   : 6;
8953 		mmr_t	vc0_force_cred : 1;
8954 		mmr_t	reserved_0     : 1;
8955 		mmr_t	vc0_withhold   : 6;
8966 	mmr_t	sh_xnni0_to_iilb_intra_flow_debit_regval;
8968 		mmr_t	vc0_withhold   : 6;
8969 		mmr_t	reserved_0     : 1;
8970 		mmr_t	vc0_force_cred : 1;
8971 		mmr_t	vc2_withhold   : 6;
8972 		mmr_t	reserved_1     : 1;
8973 		mmr_t	vc2_force_cred : 1;
8974 		mmr_t	reserved_2     : 8;
8975 		mmr_t	vc0_dyn        : 7;
8976 		mmr_t	reserved_3     : 1;
8977 		mmr_t	vc0_cap        : 7;
8978 		mmr_t	reserved_4     : 9;
8979 		mmr_t	vc2_dyn        : 7;
8980 		mmr_t	reserved_5     : 1;
8981 		mmr_t	vc2_cap        : 7;
8982 		mmr_t	reserved_6     : 1;
8987 	mmr_t	sh_xnni0_to_iilb_intra_flow_debit_regval;
8989 		mmr_t	reserved_6     : 1;
8990 		mmr_t	vc2_cap        : 7;
8991 		mmr_t	reserved_5     : 1;
8992 		mmr_t	vc2_dyn        : 7;
8993 		mmr_t	reserved_4     : 9;
8994 		mmr_t	vc0_cap        : 7;
8995 		mmr_t	reserved_3     : 1;
8996 		mmr_t	vc0_dyn        : 7;
8997 		mmr_t	reserved_2     : 8;
8998 		mmr_t	vc2_force_cred : 1;
8999 		mmr_t	reserved_1     : 1;
9000 		mmr_t	vc2_withhold   : 6;
9001 		mmr_t	vc0_force_cred : 1;
9002 		mmr_t	reserved_0     : 1;
9003 		mmr_t	vc0_withhold   : 6;
9014 	mmr_t	sh_xnni0_fr_pi_intra_flow_credit_regval;
9016 		mmr_t	vc0_test    : 7;
9017 		mmr_t	reserved_0  : 1;
9018 		mmr_t	vc0_dyn     : 7;
9019 		mmr_t	reserved_1  : 1;
9020 		mmr_t	vc0_cap     : 7;
9021 		mmr_t	reserved_2  : 1;
9022 		mmr_t	vc2_test    : 7;
9023 		mmr_t	reserved_3  : 1;
9024 		mmr_t	vc2_dyn     : 7;
9025 		mmr_t	reserved_4  : 1;
9026 		mmr_t	vc2_cap     : 7;
9027 		mmr_t	reserved_5  : 17;
9032 	mmr_t	sh_xnni0_fr_pi_intra_flow_credit_regval;
9034 		mmr_t	reserved_5  : 17;
9035 		mmr_t	vc2_cap     : 7;
9036 		mmr_t	reserved_4  : 1;
9037 		mmr_t	vc2_dyn     : 7;
9038 		mmr_t	reserved_3  : 1;
9039 		mmr_t	vc2_test    : 7;
9040 		mmr_t	reserved_2  : 1;
9041 		mmr_t	vc0_cap     : 7;
9042 		mmr_t	reserved_1  : 1;
9043 		mmr_t	vc0_dyn     : 7;
9044 		mmr_t	reserved_0  : 1;
9045 		mmr_t	vc0_test    : 7;
9056 	mmr_t	sh_xnni0_fr_md_intra_flow_credit_regval;
9058 		mmr_t	vc0_test    : 7;
9059 		mmr_t	reserved_0  : 1;
9060 		mmr_t	vc0_dyn     : 7;
9061 		mmr_t	reserved_1  : 1;
9062 		mmr_t	vc0_cap     : 7;
9063 		mmr_t	reserved_2  : 1;
9064 		mmr_t	vc2_test    : 7;
9065 		mmr_t	reserved_3  : 1;
9066 		mmr_t	vc2_dyn     : 7;
9067 		mmr_t	reserved_4  : 1;
9068 		mmr_t	vc2_cap     : 7;
9069 		mmr_t	reserved_5  : 17;
9074 	mmr_t	sh_xnni0_fr_md_intra_flow_credit_regval;
9076 		mmr_t	reserved_5  : 17;
9077 		mmr_t	vc2_cap     : 7;
9078 		mmr_t	reserved_4  : 1;
9079 		mmr_t	vc2_dyn     : 7;
9080 		mmr_t	reserved_3  : 1;
9081 		mmr_t	vc2_test    : 7;
9082 		mmr_t	reserved_2  : 1;
9083 		mmr_t	vc0_cap     : 7;
9084 		mmr_t	reserved_1  : 1;
9085 		mmr_t	vc0_dyn     : 7;
9086 		mmr_t	reserved_0  : 1;
9087 		mmr_t	vc0_test    : 7;
9098 	mmr_t	sh_xnni0_fr_iilb_intra_flow_credit_regval;
9100 		mmr_t	vc0_test    : 7;
9101 		mmr_t	reserved_0  : 1;
9102 		mmr_t	vc0_dyn     : 7;
9103 		mmr_t	reserved_1  : 1;
9104 		mmr_t	vc0_cap     : 7;
9105 		mmr_t	reserved_2  : 1;
9106 		mmr_t	vc2_test    : 7;
9107 		mmr_t	reserved_3  : 1;
9108 		mmr_t	vc2_dyn     : 7;
9109 		mmr_t	reserved_4  : 1;
9110 		mmr_t	vc2_cap     : 7;
9111 		mmr_t	reserved_5  : 17;
9116 	mmr_t	sh_xnni0_fr_iilb_intra_flow_credit_regval;
9118 		mmr_t	reserved_5  : 17;
9119 		mmr_t	vc2_cap     : 7;
9120 		mmr_t	reserved_4  : 1;
9121 		mmr_t	vc2_dyn     : 7;
9122 		mmr_t	reserved_3  : 1;
9123 		mmr_t	vc2_test    : 7;
9124 		mmr_t	reserved_2  : 1;
9125 		mmr_t	vc0_cap     : 7;
9126 		mmr_t	reserved_1  : 1;
9127 		mmr_t	vc0_dyn     : 7;
9128 		mmr_t	reserved_0  : 1;
9129 		mmr_t	vc0_test    : 7;
9140 	mmr_t	sh_xnni0_0_intrani_flow_regval;
9142 		mmr_t	debit_vc0_withhold   : 6;
9143 		mmr_t	reserved_0           : 1;
9144 		mmr_t	debit_vc0_force_cred : 1;
9145 		mmr_t	reserved_1           : 56;
9150 	mmr_t	sh_xnni0_0_intrani_flow_regval;
9152 		mmr_t	reserved_1           : 56;
9153 		mmr_t	debit_vc0_force_cred : 1;
9154 		mmr_t	reserved_0           : 1;
9155 		mmr_t	debit_vc0_withhold   : 6;
9166 	mmr_t	sh_xnni0_1_intrani_flow_regval;
9168 		mmr_t	debit_vc1_withhold   : 6;
9169 		mmr_t	reserved_0           : 1;
9170 		mmr_t	debit_vc1_force_cred : 1;
9171 		mmr_t	reserved_1           : 56;
9176 	mmr_t	sh_xnni0_1_intrani_flow_regval;
9178 		mmr_t	reserved_1           : 56;
9179 		mmr_t	debit_vc1_force_cred : 1;
9180 		mmr_t	reserved_0           : 1;
9181 		mmr_t	debit_vc1_withhold   : 6;
9192 	mmr_t	sh_xnni0_2_intrani_flow_regval;
9194 		mmr_t	debit_vc2_withhold   : 6;
9195 		mmr_t	reserved_0           : 1;
9196 		mmr_t	debit_vc2_force_cred : 1;
9197 		mmr_t	reserved_1           : 56;
9202 	mmr_t	sh_xnni0_2_intrani_flow_regval;
9204 		mmr_t	reserved_1           : 56;
9205 		mmr_t	debit_vc2_force_cred : 1;
9206 		mmr_t	reserved_0           : 1;
9207 		mmr_t	debit_vc2_withhold   : 6;
9218 	mmr_t	sh_xnni0_3_intrani_flow_regval;
9220 		mmr_t	debit_vc3_withhold   : 6;
9221 		mmr_t	reserved_0           : 1;
9222 		mmr_t	debit_vc3_force_cred : 1;
9223 		mmr_t	reserved_1           : 56;
9228 	mmr_t	sh_xnni0_3_intrani_flow_regval;
9230 		mmr_t	reserved_1           : 56;
9231 		mmr_t	debit_vc3_force_cred : 1;
9232 		mmr_t	reserved_0           : 1;
9233 		mmr_t	debit_vc3_withhold   : 6;
9244 	mmr_t	sh_xnni0_vcswitch_flow_regval;
9246 		mmr_t	ni_vcfifo_dateline_switch : 1;
9247 		mmr_t	reserved_0                : 7;
9248 		mmr_t	pi_vcfifo_switch          : 1;
9249 		mmr_t	reserved_1                : 7;
9250 		mmr_t	md_vcfifo_switch          : 1;
9251 		mmr_t	reserved_2                : 7;
9252 		mmr_t	iilb_vcfifo_switch        : 1;
9253 		mmr_t	reserved_3                : 7;
9254 		mmr_t	disable_sync_bypass_in    : 1;
9255 		mmr_t	disable_sync_bypass_out   : 1;
9256 		mmr_t	async_fifoes              : 1;
9257 		mmr_t	reserved_4                : 29;
9262 	mmr_t	sh_xnni0_vcswitch_flow_regval;
9264 		mmr_t	reserved_4                : 29;
9265 		mmr_t	async_fifoes              : 1;
9266 		mmr_t	disable_sync_bypass_out   : 1;
9267 		mmr_t	disable_sync_bypass_in    : 1;
9268 		mmr_t	reserved_3                : 7;
9269 		mmr_t	iilb_vcfifo_switch        : 1;
9270 		mmr_t	reserved_2                : 7;
9271 		mmr_t	md_vcfifo_switch          : 1;
9272 		mmr_t	reserved_1                : 7;
9273 		mmr_t	pi_vcfifo_switch          : 1;
9274 		mmr_t	reserved_0                : 7;
9275 		mmr_t	ni_vcfifo_dateline_switch : 1;
9286 	mmr_t	sh_xnni0_timer_reg_regval;
9288 		mmr_t	timeout_reg     : 24;
9289 		mmr_t	reserved_0      : 8;
9290 		mmr_t	linkcleanup_reg : 1;
9291 		mmr_t	reserved_1      : 31;
9296 	mmr_t	sh_xnni0_timer_reg_regval;
9298 		mmr_t	reserved_1      : 31;
9299 		mmr_t	linkcleanup_reg : 1;
9300 		mmr_t	reserved_0      : 8;
9301 		mmr_t	timeout_reg     : 24;
9312 	mmr_t	sh_xnni0_fifo02_flow_regval;
9314 		mmr_t	count_vc0_limit : 4;
9315 		mmr_t	reserved_0      : 4;
9316 		mmr_t	count_vc0_dyn   : 4;
9317 		mmr_t	reserved_1      : 4;
9318 		mmr_t	count_vc0_cap   : 4;
9319 		mmr_t	reserved_2      : 4;
9320 		mmr_t	count_vc2_limit : 4;
9321 		mmr_t	reserved_3      : 4;
9322 		mmr_t	count_vc2_dyn   : 4;
9323 		mmr_t	reserved_4      : 4;
9324 		mmr_t	count_vc2_cap   : 4;
9325 		mmr_t	reserved_5      : 20;
9330 	mmr_t	sh_xnni0_fifo02_flow_regval;
9332 		mmr_t	reserved_5      : 20;
9333 		mmr_t	count_vc2_cap   : 4;
9334 		mmr_t	reserved_4      : 4;
9335 		mmr_t	count_vc2_dyn   : 4;
9336 		mmr_t	reserved_3      : 4;
9337 		mmr_t	count_vc2_limit : 4;
9338 		mmr_t	reserved_2      : 4;
9339 		mmr_t	count_vc0_cap   : 4;
9340 		mmr_t	reserved_1      : 4;
9341 		mmr_t	count_vc0_dyn   : 4;
9342 		mmr_t	reserved_0      : 4;
9343 		mmr_t	count_vc0_limit : 4;
9354 	mmr_t	sh_xnni0_fifo13_flow_regval;
9356 		mmr_t	count_vc1_limit : 4;
9357 		mmr_t	reserved_0      : 4;
9358 		mmr_t	count_vc1_dyn   : 4;
9359 		mmr_t	reserved_1      : 4;
9360 		mmr_t	count_vc1_cap   : 4;
9361 		mmr_t	reserved_2      : 4;
9362 		mmr_t	count_vc3_limit : 4;
9363 		mmr_t	reserved_3      : 4;
9364 		mmr_t	count_vc3_dyn   : 4;
9365 		mmr_t	reserved_4      : 4;
9366 		mmr_t	count_vc3_cap   : 4;
9367 		mmr_t	reserved_5      : 20;
9372 	mmr_t	sh_xnni0_fifo13_flow_regval;
9374 		mmr_t	reserved_5      : 20;
9375 		mmr_t	count_vc3_cap   : 4;
9376 		mmr_t	reserved_4      : 4;
9377 		mmr_t	count_vc3_dyn   : 4;
9378 		mmr_t	reserved_3      : 4;
9379 		mmr_t	count_vc3_limit : 4;
9380 		mmr_t	reserved_2      : 4;
9381 		mmr_t	count_vc1_cap   : 4;
9382 		mmr_t	reserved_1      : 4;
9383 		mmr_t	count_vc1_dyn   : 4;
9384 		mmr_t	reserved_0      : 4;
9385 		mmr_t	count_vc1_limit : 4;
9396 	mmr_t	sh_xnni0_ni_flow_regval;
9398 		mmr_t	vc0_limit   : 4;
9399 		mmr_t	reserved_0  : 4;
9400 		mmr_t	vc0_dyn     : 4;
9401 		mmr_t	vc0_cap     : 4;
9402 		mmr_t	vc1_limit   : 4;
9403 		mmr_t	reserved_1  : 4;
9404 		mmr_t	vc1_dyn     : 4;
9405 		mmr_t	vc1_cap     : 4;
9406 		mmr_t	vc2_limit   : 4;
9407 		mmr_t	reserved_2  : 4;
9408 		mmr_t	vc2_dyn     : 4;
9409 		mmr_t	vc2_cap     : 4;
9410 		mmr_t	vc3_limit   : 4;
9411 		mmr_t	reserved_3  : 4;
9412 		mmr_t	vc3_dyn     : 4;
9413 		mmr_t	vc3_cap     : 4;
9418 	mmr_t	sh_xnni0_ni_flow_regval;
9420 		mmr_t	vc3_cap     : 4;
9421 		mmr_t	vc3_dyn     : 4;
9422 		mmr_t	reserved_3  : 4;
9423 		mmr_t	vc3_limit   : 4;
9424 		mmr_t	vc2_cap     : 4;
9425 		mmr_t	vc2_dyn     : 4;
9426 		mmr_t	reserved_2  : 4;
9427 		mmr_t	vc2_limit   : 4;
9428 		mmr_t	vc1_cap     : 4;
9429 		mmr_t	vc1_dyn     : 4;
9430 		mmr_t	reserved_1  : 4;
9431 		mmr_t	vc1_limit   : 4;
9432 		mmr_t	vc0_cap     : 4;
9433 		mmr_t	vc0_dyn     : 4;
9434 		mmr_t	reserved_0  : 4;
9435 		mmr_t	vc0_limit   : 4;
9446 	mmr_t	sh_xnni0_dead_flow_regval;
9448 		mmr_t	vc0_limit   : 4;
9449 		mmr_t	reserved_0  : 4;
9450 		mmr_t	vc0_dyn     : 4;
9451 		mmr_t	vc0_cap     : 4;
9452 		mmr_t	vc1_limit   : 4;
9453 		mmr_t	reserved_1  : 4;
9454 		mmr_t	vc1_dyn     : 4;
9455 		mmr_t	vc1_cap     : 4;
9456 		mmr_t	vc2_limit   : 4;
9457 		mmr_t	reserved_2  : 4;
9458 		mmr_t	vc2_dyn     : 4;
9459 		mmr_t	vc2_cap     : 4;
9460 		mmr_t	vc3_limit   : 4;
9461 		mmr_t	reserved_3  : 4;
9462 		mmr_t	vc3_dyn     : 4;
9463 		mmr_t	vc3_cap     : 4;
9468 	mmr_t	sh_xnni0_dead_flow_regval;
9470 		mmr_t	vc3_cap     : 4;
9471 		mmr_t	vc3_dyn     : 4;
9472 		mmr_t	reserved_3  : 4;
9473 		mmr_t	vc3_limit   : 4;
9474 		mmr_t	vc2_cap     : 4;
9475 		mmr_t	vc2_dyn     : 4;
9476 		mmr_t	reserved_2  : 4;
9477 		mmr_t	vc2_limit   : 4;
9478 		mmr_t	vc1_cap     : 4;
9479 		mmr_t	vc1_dyn     : 4;
9480 		mmr_t	reserved_1  : 4;
9481 		mmr_t	vc1_limit   : 4;
9482 		mmr_t	vc0_cap     : 4;
9483 		mmr_t	vc0_dyn     : 4;
9484 		mmr_t	reserved_0  : 4;
9485 		mmr_t	vc0_limit   : 4;
9496 	mmr_t	sh_xnni0_inject_age_regval;
9498 		mmr_t	request_inject : 8;
9499 		mmr_t	reply_inject   : 8;
9500 		mmr_t	reserved_0     : 48;
9505 	mmr_t	sh_xnni0_inject_age_regval;
9507 		mmr_t	reserved_0     : 48;
9508 		mmr_t	reply_inject   : 8;
9509 		mmr_t	request_inject : 8;
9520 	mmr_t	sh_xnni1_to_pi_intra_flow_debit_regval;
9522 		mmr_t	vc0_withhold   : 6;
9523 		mmr_t	reserved_0     : 1;
9524 		mmr_t	vc0_force_cred : 1;
9525 		mmr_t	vc2_withhold   : 6;
9526 		mmr_t	reserved_1     : 1;
9527 		mmr_t	vc2_force_cred : 1;
9528 		mmr_t	reserved_2     : 8;
9529 		mmr_t	vc0_dyn        : 7;
9530 		mmr_t	reserved_3     : 1;
9531 		mmr_t	vc0_cap        : 7;
9532 		mmr_t	reserved_4     : 9;
9533 		mmr_t	vc2_dyn        : 7;
9534 		mmr_t	reserved_5     : 1;
9535 		mmr_t	vc2_cap        : 7;
9536 		mmr_t	reserved_6     : 1;
9541 	mmr_t	sh_xnni1_to_pi_intra_flow_debit_regval;
9543 		mmr_t	reserved_6     : 1;
9544 		mmr_t	vc2_cap        : 7;
9545 		mmr_t	reserved_5     : 1;
9546 		mmr_t	vc2_dyn        : 7;
9547 		mmr_t	reserved_4     : 9;
9548 		mmr_t	vc0_cap        : 7;
9549 		mmr_t	reserved_3     : 1;
9550 		mmr_t	vc0_dyn        : 7;
9551 		mmr_t	reserved_2     : 8;
9552 		mmr_t	vc2_force_cred : 1;
9553 		mmr_t	reserved_1     : 1;
9554 		mmr_t	vc2_withhold   : 6;
9555 		mmr_t	vc0_force_cred : 1;
9556 		mmr_t	reserved_0     : 1;
9557 		mmr_t	vc0_withhold   : 6;
9568 	mmr_t	sh_xnni1_to_md_intra_flow_debit_regval;
9570 		mmr_t	vc0_withhold   : 6;
9571 		mmr_t	reserved_0     : 1;
9572 		mmr_t	vc0_force_cred : 1;
9573 		mmr_t	vc2_withhold   : 6;
9574 		mmr_t	reserved_1     : 1;
9575 		mmr_t	vc2_force_cred : 1;
9576 		mmr_t	reserved_2     : 8;
9577 		mmr_t	vc0_dyn        : 7;
9578 		mmr_t	reserved_3     : 1;
9579 		mmr_t	vc0_cap        : 7;
9580 		mmr_t	reserved_4     : 9;
9581 		mmr_t	vc2_dyn        : 7;
9582 		mmr_t	reserved_5     : 1;
9583 		mmr_t	vc2_cap        : 7;
9584 		mmr_t	reserved_6     : 1;
9589 	mmr_t	sh_xnni1_to_md_intra_flow_debit_regval;
9591 		mmr_t	reserved_6     : 1;
9592 		mmr_t	vc2_cap        : 7;
9593 		mmr_t	reserved_5     : 1;
9594 		mmr_t	vc2_dyn        : 7;
9595 		mmr_t	reserved_4     : 9;
9596 		mmr_t	vc0_cap        : 7;
9597 		mmr_t	reserved_3     : 1;
9598 		mmr_t	vc0_dyn        : 7;
9599 		mmr_t	reserved_2     : 8;
9600 		mmr_t	vc2_force_cred : 1;
9601 		mmr_t	reserved_1     : 1;
9602 		mmr_t	vc2_withhold   : 6;
9603 		mmr_t	vc0_force_cred : 1;
9604 		mmr_t	reserved_0     : 1;
9605 		mmr_t	vc0_withhold   : 6;
9616 	mmr_t	sh_xnni1_to_iilb_intra_flow_debit_regval;
9618 		mmr_t	vc0_withhold   : 6;
9619 		mmr_t	reserved_0     : 1;
9620 		mmr_t	vc0_force_cred : 1;
9621 		mmr_t	vc2_withhold   : 6;
9622 		mmr_t	reserved_1     : 1;
9623 		mmr_t	vc2_force_cred : 1;
9624 		mmr_t	reserved_2     : 8;
9625 		mmr_t	vc0_dyn        : 7;
9626 		mmr_t	reserved_3     : 1;
9627 		mmr_t	vc0_cap        : 7;
9628 		mmr_t	reserved_4     : 9;
9629 		mmr_t	vc2_dyn        : 7;
9630 		mmr_t	reserved_5     : 1;
9631 		mmr_t	vc2_cap        : 7;
9632 		mmr_t	reserved_6     : 1;
9637 	mmr_t	sh_xnni1_to_iilb_intra_flow_debit_regval;
9639 		mmr_t	reserved_6     : 1;
9640 		mmr_t	vc2_cap        : 7;
9641 		mmr_t	reserved_5     : 1;
9642 		mmr_t	vc2_dyn        : 7;
9643 		mmr_t	reserved_4     : 9;
9644 		mmr_t	vc0_cap        : 7;
9645 		mmr_t	reserved_3     : 1;
9646 		mmr_t	vc0_dyn        : 7;
9647 		mmr_t	reserved_2     : 8;
9648 		mmr_t	vc2_force_cred : 1;
9649 		mmr_t	reserved_1     : 1;
9650 		mmr_t	vc2_withhold   : 6;
9651 		mmr_t	vc0_force_cred : 1;
9652 		mmr_t	reserved_0     : 1;
9653 		mmr_t	vc0_withhold   : 6;
9664 	mmr_t	sh_xnni1_fr_pi_intra_flow_credit_regval;
9666 		mmr_t	vc0_test    : 7;
9667 		mmr_t	reserved_0  : 1;
9668 		mmr_t	vc0_dyn     : 7;
9669 		mmr_t	reserved_1  : 1;
9670 		mmr_t	vc0_cap     : 7;
9671 		mmr_t	reserved_2  : 1;
9672 		mmr_t	vc2_test    : 7;
9673 		mmr_t	reserved_3  : 1;
9674 		mmr_t	vc2_dyn     : 7;
9675 		mmr_t	reserved_4  : 1;
9676 		mmr_t	vc2_cap     : 7;
9677 		mmr_t	reserved_5  : 17;
9682 	mmr_t	sh_xnni1_fr_pi_intra_flow_credit_regval;
9684 		mmr_t	reserved_5  : 17;
9685 		mmr_t	vc2_cap     : 7;
9686 		mmr_t	reserved_4  : 1;
9687 		mmr_t	vc2_dyn     : 7;
9688 		mmr_t	reserved_3  : 1;
9689 		mmr_t	vc2_test    : 7;
9690 		mmr_t	reserved_2  : 1;
9691 		mmr_t	vc0_cap     : 7;
9692 		mmr_t	reserved_1  : 1;
9693 		mmr_t	vc0_dyn     : 7;
9694 		mmr_t	reserved_0  : 1;
9695 		mmr_t	vc0_test    : 7;
9706 	mmr_t	sh_xnni1_fr_md_intra_flow_credit_regval;
9708 		mmr_t	vc0_test    : 7;
9709 		mmr_t	reserved_0  : 1;
9710 		mmr_t	vc0_dyn     : 7;
9711 		mmr_t	reserved_1  : 1;
9712 		mmr_t	vc0_cap     : 7;
9713 		mmr_t	reserved_2  : 1;
9714 		mmr_t	vc2_test    : 7;
9715 		mmr_t	reserved_3  : 1;
9716 		mmr_t	vc2_dyn     : 7;
9717 		mmr_t	reserved_4  : 1;
9718 		mmr_t	vc2_cap     : 7;
9719 		mmr_t	reserved_5  : 17;
9724 	mmr_t	sh_xnni1_fr_md_intra_flow_credit_regval;
9726 		mmr_t	reserved_5  : 17;
9727 		mmr_t	vc2_cap     : 7;
9728 		mmr_t	reserved_4  : 1;
9729 		mmr_t	vc2_dyn     : 7;
9730 		mmr_t	reserved_3  : 1;
9731 		mmr_t	vc2_test    : 7;
9732 		mmr_t	reserved_2  : 1;
9733 		mmr_t	vc0_cap     : 7;
9734 		mmr_t	reserved_1  : 1;
9735 		mmr_t	vc0_dyn     : 7;
9736 		mmr_t	reserved_0  : 1;
9737 		mmr_t	vc0_test    : 7;
9748 	mmr_t	sh_xnni1_fr_iilb_intra_flow_credit_regval;
9750 		mmr_t	vc0_test    : 7;
9751 		mmr_t	reserved_0  : 1;
9752 		mmr_t	vc0_dyn     : 7;
9753 		mmr_t	reserved_1  : 1;
9754 		mmr_t	vc0_cap     : 7;
9755 		mmr_t	reserved_2  : 1;
9756 		mmr_t	vc2_test    : 7;
9757 		mmr_t	reserved_3  : 1;
9758 		mmr_t	vc2_dyn     : 7;
9759 		mmr_t	reserved_4  : 1;
9760 		mmr_t	vc2_cap     : 7;
9761 		mmr_t	reserved_5  : 17;
9766 	mmr_t	sh_xnni1_fr_iilb_intra_flow_credit_regval;
9768 		mmr_t	reserved_5  : 17;
9769 		mmr_t	vc2_cap     : 7;
9770 		mmr_t	reserved_4  : 1;
9771 		mmr_t	vc2_dyn     : 7;
9772 		mmr_t	reserved_3  : 1;
9773 		mmr_t	vc2_test    : 7;
9774 		mmr_t	reserved_2  : 1;
9775 		mmr_t	vc0_cap     : 7;
9776 		mmr_t	reserved_1  : 1;
9777 		mmr_t	vc0_dyn     : 7;
9778 		mmr_t	reserved_0  : 1;
9779 		mmr_t	vc0_test    : 7;
9790 	mmr_t	sh_xnni1_0_intrani_flow_regval;
9792 		mmr_t	debit_vc0_withhold   : 6;
9793 		mmr_t	reserved_0           : 1;
9794 		mmr_t	debit_vc0_force_cred : 1;
9795 		mmr_t	reserved_1           : 56;
9800 	mmr_t	sh_xnni1_0_intrani_flow_regval;
9802 		mmr_t	reserved_1           : 56;
9803 		mmr_t	debit_vc0_force_cred : 1;
9804 		mmr_t	reserved_0           : 1;
9805 		mmr_t	debit_vc0_withhold   : 6;
9816 	mmr_t	sh_xnni1_1_intrani_flow_regval;
9818 		mmr_t	debit_vc1_withhold   : 6;
9819 		mmr_t	reserved_0           : 1;
9820 		mmr_t	debit_vc1_force_cred : 1;
9821 		mmr_t	reserved_1           : 56;
9826 	mmr_t	sh_xnni1_1_intrani_flow_regval;
9828 		mmr_t	reserved_1           : 56;
9829 		mmr_t	debit_vc1_force_cred : 1;
9830 		mmr_t	reserved_0           : 1;
9831 		mmr_t	debit_vc1_withhold   : 6;
9842 	mmr_t	sh_xnni1_2_intrani_flow_regval;
9844 		mmr_t	debit_vc2_withhold   : 6;
9845 		mmr_t	reserved_0           : 1;
9846 		mmr_t	debit_vc2_force_cred : 1;
9847 		mmr_t	reserved_1           : 56;
9852 	mmr_t	sh_xnni1_2_intrani_flow_regval;
9854 		mmr_t	reserved_1           : 56;
9855 		mmr_t	debit_vc2_force_cred : 1;
9856 		mmr_t	reserved_0           : 1;
9857 		mmr_t	debit_vc2_withhold   : 6;
9868 	mmr_t	sh_xnni1_3_intrani_flow_regval;
9870 		mmr_t	debit_vc3_withhold   : 6;
9871 		mmr_t	reserved_0           : 1;
9872 		mmr_t	debit_vc3_force_cred : 1;
9873 		mmr_t	reserved_1           : 56;
9878 	mmr_t	sh_xnni1_3_intrani_flow_regval;
9880 		mmr_t	reserved_1           : 56;
9881 		mmr_t	debit_vc3_force_cred : 1;
9882 		mmr_t	reserved_0           : 1;
9883 		mmr_t	debit_vc3_withhold   : 6;
9894 	mmr_t	sh_xnni1_vcswitch_flow_regval;
9896 		mmr_t	ni_vcfifo_dateline_switch : 1;
9897 		mmr_t	reserved_0                : 7;
9898 		mmr_t	pi_vcfifo_switch          : 1;
9899 		mmr_t	reserved_1                : 7;
9900 		mmr_t	md_vcfifo_switch          : 1;
9901 		mmr_t	reserved_2                : 7;
9902 		mmr_t	iilb_vcfifo_switch        : 1;
9903 		mmr_t	reserved_3                : 7;
9904 		mmr_t	disable_sync_bypass_in    : 1;
9905 		mmr_t	disable_sync_bypass_out   : 1;
9906 		mmr_t	async_fifoes              : 1;
9907 		mmr_t	reserved_4                : 29;
9912 	mmr_t	sh_xnni1_vcswitch_flow_regval;
9914 		mmr_t	reserved_4                : 29;
9915 		mmr_t	async_fifoes              : 1;
9916 		mmr_t	disable_sync_bypass_out   : 1;
9917 		mmr_t	disable_sync_bypass_in    : 1;
9918 		mmr_t	reserved_3                : 7;
9919 		mmr_t	iilb_vcfifo_switch        : 1;
9920 		mmr_t	reserved_2                : 7;
9921 		mmr_t	md_vcfifo_switch          : 1;
9922 		mmr_t	reserved_1                : 7;
9923 		mmr_t	pi_vcfifo_switch          : 1;
9924 		mmr_t	reserved_0                : 7;
9925 		mmr_t	ni_vcfifo_dateline_switch : 1;
9936 	mmr_t	sh_xnni1_timer_reg_regval;
9938 		mmr_t	timeout_reg     : 24;
9939 		mmr_t	reserved_0      : 8;
9940 		mmr_t	linkcleanup_reg : 1;
9941 		mmr_t	reserved_1      : 31;
9946 	mmr_t	sh_xnni1_timer_reg_regval;
9948 		mmr_t	reserved_1      : 31;
9949 		mmr_t	linkcleanup_reg : 1;
9950 		mmr_t	reserved_0      : 8;
9951 		mmr_t	timeout_reg     : 24;
9962 	mmr_t	sh_xnni1_fifo02_flow_regval;
9964 		mmr_t	count_vc0_limit : 4;
9965 		mmr_t	reserved_0      : 4;
9966 		mmr_t	count_vc0_dyn   : 4;
9967 		mmr_t	reserved_1      : 4;
9968 		mmr_t	count_vc0_cap   : 4;
9969 		mmr_t	reserved_2      : 4;
9970 		mmr_t	count_vc2_limit : 4;
9971 		mmr_t	reserved_3      : 4;
9972 		mmr_t	count_vc2_dyn   : 4;
9973 		mmr_t	reserved_4      : 4;
9974 		mmr_t	count_vc2_cap   : 4;
9975 		mmr_t	reserved_5      : 20;
9980 	mmr_t	sh_xnni1_fifo02_flow_regval;
9982 		mmr_t	reserved_5      : 20;
9983 		mmr_t	count_vc2_cap   : 4;
9984 		mmr_t	reserved_4      : 4;
9985 		mmr_t	count_vc2_dyn   : 4;
9986 		mmr_t	reserved_3      : 4;
9987 		mmr_t	count_vc2_limit : 4;
9988 		mmr_t	reserved_2      : 4;
9989 		mmr_t	count_vc0_cap   : 4;
9990 		mmr_t	reserved_1      : 4;
9991 		mmr_t	count_vc0_dyn   : 4;
9992 		mmr_t	reserved_0      : 4;
9993 		mmr_t	count_vc0_limit : 4;
10004 	mmr_t	sh_xnni1_fifo13_flow_regval;
10006 		mmr_t	count_vc1_limit : 4;
10007 		mmr_t	reserved_0      : 4;
10008 		mmr_t	count_vc1_dyn   : 4;
10009 		mmr_t	reserved_1      : 4;
10010 		mmr_t	count_vc1_cap   : 4;
10011 		mmr_t	reserved_2      : 4;
10012 		mmr_t	count_vc3_limit : 4;
10013 		mmr_t	reserved_3      : 4;
10014 		mmr_t	count_vc3_dyn   : 4;
10015 		mmr_t	reserved_4      : 4;
10016 		mmr_t	count_vc3_cap   : 4;
10017 		mmr_t	reserved_5      : 20;
10022 	mmr_t	sh_xnni1_fifo13_flow_regval;
10024 		mmr_t	reserved_5      : 20;
10025 		mmr_t	count_vc3_cap   : 4;
10026 		mmr_t	reserved_4      : 4;
10027 		mmr_t	count_vc3_dyn   : 4;
10028 		mmr_t	reserved_3      : 4;
10029 		mmr_t	count_vc3_limit : 4;
10030 		mmr_t	reserved_2      : 4;
10031 		mmr_t	count_vc1_cap   : 4;
10032 		mmr_t	reserved_1      : 4;
10033 		mmr_t	count_vc1_dyn   : 4;
10034 		mmr_t	reserved_0      : 4;
10035 		mmr_t	count_vc1_limit : 4;
10046 	mmr_t	sh_xnni1_ni_flow_regval;
10048 		mmr_t	vc0_limit   : 4;
10049 		mmr_t	reserved_0  : 4;
10050 		mmr_t	vc0_dyn     : 4;
10051 		mmr_t	vc0_cap     : 4;
10052 		mmr_t	vc1_limit   : 4;
10053 		mmr_t	reserved_1  : 4;
10054 		mmr_t	vc1_dyn     : 4;
10055 		mmr_t	vc1_cap     : 4;
10056 		mmr_t	vc2_limit   : 4;
10057 		mmr_t	reserved_2  : 4;
10058 		mmr_t	vc2_dyn     : 4;
10059 		mmr_t	vc2_cap     : 4;
10060 		mmr_t	vc3_limit   : 4;
10061 		mmr_t	reserved_3  : 4;
10062 		mmr_t	vc3_dyn     : 4;
10063 		mmr_t	vc3_cap     : 4;
10068 	mmr_t	sh_xnni1_ni_flow_regval;
10070 		mmr_t	vc3_cap     : 4;
10071 		mmr_t	vc3_dyn     : 4;
10072 		mmr_t	reserved_3  : 4;
10073 		mmr_t	vc3_limit   : 4;
10074 		mmr_t	vc2_cap     : 4;
10075 		mmr_t	vc2_dyn     : 4;
10076 		mmr_t	reserved_2  : 4;
10077 		mmr_t	vc2_limit   : 4;
10078 		mmr_t	vc1_cap     : 4;
10079 		mmr_t	vc1_dyn     : 4;
10080 		mmr_t	reserved_1  : 4;
10081 		mmr_t	vc1_limit   : 4;
10082 		mmr_t	vc0_cap     : 4;
10083 		mmr_t	vc0_dyn     : 4;
10084 		mmr_t	reserved_0  : 4;
10085 		mmr_t	vc0_limit   : 4;
10096 	mmr_t	sh_xnni1_dead_flow_regval;
10098 		mmr_t	vc0_limit   : 4;
10099 		mmr_t	reserved_0  : 4;
10100 		mmr_t	vc0_dyn     : 4;
10101 		mmr_t	vc0_cap     : 4;
10102 		mmr_t	vc1_limit   : 4;
10103 		mmr_t	reserved_1  : 4;
10104 		mmr_t	vc1_dyn     : 4;
10105 		mmr_t	vc1_cap     : 4;
10106 		mmr_t	vc2_limit   : 4;
10107 		mmr_t	reserved_2  : 4;
10108 		mmr_t	vc2_dyn     : 4;
10109 		mmr_t	vc2_cap     : 4;
10110 		mmr_t	vc3_limit   : 4;
10111 		mmr_t	reserved_3  : 4;
10112 		mmr_t	vc3_dyn     : 4;
10113 		mmr_t	vc3_cap     : 4;
10118 	mmr_t	sh_xnni1_dead_flow_regval;
10120 		mmr_t	vc3_cap     : 4;
10121 		mmr_t	vc3_dyn     : 4;
10122 		mmr_t	reserved_3  : 4;
10123 		mmr_t	vc3_limit   : 4;
10124 		mmr_t	vc2_cap     : 4;
10125 		mmr_t	vc2_dyn     : 4;
10126 		mmr_t	reserved_2  : 4;
10127 		mmr_t	vc2_limit   : 4;
10128 		mmr_t	vc1_cap     : 4;
10129 		mmr_t	vc1_dyn     : 4;
10130 		mmr_t	reserved_1  : 4;
10131 		mmr_t	vc1_limit   : 4;
10132 		mmr_t	vc0_cap     : 4;
10133 		mmr_t	vc0_dyn     : 4;
10134 		mmr_t	reserved_0  : 4;
10135 		mmr_t	vc0_limit   : 4;
10146 	mmr_t	sh_xnni1_inject_age_regval;
10148 		mmr_t	request_inject : 8;
10149 		mmr_t	reply_inject   : 8;
10150 		mmr_t	reserved_0     : 48;
10155 	mmr_t	sh_xnni1_inject_age_regval;
10157 		mmr_t	reserved_0     : 48;
10158 		mmr_t	reply_inject   : 8;
10159 		mmr_t	request_inject : 8;
10171 	mmr_t	sh_xn_debug_sel_regval;
10173 		mmr_t	nibble0_rlm_sel    : 3;
10174 		mmr_t	reserved_0         : 1;
10175 		mmr_t	nibble0_nibble_sel : 3;
10176 		mmr_t	reserved_1         : 1;
10177 		mmr_t	nibble1_rlm_sel    : 3;
10178 		mmr_t	reserved_2         : 1;
10179 		mmr_t	nibble1_nibble_sel : 3;
10180 		mmr_t	reserved_3         : 1;
10181 		mmr_t	nibble2_rlm_sel    : 3;
10182 		mmr_t	reserved_4         : 1;
10183 		mmr_t	nibble2_nibble_sel : 3;
10184 		mmr_t	reserved_5         : 1;
10185 		mmr_t	nibble3_rlm_sel    : 3;
10186 		mmr_t	reserved_6         : 1;
10187 		mmr_t	nibble3_nibble_sel : 3;
10188 		mmr_t	reserved_7         : 1;
10189 		mmr_t	nibble4_rlm_sel    : 3;
10190 		mmr_t	reserved_8         : 1;
10191 		mmr_t	nibble4_nibble_sel : 3;
10192 		mmr_t	reserved_9         : 1;
10193 		mmr_t	nibble5_rlm_sel    : 3;
10194 		mmr_t	reserved_10        : 1;
10195 		mmr_t	nibble5_nibble_sel : 3;
10196 		mmr_t	reserved_11        : 1;
10197 		mmr_t	nibble6_rlm_sel    : 3;
10198 		mmr_t	reserved_12        : 1;
10199 		mmr_t	nibble6_nibble_sel : 3;
10200 		mmr_t	reserved_13        : 1;
10201 		mmr_t	nibble7_rlm_sel    : 3;
10202 		mmr_t	reserved_14        : 1;
10203 		mmr_t	nibble7_nibble_sel : 3;
10204 		mmr_t	trigger_enable     : 1;
10209 	mmr_t	sh_xn_debug_sel_regval;
10211 		mmr_t	trigger_enable     : 1;
10212 		mmr_t	nibble7_nibble_sel : 3;
10213 		mmr_t	reserved_14        : 1;
10214 		mmr_t	nibble7_rlm_sel    : 3;
10215 		mmr_t	reserved_13        : 1;
10216 		mmr_t	nibble6_nibble_sel : 3;
10217 		mmr_t	reserved_12        : 1;
10218 		mmr_t	nibble6_rlm_sel    : 3;
10219 		mmr_t	reserved_11        : 1;
10220 		mmr_t	nibble5_nibble_sel : 3;
10221 		mmr_t	reserved_10        : 1;
10222 		mmr_t	nibble5_rlm_sel    : 3;
10223 		mmr_t	reserved_9         : 1;
10224 		mmr_t	nibble4_nibble_sel : 3;
10225 		mmr_t	reserved_8         : 1;
10226 		mmr_t	nibble4_rlm_sel    : 3;
10227 		mmr_t	reserved_7         : 1;
10228 		mmr_t	nibble3_nibble_sel : 3;
10229 		mmr_t	reserved_6         : 1;
10230 		mmr_t	nibble3_rlm_sel    : 3;
10231 		mmr_t	reserved_5         : 1;
10232 		mmr_t	nibble2_nibble_sel : 3;
10233 		mmr_t	reserved_4         : 1;
10234 		mmr_t	nibble2_rlm_sel    : 3;
10235 		mmr_t	reserved_3         : 1;
10236 		mmr_t	nibble1_nibble_sel : 3;
10237 		mmr_t	reserved_2         : 1;
10238 		mmr_t	nibble1_rlm_sel    : 3;
10239 		mmr_t	reserved_1         : 1;
10240 		mmr_t	nibble0_nibble_sel : 3;
10241 		mmr_t	reserved_0         : 1;
10242 		mmr_t	nibble0_rlm_sel    : 3;
10254 	mmr_t	sh_xn_debug_trig_sel_regval;
10256 		mmr_t	trigger0_rlm_sel    : 3;
10257 		mmr_t	reserved_0          : 1;
10258 		mmr_t	trigger0_nibble_sel : 3;
10259 		mmr_t	reserved_1          : 1;
10260 		mmr_t	trigger1_rlm_sel    : 3;
10261 		mmr_t	reserved_2          : 1;
10262 		mmr_t	trigger1_nibble_sel : 3;
10263 		mmr_t	reserved_3          : 1;
10264 		mmr_t	trigger2_rlm_sel    : 3;
10265 		mmr_t	reserved_4          : 1;
10266 		mmr_t	trigger2_nibble_sel : 3;
10267 		mmr_t	reserved_5          : 1;
10268 		mmr_t	trigger3_rlm_sel    : 3;
10269 		mmr_t	reserved_6          : 1;
10270 		mmr_t	trigger3_nibble_sel : 3;
10271 		mmr_t	reserved_7          : 1;
10272 		mmr_t	trigger4_rlm_sel    : 3;
10273 		mmr_t	reserved_8          : 1;
10274 		mmr_t	trigger4_nibble_sel : 3;
10275 		mmr_t	reserved_9          : 1;
10276 		mmr_t	trigger5_rlm_sel    : 3;
10277 		mmr_t	reserved_10         : 1;
10278 		mmr_t	trigger5_nibble_sel : 3;
10279 		mmr_t	reserved_11         : 1;
10280 		mmr_t	trigger6_rlm_sel    : 3;
10281 		mmr_t	reserved_12         : 1;
10282 		mmr_t	trigger6_nibble_sel : 3;
10283 		mmr_t	reserved_13         : 1;
10284 		mmr_t	trigger7_rlm_sel    : 3;
10285 		mmr_t	reserved_14         : 1;
10286 		mmr_t	trigger7_nibble_sel : 3;
10287 		mmr_t	reserved_15         : 1;
10292 	mmr_t	sh_xn_debug_trig_sel_regval;
10294 		mmr_t	reserved_15         : 1;
10295 		mmr_t	trigger7_nibble_sel : 3;
10296 		mmr_t	reserved_14         : 1;
10297 		mmr_t	trigger7_rlm_sel    : 3;
10298 		mmr_t	reserved_13         : 1;
10299 		mmr_t	trigger6_nibble_sel : 3;
10300 		mmr_t	reserved_12         : 1;
10301 		mmr_t	trigger6_rlm_sel    : 3;
10302 		mmr_t	reserved_11         : 1;
10303 		mmr_t	trigger5_nibble_sel : 3;
10304 		mmr_t	reserved_10         : 1;
10305 		mmr_t	trigger5_rlm_sel    : 3;
10306 		mmr_t	reserved_9          : 1;
10307 		mmr_t	trigger4_nibble_sel : 3;
10308 		mmr_t	reserved_8          : 1;
10309 		mmr_t	trigger4_rlm_sel    : 3;
10310 		mmr_t	reserved_7          : 1;
10311 		mmr_t	trigger3_nibble_sel : 3;
10312 		mmr_t	reserved_6          : 1;
10313 		mmr_t	trigger3_rlm_sel    : 3;
10314 		mmr_t	reserved_5          : 1;
10315 		mmr_t	trigger2_nibble_sel : 3;
10316 		mmr_t	reserved_4          : 1;
10317 		mmr_t	trigger2_rlm_sel    : 3;
10318 		mmr_t	reserved_3          : 1;
10319 		mmr_t	trigger1_nibble_sel : 3;
10320 		mmr_t	reserved_2          : 1;
10321 		mmr_t	trigger1_rlm_sel    : 3;
10322 		mmr_t	reserved_1          : 1;
10323 		mmr_t	trigger0_nibble_sel : 3;
10324 		mmr_t	reserved_0          : 1;
10325 		mmr_t	trigger0_rlm_sel    : 3;
10337 	mmr_t	sh_xn_trigger_compare_regval;
10339 		mmr_t	mask        : 32;
10340 		mmr_t	reserved_0  : 32;
10345 	mmr_t	sh_xn_trigger_compare_regval;
10347 		mmr_t	reserved_0  : 32;
10348 		mmr_t	mask        : 32;
10360 	mmr_t	sh_xn_trigger_data_regval;
10362 		mmr_t	compare_pattern : 32;
10363 		mmr_t	reserved_0      : 32;
10368 	mmr_t	sh_xn_trigger_data_regval;
10370 		mmr_t	reserved_0      : 32;
10371 		mmr_t	compare_pattern : 32;
10383 	mmr_t	sh_xn_iilb_debug_sel_regval;
10385 		mmr_t	nibble0_input_sel  : 3;
10386 		mmr_t	reserved_0         : 1;
10387 		mmr_t	nibble0_nibble_sel : 3;
10388 		mmr_t	reserved_1         : 1;
10389 		mmr_t	nibble1_input_sel  : 3;
10390 		mmr_t	reserved_2         : 1;
10391 		mmr_t	nibble1_nibble_sel : 3;
10392 		mmr_t	reserved_3         : 1;
10393 		mmr_t	nibble2_input_sel  : 3;
10394 		mmr_t	reserved_4         : 1;
10395 		mmr_t	nibble2_nibble_sel : 3;
10396 		mmr_t	reserved_5         : 1;
10397 		mmr_t	nibble3_input_sel  : 3;
10398 		mmr_t	reserved_6         : 1;
10399 		mmr_t	nibble3_nibble_sel : 3;
10400 		mmr_t	reserved_7         : 1;
10401 		mmr_t	nibble4_input_sel  : 3;
10402 		mmr_t	reserved_8         : 1;
10403 		mmr_t	nibble4_nibble_sel : 3;
10404 		mmr_t	reserved_9         : 1;
10405 		mmr_t	nibble5_input_sel  : 3;
10406 		mmr_t	reserved_10        : 1;
10407 		mmr_t	nibble5_nibble_sel : 3;
10408 		mmr_t	reserved_11        : 1;
10409 		mmr_t	nibble6_input_sel  : 3;
10410 		mmr_t	reserved_12        : 1;
10411 		mmr_t	nibble6_nibble_sel : 3;
10412 		mmr_t	reserved_13        : 1;
10413 		mmr_t	nibble7_input_sel  : 3;
10414 		mmr_t	reserved_14        : 1;
10415 		mmr_t	nibble7_nibble_sel : 3;
10416 		mmr_t	reserved_15        : 1;
10421 	mmr_t	sh_xn_iilb_debug_sel_regval;
10423 		mmr_t	reserved_15        : 1;
10424 		mmr_t	nibble7_nibble_sel : 3;
10425 		mmr_t	reserved_14        : 1;
10426 		mmr_t	nibble7_input_sel  : 3;
10427 		mmr_t	reserved_13        : 1;
10428 		mmr_t	nibble6_nibble_sel : 3;
10429 		mmr_t	reserved_12        : 1;
10430 		mmr_t	nibble6_input_sel  : 3;
10431 		mmr_t	reserved_11        : 1;
10432 		mmr_t	nibble5_nibble_sel : 3;
10433 		mmr_t	reserved_10        : 1;
10434 		mmr_t	nibble5_input_sel  : 3;
10435 		mmr_t	reserved_9         : 1;
10436 		mmr_t	nibble4_nibble_sel : 3;
10437 		mmr_t	reserved_8         : 1;
10438 		mmr_t	nibble4_input_sel  : 3;
10439 		mmr_t	reserved_7         : 1;
10440 		mmr_t	nibble3_nibble_sel : 3;
10441 		mmr_t	reserved_6         : 1;
10442 		mmr_t	nibble3_input_sel  : 3;
10443 		mmr_t	reserved_5         : 1;
10444 		mmr_t	nibble2_nibble_sel : 3;
10445 		mmr_t	reserved_4         : 1;
10446 		mmr_t	nibble2_input_sel  : 3;
10447 		mmr_t	reserved_3         : 1;
10448 		mmr_t	nibble1_nibble_sel : 3;
10449 		mmr_t	reserved_2         : 1;
10450 		mmr_t	nibble1_input_sel  : 3;
10451 		mmr_t	reserved_1         : 1;
10452 		mmr_t	nibble0_nibble_sel : 3;
10453 		mmr_t	reserved_0         : 1;
10454 		mmr_t	nibble0_input_sel  : 3;
10466 	mmr_t	sh_xn_pi_debug_sel_regval;
10468 		mmr_t	nibble0_input_sel  : 3;
10469 		mmr_t	reserved_0         : 1;
10470 		mmr_t	nibble0_nibble_sel : 3;
10471 		mmr_t	reserved_1         : 1;
10472 		mmr_t	nibble1_input_sel  : 3;
10473 		mmr_t	reserved_2         : 1;
10474 		mmr_t	nibble1_nibble_sel : 3;
10475 		mmr_t	reserved_3         : 1;
10476 		mmr_t	nibble2_input_sel  : 3;
10477 		mmr_t	reserved_4         : 1;
10478 		mmr_t	nibble2_nibble_sel : 3;
10479 		mmr_t	reserved_5         : 1;
10480 		mmr_t	nibble3_input_sel  : 3;
10481 		mmr_t	reserved_6         : 1;
10482 		mmr_t	nibble3_nibble_sel : 3;
10483 		mmr_t	reserved_7         : 1;
10484 		mmr_t	nibble4_input_sel  : 3;
10485 		mmr_t	reserved_8         : 1;
10486 		mmr_t	nibble4_nibble_sel : 3;
10487 		mmr_t	reserved_9         : 1;
10488 		mmr_t	nibble5_input_sel  : 3;
10489 		mmr_t	reserved_10        : 1;
10490 		mmr_t	nibble5_nibble_sel : 3;
10491 		mmr_t	reserved_11        : 1;
10492 		mmr_t	nibble6_input_sel  : 3;
10493 		mmr_t	reserved_12        : 1;
10494 		mmr_t	nibble6_nibble_sel : 3;
10495 		mmr_t	reserved_13        : 1;
10496 		mmr_t	nibble7_input_sel  : 3;
10497 		mmr_t	reserved_14        : 1;
10498 		mmr_t	nibble7_nibble_sel : 3;
10499 		mmr_t	reserved_15        : 1;
10504 	mmr_t	sh_xn_pi_debug_sel_regval;
10506 		mmr_t	reserved_15        : 1;
10507 		mmr_t	nibble7_nibble_sel : 3;
10508 		mmr_t	reserved_14        : 1;
10509 		mmr_t	nibble7_input_sel  : 3;
10510 		mmr_t	reserved_13        : 1;
10511 		mmr_t	nibble6_nibble_sel : 3;
10512 		mmr_t	reserved_12        : 1;
10513 		mmr_t	nibble6_input_sel  : 3;
10514 		mmr_t	reserved_11        : 1;
10515 		mmr_t	nibble5_nibble_sel : 3;
10516 		mmr_t	reserved_10        : 1;
10517 		mmr_t	nibble5_input_sel  : 3;
10518 		mmr_t	reserved_9         : 1;
10519 		mmr_t	nibble4_nibble_sel : 3;
10520 		mmr_t	reserved_8         : 1;
10521 		mmr_t	nibble4_input_sel  : 3;
10522 		mmr_t	reserved_7         : 1;
10523 		mmr_t	nibble3_nibble_sel : 3;
10524 		mmr_t	reserved_6         : 1;
10525 		mmr_t	nibble3_input_sel  : 3;
10526 		mmr_t	reserved_5         : 1;
10527 		mmr_t	nibble2_nibble_sel : 3;
10528 		mmr_t	reserved_4         : 1;
10529 		mmr_t	nibble2_input_sel  : 3;
10530 		mmr_t	reserved_3         : 1;
10531 		mmr_t	nibble1_nibble_sel : 3;
10532 		mmr_t	reserved_2         : 1;
10533 		mmr_t	nibble1_input_sel  : 3;
10534 		mmr_t	reserved_1         : 1;
10535 		mmr_t	nibble0_nibble_sel : 3;
10536 		mmr_t	reserved_0         : 1;
10537 		mmr_t	nibble0_input_sel  : 3;
10549 	mmr_t	sh_xn_md_debug_sel_regval;
10551 		mmr_t	nibble0_input_sel  : 3;
10552 		mmr_t	reserved_0         : 1;
10553 		mmr_t	nibble0_nibble_sel : 3;
10554 		mmr_t	reserved_1         : 1;
10555 		mmr_t	nibble1_input_sel  : 3;
10556 		mmr_t	reserved_2         : 1;
10557 		mmr_t	nibble1_nibble_sel : 3;
10558 		mmr_t	reserved_3         : 1;
10559 		mmr_t	nibble2_input_sel  : 3;
10560 		mmr_t	reserved_4         : 1;
10561 		mmr_t	nibble2_nibble_sel : 3;
10562 		mmr_t	reserved_5         : 1;
10563 		mmr_t	nibble3_input_sel  : 3;
10564 		mmr_t	reserved_6         : 1;
10565 		mmr_t	nibble3_nibble_sel : 3;
10566 		mmr_t	reserved_7         : 1;
10567 		mmr_t	nibble4_input_sel  : 3;
10568 		mmr_t	reserved_8         : 1;
10569 		mmr_t	nibble4_nibble_sel : 3;
10570 		mmr_t	reserved_9         : 1;
10571 		mmr_t	nibble5_input_sel  : 3;
10572 		mmr_t	reserved_10        : 1;
10573 		mmr_t	nibble5_nibble_sel : 3;
10574 		mmr_t	reserved_11        : 1;
10575 		mmr_t	nibble6_input_sel  : 3;
10576 		mmr_t	reserved_12        : 1;
10577 		mmr_t	nibble6_nibble_sel : 3;
10578 		mmr_t	reserved_13        : 1;
10579 		mmr_t	nibble7_input_sel  : 3;
10580 		mmr_t	reserved_14        : 1;
10581 		mmr_t	nibble7_nibble_sel : 3;
10582 		mmr_t	reserved_15        : 1;
10587 	mmr_t	sh_xn_md_debug_sel_regval;
10589 		mmr_t	reserved_15        : 1;
10590 		mmr_t	nibble7_nibble_sel : 3;
10591 		mmr_t	reserved_14        : 1;
10592 		mmr_t	nibble7_input_sel  : 3;
10593 		mmr_t	reserved_13        : 1;
10594 		mmr_t	nibble6_nibble_sel : 3;
10595 		mmr_t	reserved_12        : 1;
10596 		mmr_t	nibble6_input_sel  : 3;
10597 		mmr_t	reserved_11        : 1;
10598 		mmr_t	nibble5_nibble_sel : 3;
10599 		mmr_t	reserved_10        : 1;
10600 		mmr_t	nibble5_input_sel  : 3;
10601 		mmr_t	reserved_9         : 1;
10602 		mmr_t	nibble4_nibble_sel : 3;
10603 		mmr_t	reserved_8         : 1;
10604 		mmr_t	nibble4_input_sel  : 3;
10605 		mmr_t	reserved_7         : 1;
10606 		mmr_t	nibble3_nibble_sel : 3;
10607 		mmr_t	reserved_6         : 1;
10608 		mmr_t	nibble3_input_sel  : 3;
10609 		mmr_t	reserved_5         : 1;
10610 		mmr_t	nibble2_nibble_sel : 3;
10611 		mmr_t	reserved_4         : 1;
10612 		mmr_t	nibble2_input_sel  : 3;
10613 		mmr_t	reserved_3         : 1;
10614 		mmr_t	nibble1_nibble_sel : 3;
10615 		mmr_t	reserved_2         : 1;
10616 		mmr_t	nibble1_input_sel  : 3;
10617 		mmr_t	reserved_1         : 1;
10618 		mmr_t	nibble0_nibble_sel : 3;
10619 		mmr_t	reserved_0         : 1;
10620 		mmr_t	nibble0_input_sel  : 3;
10632 	mmr_t	sh_xn_ni0_debug_sel_regval;
10634 		mmr_t	nibble0_input_sel  : 3;
10635 		mmr_t	reserved_0         : 1;
10636 		mmr_t	nibble0_nibble_sel : 3;
10637 		mmr_t	reserved_1         : 1;
10638 		mmr_t	nibble1_input_sel  : 3;
10639 		mmr_t	reserved_2         : 1;
10640 		mmr_t	nibble1_nibble_sel : 3;
10641 		mmr_t	reserved_3         : 1;
10642 		mmr_t	nibble2_input_sel  : 3;
10643 		mmr_t	reserved_4         : 1;
10644 		mmr_t	nibble2_nibble_sel : 3;
10645 		mmr_t	reserved_5         : 1;
10646 		mmr_t	nibble3_input_sel  : 3;
10647 		mmr_t	reserved_6         : 1;
10648 		mmr_t	nibble3_nibble_sel : 3;
10649 		mmr_t	reserved_7         : 1;
10650 		mmr_t	nibble4_input_sel  : 3;
10651 		mmr_t	reserved_8         : 1;
10652 		mmr_t	nibble4_nibble_sel : 3;
10653 		mmr_t	reserved_9         : 1;
10654 		mmr_t	nibble5_input_sel  : 3;
10655 		mmr_t	reserved_10        : 1;
10656 		mmr_t	nibble5_nibble_sel : 3;
10657 		mmr_t	reserved_11        : 1;
10658 		mmr_t	nibble6_input_sel  : 3;
10659 		mmr_t	reserved_12        : 1;
10660 		mmr_t	nibble6_nibble_sel : 3;
10661 		mmr_t	reserved_13        : 1;
10662 		mmr_t	nibble7_input_sel  : 3;
10663 		mmr_t	reserved_14        : 1;
10664 		mmr_t	nibble7_nibble_sel : 3;
10665 		mmr_t	reserved_15        : 1;
10670 	mmr_t	sh_xn_ni0_debug_sel_regval;
10672 		mmr_t	reserved_15        : 1;
10673 		mmr_t	nibble7_nibble_sel : 3;
10674 		mmr_t	reserved_14        : 1;
10675 		mmr_t	nibble7_input_sel  : 3;
10676 		mmr_t	reserved_13        : 1;
10677 		mmr_t	nibble6_nibble_sel : 3;
10678 		mmr_t	reserved_12        : 1;
10679 		mmr_t	nibble6_input_sel  : 3;
10680 		mmr_t	reserved_11        : 1;
10681 		mmr_t	nibble5_nibble_sel : 3;
10682 		mmr_t	reserved_10        : 1;
10683 		mmr_t	nibble5_input_sel  : 3;
10684 		mmr_t	reserved_9         : 1;
10685 		mmr_t	nibble4_nibble_sel : 3;
10686 		mmr_t	reserved_8         : 1;
10687 		mmr_t	nibble4_input_sel  : 3;
10688 		mmr_t	reserved_7         : 1;
10689 		mmr_t	nibble3_nibble_sel : 3;
10690 		mmr_t	reserved_6         : 1;
10691 		mmr_t	nibble3_input_sel  : 3;
10692 		mmr_t	reserved_5         : 1;
10693 		mmr_t	nibble2_nibble_sel : 3;
10694 		mmr_t	reserved_4         : 1;
10695 		mmr_t	nibble2_input_sel  : 3;
10696 		mmr_t	reserved_3         : 1;
10697 		mmr_t	nibble1_nibble_sel : 3;
10698 		mmr_t	reserved_2         : 1;
10699 		mmr_t	nibble1_input_sel  : 3;
10700 		mmr_t	reserved_1         : 1;
10701 		mmr_t	nibble0_nibble_sel : 3;
10702 		mmr_t	reserved_0         : 1;
10703 		mmr_t	nibble0_input_sel  : 3;
10715 	mmr_t	sh_xn_ni1_debug_sel_regval;
10717 		mmr_t	nibble0_input_sel  : 3;
10718 		mmr_t	reserved_0         : 1;
10719 		mmr_t	nibble0_nibble_sel : 3;
10720 		mmr_t	reserved_1         : 1;
10721 		mmr_t	nibble1_input_sel  : 3;
10722 		mmr_t	reserved_2         : 1;
10723 		mmr_t	nibble1_nibble_sel : 3;
10724 		mmr_t	reserved_3         : 1;
10725 		mmr_t	nibble2_input_sel  : 3;
10726 		mmr_t	reserved_4         : 1;
10727 		mmr_t	nibble2_nibble_sel : 3;
10728 		mmr_t	reserved_5         : 1;
10729 		mmr_t	nibble3_input_sel  : 3;
10730 		mmr_t	reserved_6         : 1;
10731 		mmr_t	nibble3_nibble_sel : 3;
10732 		mmr_t	reserved_7         : 1;
10733 		mmr_t	nibble4_input_sel  : 3;
10734 		mmr_t	reserved_8         : 1;
10735 		mmr_t	nibble4_nibble_sel : 3;
10736 		mmr_t	reserved_9         : 1;
10737 		mmr_t	nibble5_input_sel  : 3;
10738 		mmr_t	reserved_10        : 1;
10739 		mmr_t	nibble5_nibble_sel : 3;
10740 		mmr_t	reserved_11        : 1;
10741 		mmr_t	nibble6_input_sel  : 3;
10742 		mmr_t	reserved_12        : 1;
10743 		mmr_t	nibble6_nibble_sel : 3;
10744 		mmr_t	reserved_13        : 1;
10745 		mmr_t	nibble7_input_sel  : 3;
10746 		mmr_t	reserved_14        : 1;
10747 		mmr_t	nibble7_nibble_sel : 3;
10748 		mmr_t	reserved_15        : 1;
10753 	mmr_t	sh_xn_ni1_debug_sel_regval;
10755 		mmr_t	reserved_15        : 1;
10756 		mmr_t	nibble7_nibble_sel : 3;
10757 		mmr_t	reserved_14        : 1;
10758 		mmr_t	nibble7_input_sel  : 3;
10759 		mmr_t	reserved_13        : 1;
10760 		mmr_t	nibble6_nibble_sel : 3;
10761 		mmr_t	reserved_12        : 1;
10762 		mmr_t	nibble6_input_sel  : 3;
10763 		mmr_t	reserved_11        : 1;
10764 		mmr_t	nibble5_nibble_sel : 3;
10765 		mmr_t	reserved_10        : 1;
10766 		mmr_t	nibble5_input_sel  : 3;
10767 		mmr_t	reserved_9         : 1;
10768 		mmr_t	nibble4_nibble_sel : 3;
10769 		mmr_t	reserved_8         : 1;
10770 		mmr_t	nibble4_input_sel  : 3;
10771 		mmr_t	reserved_7         : 1;
10772 		mmr_t	nibble3_nibble_sel : 3;
10773 		mmr_t	reserved_6         : 1;
10774 		mmr_t	nibble3_input_sel  : 3;
10775 		mmr_t	reserved_5         : 1;
10776 		mmr_t	nibble2_nibble_sel : 3;
10777 		mmr_t	reserved_4         : 1;
10778 		mmr_t	nibble2_input_sel  : 3;
10779 		mmr_t	reserved_3         : 1;
10780 		mmr_t	nibble1_nibble_sel : 3;
10781 		mmr_t	reserved_2         : 1;
10782 		mmr_t	nibble1_input_sel  : 3;
10783 		mmr_t	reserved_1         : 1;
10784 		mmr_t	nibble0_nibble_sel : 3;
10785 		mmr_t	reserved_0         : 1;
10786 		mmr_t	nibble0_input_sel  : 3;
10798 	mmr_t	sh_xn_iilb_lb_cmp_exp_data0_regval;
10800 		mmr_t	data        : 64;
10805 	mmr_t	sh_xn_iilb_lb_cmp_exp_data0_regval;
10807 		mmr_t	data        : 64;
10819 	mmr_t	sh_xn_iilb_lb_cmp_exp_data1_regval;
10821 		mmr_t	data        : 64;
10826 	mmr_t	sh_xn_iilb_lb_cmp_exp_data1_regval;
10828 		mmr_t	data        : 64;
10840 	mmr_t	sh_xn_iilb_lb_cmp_enable0_regval;
10842 		mmr_t	enable      : 64;
10847 	mmr_t	sh_xn_iilb_lb_cmp_enable0_regval;
10849 		mmr_t	enable      : 64;
10861 	mmr_t	sh_xn_iilb_lb_cmp_enable1_regval;
10863 		mmr_t	enable      : 64;
10868 	mmr_t	sh_xn_iilb_lb_cmp_enable1_regval;
10870 		mmr_t	enable      : 64;
10882 	mmr_t	sh_xn_iilb_ii_cmp_exp_data0_regval;
10884 		mmr_t	data        : 64;
10889 	mmr_t	sh_xn_iilb_ii_cmp_exp_data0_regval;
10891 		mmr_t	data        : 64;
10903 	mmr_t	sh_xn_iilb_ii_cmp_exp_data1_regval;
10905 		mmr_t	data        : 64;
10910 	mmr_t	sh_xn_iilb_ii_cmp_exp_data1_regval;
10912 		mmr_t	data        : 64;
10924 	mmr_t	sh_xn_iilb_ii_cmp_enable0_regval;
10926 		mmr_t	enable      : 64;
10931 	mmr_t	sh_xn_iilb_ii_cmp_enable0_regval;
10933 		mmr_t	enable      : 64;
10945 	mmr_t	sh_xn_iilb_ii_cmp_enable1_regval;
10947 		mmr_t	enable      : 64;
10952 	mmr_t	sh_xn_iilb_ii_cmp_enable1_regval;
10954 		mmr_t	enable      : 64;
10966 	mmr_t	sh_xn_iilb_md_cmp_exp_data0_regval;
10968 		mmr_t	data        : 64;
10973 	mmr_t	sh_xn_iilb_md_cmp_exp_data0_regval;
10975 		mmr_t	data        : 64;
10987 	mmr_t	sh_xn_iilb_md_cmp_exp_data1_regval;
10989 		mmr_t	data        : 64;
10994 	mmr_t	sh_xn_iilb_md_cmp_exp_data1_regval;
10996 		mmr_t	data        : 64;
11008 	mmr_t	sh_xn_iilb_md_cmp_enable0_regval;
11010 		mmr_t	enable      : 64;
11015 	mmr_t	sh_xn_iilb_md_cmp_enable0_regval;
11017 		mmr_t	enable      : 64;
11029 	mmr_t	sh_xn_iilb_md_cmp_enable1_regval;
11031 		mmr_t	enable      : 64;
11036 	mmr_t	sh_xn_iilb_md_cmp_enable1_regval;
11038 		mmr_t	enable      : 64;
11050 	mmr_t	sh_xn_iilb_pi_cmp_exp_data0_regval;
11052 		mmr_t	data        : 64;
11057 	mmr_t	sh_xn_iilb_pi_cmp_exp_data0_regval;
11059 		mmr_t	data        : 64;
11071 	mmr_t	sh_xn_iilb_pi_cmp_exp_data1_regval;
11073 		mmr_t	data        : 64;
11078 	mmr_t	sh_xn_iilb_pi_cmp_exp_data1_regval;
11080 		mmr_t	data        : 64;
11092 	mmr_t	sh_xn_iilb_pi_cmp_enable0_regval;
11094 		mmr_t	enable      : 64;
11099 	mmr_t	sh_xn_iilb_pi_cmp_enable0_regval;
11101 		mmr_t	enable      : 64;
11113 	mmr_t	sh_xn_iilb_pi_cmp_enable1_regval;
11115 		mmr_t	enable      : 64;
11120 	mmr_t	sh_xn_iilb_pi_cmp_enable1_regval;
11122 		mmr_t	enable      : 64;
11134 	mmr_t	sh_xn_iilb_ni0_cmp_exp_data0_regval;
11136 		mmr_t	data        : 64;
11141 	mmr_t	sh_xn_iilb_ni0_cmp_exp_data0_regval;
11143 		mmr_t	data        : 64;
11155 	mmr_t	sh_xn_iilb_ni0_cmp_exp_data1_regval;
11157 		mmr_t	data        : 64;
11162 	mmr_t	sh_xn_iilb_ni0_cmp_exp_data1_regval;
11164 		mmr_t	data        : 64;
11176 	mmr_t	sh_xn_iilb_ni0_cmp_enable0_regval;
11178 		mmr_t	enable      : 64;
11183 	mmr_t	sh_xn_iilb_ni0_cmp_enable0_regval;
11185 		mmr_t	enable      : 64;
11197 	mmr_t	sh_xn_iilb_ni0_cmp_enable1_regval;
11199 		mmr_t	enable      : 64;
11204 	mmr_t	sh_xn_iilb_ni0_cmp_enable1_regval;
11206 		mmr_t	enable      : 64;
11218 	mmr_t	sh_xn_iilb_ni1_cmp_exp_data0_regval;
11220 		mmr_t	data        : 64;
11225 	mmr_t	sh_xn_iilb_ni1_cmp_exp_data0_regval;
11227 		mmr_t	data        : 64;
11239 	mmr_t	sh_xn_iilb_ni1_cmp_exp_data1_regval;
11241 		mmr_t	data        : 64;
11246 	mmr_t	sh_xn_iilb_ni1_cmp_exp_data1_regval;
11248 		mmr_t	data        : 64;
11260 	mmr_t	sh_xn_iilb_ni1_cmp_enable0_regval;
11262 		mmr_t	enable      : 64;
11267 	mmr_t	sh_xn_iilb_ni1_cmp_enable0_regval;
11269 		mmr_t	enable      : 64;
11281 	mmr_t	sh_xn_iilb_ni1_cmp_enable1_regval;
11283 		mmr_t	enable      : 64;
11288 	mmr_t	sh_xn_iilb_ni1_cmp_enable1_regval;
11290 		mmr_t	enable      : 64;
11302 	mmr_t	sh_xn_md_iilb_cmp_exp_data0_regval;
11304 		mmr_t	data        : 64;
11309 	mmr_t	sh_xn_md_iilb_cmp_exp_data0_regval;
11311 		mmr_t	data        : 64;
11323 	mmr_t	sh_xn_md_iilb_cmp_exp_data1_regval;
11325 		mmr_t	data        : 64;
11330 	mmr_t	sh_xn_md_iilb_cmp_exp_data1_regval;
11332 		mmr_t	data        : 64;
11344 	mmr_t	sh_xn_md_iilb_cmp_enable0_regval;
11346 		mmr_t	enable      : 64;
11351 	mmr_t	sh_xn_md_iilb_cmp_enable0_regval;
11353 		mmr_t	enable      : 64;
11365 	mmr_t	sh_xn_md_iilb_cmp_enable1_regval;
11367 		mmr_t	enable      : 64;
11372 	mmr_t	sh_xn_md_iilb_cmp_enable1_regval;
11374 		mmr_t	enable      : 64;
11386 	mmr_t	sh_xn_md_ni0_cmp_exp_data0_regval;
11388 		mmr_t	data        : 64;
11393 	mmr_t	sh_xn_md_ni0_cmp_exp_data0_regval;
11395 		mmr_t	data        : 64;
11407 	mmr_t	sh_xn_md_ni0_cmp_exp_data1_regval;
11409 		mmr_t	data        : 64;
11414 	mmr_t	sh_xn_md_ni0_cmp_exp_data1_regval;
11416 		mmr_t	data        : 64;
11428 	mmr_t	sh_xn_md_ni0_cmp_enable0_regval;
11430 		mmr_t	enable      : 64;
11435 	mmr_t	sh_xn_md_ni0_cmp_enable0_regval;
11437 		mmr_t	enable      : 64;
11449 	mmr_t	sh_xn_md_ni0_cmp_enable1_regval;
11451 		mmr_t	enable      : 64;
11456 	mmr_t	sh_xn_md_ni0_cmp_enable1_regval;
11458 		mmr_t	enable      : 64;
11470 	mmr_t	sh_xn_md_ni1_cmp_exp_data0_regval;
11472 		mmr_t	data        : 64;
11477 	mmr_t	sh_xn_md_ni1_cmp_exp_data0_regval;
11479 		mmr_t	data        : 64;
11491 	mmr_t	sh_xn_md_ni1_cmp_exp_data1_regval;
11493 		mmr_t	data        : 64;
11498 	mmr_t	sh_xn_md_ni1_cmp_exp_data1_regval;
11500 		mmr_t	data        : 64;
11512 	mmr_t	sh_xn_md_ni1_cmp_enable0_regval;
11514 		mmr_t	enable      : 64;
11519 	mmr_t	sh_xn_md_ni1_cmp_enable0_regval;
11521 		mmr_t	enable      : 64;
11533 	mmr_t	sh_xn_md_ni1_cmp_enable1_regval;
11535 		mmr_t	enable      : 64;
11540 	mmr_t	sh_xn_md_ni1_cmp_enable1_regval;
11542 		mmr_t	enable      : 64;
11554 	mmr_t	sh_xn_md_sic_cmp_exp_hdr0_regval;
11556 		mmr_t	data        : 64;
11561 	mmr_t	sh_xn_md_sic_cmp_exp_hdr0_regval;
11563 		mmr_t	data        : 64;
11575 	mmr_t	sh_xn_md_sic_cmp_exp_hdr1_regval;
11577 		mmr_t	data        : 42;
11578 		mmr_t	reserved_0  : 22;
11583 	mmr_t	sh_xn_md_sic_cmp_exp_hdr1_regval;
11585 		mmr_t	reserved_0  : 22;
11586 		mmr_t	data        : 42;
11598 	mmr_t	sh_xn_md_sic_cmp_hdr_enable0_regval;
11600 		mmr_t	enable      : 64;
11605 	mmr_t	sh_xn_md_sic_cmp_hdr_enable0_regval;
11607 		mmr_t	enable      : 64;
11619 	mmr_t	sh_xn_md_sic_cmp_hdr_enable1_regval;
11621 		mmr_t	enable      : 42;
11622 		mmr_t	reserved_0  : 22;
11627 	mmr_t	sh_xn_md_sic_cmp_hdr_enable1_regval;
11629 		mmr_t	reserved_0  : 22;
11630 		mmr_t	enable      : 42;
11642 	mmr_t	sh_xn_md_sic_cmp_data0_regval;
11644 		mmr_t	data0       : 64;
11649 	mmr_t	sh_xn_md_sic_cmp_data0_regval;
11651 		mmr_t	data0       : 64;
11663 	mmr_t	sh_xn_md_sic_cmp_data1_regval;
11665 		mmr_t	data1       : 64;
11670 	mmr_t	sh_xn_md_sic_cmp_data1_regval;
11672 		mmr_t	data1       : 64;
11684 	mmr_t	sh_xn_md_sic_cmp_data2_regval;
11686 		mmr_t	data2       : 64;
11691 	mmr_t	sh_xn_md_sic_cmp_data2_regval;
11693 		mmr_t	data2       : 64;
11705 	mmr_t	sh_xn_md_sic_cmp_data3_regval;
11707 		mmr_t	data3       : 64;
11712 	mmr_t	sh_xn_md_sic_cmp_data3_regval;
11714 		mmr_t	data3       : 64;
11726 	mmr_t	sh_xn_md_sic_cmp_data_enable0_regval;
11728 		mmr_t	data_enable0 : 64;
11733 	mmr_t	sh_xn_md_sic_cmp_data_enable0_regval;
11735 		mmr_t	data_enable0 : 64;
11747 	mmr_t	sh_xn_md_sic_cmp_data_enable1_regval;
11749 		mmr_t	data_enable1 : 64;
11754 	mmr_t	sh_xn_md_sic_cmp_data_enable1_regval;
11756 		mmr_t	data_enable1 : 64;
11768 	mmr_t	sh_xn_md_sic_cmp_data_enable2_regval;
11770 		mmr_t	data_enable2 : 64;
11775 	mmr_t	sh_xn_md_sic_cmp_data_enable2_regval;
11777 		mmr_t	data_enable2 : 64;
11789 	mmr_t	sh_xn_md_sic_cmp_data_enable3_regval;
11791 		mmr_t	data_enable3 : 64;
11796 	mmr_t	sh_xn_md_sic_cmp_data_enable3_regval;
11798 		mmr_t	data_enable3 : 64;
11810 	mmr_t	sh_xn_pi_iilb_cmp_exp_data0_regval;
11812 		mmr_t	data        : 64;
11817 	mmr_t	sh_xn_pi_iilb_cmp_exp_data0_regval;
11819 		mmr_t	data        : 64;
11831 	mmr_t	sh_xn_pi_iilb_cmp_exp_data1_regval;
11833 		mmr_t	data        : 64;
11838 	mmr_t	sh_xn_pi_iilb_cmp_exp_data1_regval;
11840 		mmr_t	data        : 64;
11852 	mmr_t	sh_xn_pi_iilb_cmp_enable0_regval;
11854 		mmr_t	enable      : 64;
11859 	mmr_t	sh_xn_pi_iilb_cmp_enable0_regval;
11861 		mmr_t	enable      : 64;
11873 	mmr_t	sh_xn_pi_iilb_cmp_enable1_regval;
11875 		mmr_t	enable      : 64;
11880 	mmr_t	sh_xn_pi_iilb_cmp_enable1_regval;
11882 		mmr_t	enable      : 64;
11894 	mmr_t	sh_xn_pi_ni0_cmp_exp_data0_regval;
11896 		mmr_t	data        : 64;
11901 	mmr_t	sh_xn_pi_ni0_cmp_exp_data0_regval;
11903 		mmr_t	data        : 64;
11915 	mmr_t	sh_xn_pi_ni0_cmp_exp_data1_regval;
11917 		mmr_t	data        : 64;
11922 	mmr_t	sh_xn_pi_ni0_cmp_exp_data1_regval;
11924 		mmr_t	data        : 64;
11936 	mmr_t	sh_xn_pi_ni0_cmp_enable0_regval;
11938 		mmr_t	enable      : 64;
11943 	mmr_t	sh_xn_pi_ni0_cmp_enable0_regval;
11945 		mmr_t	enable      : 64;
11957 	mmr_t	sh_xn_pi_ni0_cmp_enable1_regval;
11959 		mmr_t	enable      : 64;
11964 	mmr_t	sh_xn_pi_ni0_cmp_enable1_regval;
11966 		mmr_t	enable      : 64;
11978 	mmr_t	sh_xn_pi_ni1_cmp_exp_data0_regval;
11980 		mmr_t	data        : 64;
11985 	mmr_t	sh_xn_pi_ni1_cmp_exp_data0_regval;
11987 		mmr_t	data        : 64;
11999 	mmr_t	sh_xn_pi_ni1_cmp_exp_data1_regval;
12001 		mmr_t	data        : 64;
12006 	mmr_t	sh_xn_pi_ni1_cmp_exp_data1_regval;
12008 		mmr_t	data        : 64;
12020 	mmr_t	sh_xn_pi_ni1_cmp_enable0_regval;
12022 		mmr_t	enable      : 64;
12027 	mmr_t	sh_xn_pi_ni1_cmp_enable0_regval;
12029 		mmr_t	enable      : 64;
12041 	mmr_t	sh_xn_pi_ni1_cmp_enable1_regval;
12043 		mmr_t	enable      : 64;
12048 	mmr_t	sh_xn_pi_ni1_cmp_enable1_regval;
12050 		mmr_t	enable      : 64;
12062 	mmr_t	sh_xn_pi_sic_cmp_exp_hdr0_regval;
12064 		mmr_t	data        : 64;
12069 	mmr_t	sh_xn_pi_sic_cmp_exp_hdr0_regval;
12071 		mmr_t	data        : 64;
12083 	mmr_t	sh_xn_pi_sic_cmp_exp_hdr1_regval;
12085 		mmr_t	data        : 42;
12086 		mmr_t	reserved_0  : 22;
12091 	mmr_t	sh_xn_pi_sic_cmp_exp_hdr1_regval;
12093 		mmr_t	reserved_0  : 22;
12094 		mmr_t	data        : 42;
12106 	mmr_t	sh_xn_pi_sic_cmp_hdr_enable0_regval;
12108 		mmr_t	enable      : 64;
12113 	mmr_t	sh_xn_pi_sic_cmp_hdr_enable0_regval;
12115 		mmr_t	enable      : 64;
12127 	mmr_t	sh_xn_pi_sic_cmp_hdr_enable1_regval;
12129 		mmr_t	enable      : 42;
12130 		mmr_t	reserved_0  : 22;
12135 	mmr_t	sh_xn_pi_sic_cmp_hdr_enable1_regval;
12137 		mmr_t	reserved_0  : 22;
12138 		mmr_t	enable      : 42;
12150 	mmr_t	sh_xn_pi_sic_cmp_data0_regval;
12152 		mmr_t	data0       : 64;
12157 	mmr_t	sh_xn_pi_sic_cmp_data0_regval;
12159 		mmr_t	data0       : 64;
12171 	mmr_t	sh_xn_pi_sic_cmp_data1_regval;
12173 		mmr_t	data1       : 64;
12178 	mmr_t	sh_xn_pi_sic_cmp_data1_regval;
12180 		mmr_t	data1       : 64;
12192 	mmr_t	sh_xn_pi_sic_cmp_data2_regval;
12194 		mmr_t	data2       : 64;
12199 	mmr_t	sh_xn_pi_sic_cmp_data2_regval;
12201 		mmr_t	data2       : 64;
12213 	mmr_t	sh_xn_pi_sic_cmp_data3_regval;
12215 		mmr_t	data3       : 64;
12220 	mmr_t	sh_xn_pi_sic_cmp_data3_regval;
12222 		mmr_t	data3       : 64;
12234 	mmr_t	sh_xn_pi_sic_cmp_data_enable0_regval;
12236 		mmr_t	data_enable0 : 64;
12241 	mmr_t	sh_xn_pi_sic_cmp_data_enable0_regval;
12243 		mmr_t	data_enable0 : 64;
12255 	mmr_t	sh_xn_pi_sic_cmp_data_enable1_regval;
12257 		mmr_t	data_enable1 : 64;
12262 	mmr_t	sh_xn_pi_sic_cmp_data_enable1_regval;
12264 		mmr_t	data_enable1 : 64;
12276 	mmr_t	sh_xn_pi_sic_cmp_data_enable2_regval;
12278 		mmr_t	data_enable2 : 64;
12283 	mmr_t	sh_xn_pi_sic_cmp_data_enable2_regval;
12285 		mmr_t	data_enable2 : 64;
12297 	mmr_t	sh_xn_pi_sic_cmp_data_enable3_regval;
12299 		mmr_t	data_enable3 : 64;
12304 	mmr_t	sh_xn_pi_sic_cmp_data_enable3_regval;
12306 		mmr_t	data_enable3 : 64;
12318 	mmr_t	sh_xn_ni0_iilb_cmp_exp_data0_regval;
12320 		mmr_t	data        : 64;
12325 	mmr_t	sh_xn_ni0_iilb_cmp_exp_data0_regval;
12327 		mmr_t	data        : 64;
12339 	mmr_t	sh_xn_ni0_iilb_cmp_exp_data1_regval;
12341 		mmr_t	data        : 64;
12346 	mmr_t	sh_xn_ni0_iilb_cmp_exp_data1_regval;
12348 		mmr_t	data        : 64;
12360 	mmr_t	sh_xn_ni0_iilb_cmp_enable0_regval;
12362 		mmr_t	enable      : 64;
12367 	mmr_t	sh_xn_ni0_iilb_cmp_enable0_regval;
12369 		mmr_t	enable      : 64;
12381 	mmr_t	sh_xn_ni0_iilb_cmp_enable1_regval;
12383 		mmr_t	enable      : 64;
12388 	mmr_t	sh_xn_ni0_iilb_cmp_enable1_regval;
12390 		mmr_t	enable      : 64;
12402 	mmr_t	sh_xn_ni0_pi_cmp_exp_data0_regval;
12404 		mmr_t	data        : 64;
12409 	mmr_t	sh_xn_ni0_pi_cmp_exp_data0_regval;
12411 		mmr_t	data        : 64;
12423 	mmr_t	sh_xn_ni0_pi_cmp_exp_data1_regval;
12425 		mmr_t	data        : 64;
12430 	mmr_t	sh_xn_ni0_pi_cmp_exp_data1_regval;
12432 		mmr_t	data        : 64;
12444 	mmr_t	sh_xn_ni0_pi_cmp_enable0_regval;
12446 		mmr_t	enable      : 64;
12451 	mmr_t	sh_xn_ni0_pi_cmp_enable0_regval;
12453 		mmr_t	enable      : 64;
12465 	mmr_t	sh_xn_ni0_pi_cmp_enable1_regval;
12467 		mmr_t	enable      : 64;
12472 	mmr_t	sh_xn_ni0_pi_cmp_enable1_regval;
12474 		mmr_t	enable      : 64;
12486 	mmr_t	sh_xn_ni0_md_cmp_exp_data0_regval;
12488 		mmr_t	data        : 64;
12493 	mmr_t	sh_xn_ni0_md_cmp_exp_data0_regval;
12495 		mmr_t	data        : 64;
12507 	mmr_t	sh_xn_ni0_md_cmp_exp_data1_regval;
12509 		mmr_t	data        : 64;
12514 	mmr_t	sh_xn_ni0_md_cmp_exp_data1_regval;
12516 		mmr_t	data        : 64;
12528 	mmr_t	sh_xn_ni0_md_cmp_enable0_regval;
12530 		mmr_t	enable      : 64;
12535 	mmr_t	sh_xn_ni0_md_cmp_enable0_regval;
12537 		mmr_t	enable      : 64;
12549 	mmr_t	sh_xn_ni0_md_cmp_enable1_regval;
12551 		mmr_t	enable      : 64;
12556 	mmr_t	sh_xn_ni0_md_cmp_enable1_regval;
12558 		mmr_t	enable      : 64;
12570 	mmr_t	sh_xn_ni0_ni_cmp_exp_data0_regval;
12572 		mmr_t	data        : 64;
12577 	mmr_t	sh_xn_ni0_ni_cmp_exp_data0_regval;
12579 		mmr_t	data        : 64;
12591 	mmr_t	sh_xn_ni0_ni_cmp_exp_data1_regval;
12593 		mmr_t	data        : 64;
12598 	mmr_t	sh_xn_ni0_ni_cmp_exp_data1_regval;
12600 		mmr_t	data        : 64;
12612 	mmr_t	sh_xn_ni0_ni_cmp_enable0_regval;
12614 		mmr_t	enable      : 64;
12619 	mmr_t	sh_xn_ni0_ni_cmp_enable0_regval;
12621 		mmr_t	enable      : 64;
12633 	mmr_t	sh_xn_ni0_ni_cmp_enable1_regval;
12635 		mmr_t	enable      : 64;
12640 	mmr_t	sh_xn_ni0_ni_cmp_enable1_regval;
12642 		mmr_t	enable      : 64;
12654 	mmr_t	sh_xn_ni0_llp_cmp_exp_data0_regval;
12656 		mmr_t	data        : 64;
12661 	mmr_t	sh_xn_ni0_llp_cmp_exp_data0_regval;
12663 		mmr_t	data        : 64;
12675 	mmr_t	sh_xn_ni0_llp_cmp_exp_data1_regval;
12677 		mmr_t	data        : 64;
12682 	mmr_t	sh_xn_ni0_llp_cmp_exp_data1_regval;
12684 		mmr_t	data        : 64;
12696 	mmr_t	sh_xn_ni0_llp_cmp_enable0_regval;
12698 		mmr_t	enable      : 64;
12703 	mmr_t	sh_xn_ni0_llp_cmp_enable0_regval;
12705 		mmr_t	enable      : 64;
12717 	mmr_t	sh_xn_ni0_llp_cmp_enable1_regval;
12719 		mmr_t	enable      : 64;
12724 	mmr_t	sh_xn_ni0_llp_cmp_enable1_regval;
12726 		mmr_t	enable      : 64;
12738 	mmr_t	sh_xn_ni1_iilb_cmp_exp_data0_regval;
12740 		mmr_t	data        : 64;
12745 	mmr_t	sh_xn_ni1_iilb_cmp_exp_data0_regval;
12747 		mmr_t	data        : 64;
12759 	mmr_t	sh_xn_ni1_iilb_cmp_exp_data1_regval;
12761 		mmr_t	data        : 64;
12766 	mmr_t	sh_xn_ni1_iilb_cmp_exp_data1_regval;
12768 		mmr_t	data        : 64;
12780 	mmr_t	sh_xn_ni1_iilb_cmp_enable0_regval;
12782 		mmr_t	enable      : 64;
12787 	mmr_t	sh_xn_ni1_iilb_cmp_enable0_regval;
12789 		mmr_t	enable      : 64;
12801 	mmr_t	sh_xn_ni1_iilb_cmp_enable1_regval;
12803 		mmr_t	enable      : 64;
12808 	mmr_t	sh_xn_ni1_iilb_cmp_enable1_regval;
12810 		mmr_t	enable      : 64;
12822 	mmr_t	sh_xn_ni1_pi_cmp_exp_data0_regval;
12824 		mmr_t	data        : 64;
12829 	mmr_t	sh_xn_ni1_pi_cmp_exp_data0_regval;
12831 		mmr_t	data        : 64;
12843 	mmr_t	sh_xn_ni1_pi_cmp_exp_data1_regval;
12845 		mmr_t	data        : 64;
12850 	mmr_t	sh_xn_ni1_pi_cmp_exp_data1_regval;
12852 		mmr_t	data        : 64;
12864 	mmr_t	sh_xn_ni1_pi_cmp_enable0_regval;
12866 		mmr_t	enable      : 64;
12871 	mmr_t	sh_xn_ni1_pi_cmp_enable0_regval;
12873 		mmr_t	enable      : 64;
12885 	mmr_t	sh_xn_ni1_pi_cmp_enable1_regval;
12887 		mmr_t	enable      : 64;
12892 	mmr_t	sh_xn_ni1_pi_cmp_enable1_regval;
12894 		mmr_t	enable      : 64;
12906 	mmr_t	sh_xn_ni1_md_cmp_exp_data0_regval;
12908 		mmr_t	data        : 64;
12913 	mmr_t	sh_xn_ni1_md_cmp_exp_data0_regval;
12915 		mmr_t	data        : 64;
12927 	mmr_t	sh_xn_ni1_md_cmp_exp_data1_regval;
12929 		mmr_t	data        : 64;
12934 	mmr_t	sh_xn_ni1_md_cmp_exp_data1_regval;
12936 		mmr_t	data        : 64;
12948 	mmr_t	sh_xn_ni1_md_cmp_enable0_regval;
12950 		mmr_t	enable      : 64;
12955 	mmr_t	sh_xn_ni1_md_cmp_enable0_regval;
12957 		mmr_t	enable      : 64;
12969 	mmr_t	sh_xn_ni1_md_cmp_enable1_regval;
12971 		mmr_t	enable      : 64;
12976 	mmr_t	sh_xn_ni1_md_cmp_enable1_regval;
12978 		mmr_t	enable      : 64;
12990 	mmr_t	sh_xn_ni1_ni_cmp_exp_data0_regval;
12992 		mmr_t	data        : 64;
12997 	mmr_t	sh_xn_ni1_ni_cmp_exp_data0_regval;
12999 		mmr_t	data        : 64;
13011 	mmr_t	sh_xn_ni1_ni_cmp_exp_data1_regval;
13013 		mmr_t	data        : 64;
13018 	mmr_t	sh_xn_ni1_ni_cmp_exp_data1_regval;
13020 		mmr_t	data        : 64;
13032 	mmr_t	sh_xn_ni1_ni_cmp_enable0_regval;
13034 		mmr_t	enable      : 64;
13039 	mmr_t	sh_xn_ni1_ni_cmp_enable0_regval;
13041 		mmr_t	enable      : 64;
13053 	mmr_t	sh_xn_ni1_ni_cmp_enable1_regval;
13055 		mmr_t	enable      : 64;
13060 	mmr_t	sh_xn_ni1_ni_cmp_enable1_regval;
13062 		mmr_t	enable      : 64;
13074 	mmr_t	sh_xn_ni1_llp_cmp_exp_data0_regval;
13076 		mmr_t	data        : 64;
13081 	mmr_t	sh_xn_ni1_llp_cmp_exp_data0_regval;
13083 		mmr_t	data        : 64;
13095 	mmr_t	sh_xn_ni1_llp_cmp_exp_data1_regval;
13097 		mmr_t	data        : 64;
13102 	mmr_t	sh_xn_ni1_llp_cmp_exp_data1_regval;
13104 		mmr_t	data        : 64;
13116 	mmr_t	sh_xn_ni1_llp_cmp_enable0_regval;
13118 		mmr_t	enable      : 64;
13123 	mmr_t	sh_xn_ni1_llp_cmp_enable0_regval;
13125 		mmr_t	enable      : 64;
13137 	mmr_t	sh_xn_ni1_llp_cmp_enable1_regval;
13139 		mmr_t	enable      : 64;
13144 	mmr_t	sh_xn_ni1_llp_cmp_enable1_regval;
13146 		mmr_t	enable      : 64;
13157 	mmr_t	sh_xnpi_ecc_inj_reg_regval;
13159 		mmr_t	byte0          : 8;
13160 		mmr_t	reserved_0     : 4;
13161 		mmr_t	data_1shot0    : 1;
13162 		mmr_t	data_cont0     : 1;
13163 		mmr_t	data_cb_1shot0 : 1;
13164 		mmr_t	data_cb_cont0  : 1;
13165 		mmr_t	byte1          : 8;
13166 		mmr_t	reserved_1     : 4;
13167 		mmr_t	data_1shot1    : 1;
13168 		mmr_t	data_cont1     : 1;
13169 		mmr_t	data_cb_1shot1 : 1;
13170 		mmr_t	data_cb_cont1  : 1;
13171 		mmr_t	byte2          : 8;
13172 		mmr_t	reserved_2     : 4;
13173 		mmr_t	data_1shot2    : 1;
13174 		mmr_t	data_cont2     : 1;
13175 		mmr_t	data_cb_1shot2 : 1;
13176 		mmr_t	data_cb_cont2  : 1;
13177 		mmr_t	byte3          : 8;
13178 		mmr_t	reserved_3     : 4;
13179 		mmr_t	data_1shot3    : 1;
13180 		mmr_t	data_cont3     : 1;
13181 		mmr_t	data_cb_1shot3 : 1;
13182 		mmr_t	data_cb_cont3  : 1;
13187 	mmr_t	sh_xnpi_ecc_inj_reg_regval;
13189 		mmr_t	data_cb_cont3  : 1;
13190 		mmr_t	data_cb_1shot3 : 1;
13191 		mmr_t	data_cont3     : 1;
13192 		mmr_t	data_1shot3    : 1;
13193 		mmr_t	reserved_3     : 4;
13194 		mmr_t	byte3          : 8;
13195 		mmr_t	data_cb_cont2  : 1;
13196 		mmr_t	data_cb_1shot2 : 1;
13197 		mmr_t	data_cont2     : 1;
13198 		mmr_t	data_1shot2    : 1;
13199 		mmr_t	reserved_2     : 4;
13200 		mmr_t	byte2          : 8;
13201 		mmr_t	data_cb_cont1  : 1;
13202 		mmr_t	data_cb_1shot1 : 1;
13203 		mmr_t	data_cont1     : 1;
13204 		mmr_t	data_1shot1    : 1;
13205 		mmr_t	reserved_1     : 4;
13206 		mmr_t	byte1          : 8;
13207 		mmr_t	data_cb_cont0  : 1;
13208 		mmr_t	data_cb_1shot0 : 1;
13209 		mmr_t	data_cont0     : 1;
13210 		mmr_t	data_1shot0    : 1;
13211 		mmr_t	reserved_0     : 4;
13212 		mmr_t	byte0          : 8;
13223 	mmr_t	sh_xnpi_ecc0_inj_mask_reg_regval;
13225 		mmr_t	mask_ecc0   : 64;
13230 	mmr_t	sh_xnpi_ecc0_inj_mask_reg_regval;
13232 		mmr_t	mask_ecc0   : 64;
13243 	mmr_t	sh_xnpi_ecc1_inj_mask_reg_regval;
13245 		mmr_t	mask_ecc1   : 64;
13250 	mmr_t	sh_xnpi_ecc1_inj_mask_reg_regval;
13252 		mmr_t	mask_ecc1   : 64;
13263 	mmr_t	sh_xnpi_ecc2_inj_mask_reg_regval;
13265 		mmr_t	mask_ecc2   : 64;
13270 	mmr_t	sh_xnpi_ecc2_inj_mask_reg_regval;
13272 		mmr_t	mask_ecc2   : 64;
13283 	mmr_t	sh_xnpi_ecc3_inj_mask_reg_regval;
13285 		mmr_t	mask_ecc3   : 64;
13290 	mmr_t	sh_xnpi_ecc3_inj_mask_reg_regval;
13292 		mmr_t	mask_ecc3   : 64;
13303 	mmr_t	sh_xnmd_ecc_inj_reg_regval;
13305 		mmr_t	byte0          : 8;
13306 		mmr_t	reserved_0     : 4;
13307 		mmr_t	data_1shot0    : 1;
13308 		mmr_t	data_cont0     : 1;
13309 		mmr_t	data_cb_1shot0 : 1;
13310 		mmr_t	data_cb_cont0  : 1;
13311 		mmr_t	byte1          : 8;
13312 		mmr_t	reserved_1     : 4;
13313 		mmr_t	data_1shot1    : 1;
13314 		mmr_t	data_cont1     : 1;
13315 		mmr_t	data_cb_1shot1 : 1;
13316 		mmr_t	data_cb_cont1  : 1;
13317 		mmr_t	byte2          : 8;
13318 		mmr_t	reserved_2     : 4;
13319 		mmr_t	data_1shot2    : 1;
13320 		mmr_t	data_cont2     : 1;
13321 		mmr_t	data_cb_1shot2 : 1;
13322 		mmr_t	data_cb_cont2  : 1;
13323 		mmr_t	byte3          : 8;
13324 		mmr_t	reserved_3     : 4;
13325 		mmr_t	data_1shot3    : 1;
13326 		mmr_t	data_cont3     : 1;
13327 		mmr_t	data_cb_1shot3 : 1;
13328 		mmr_t	data_cb_cont3  : 1;
13333 	mmr_t	sh_xnmd_ecc_inj_reg_regval;
13335 		mmr_t	data_cb_cont3  : 1;
13336 		mmr_t	data_cb_1shot3 : 1;
13337 		mmr_t	data_cont3     : 1;
13338 		mmr_t	data_1shot3    : 1;
13339 		mmr_t	reserved_3     : 4;
13340 		mmr_t	byte3          : 8;
13341 		mmr_t	data_cb_cont2  : 1;
13342 		mmr_t	data_cb_1shot2 : 1;
13343 		mmr_t	data_cont2     : 1;
13344 		mmr_t	data_1shot2    : 1;
13345 		mmr_t	reserved_2     : 4;
13346 		mmr_t	byte2          : 8;
13347 		mmr_t	data_cb_cont1  : 1;
13348 		mmr_t	data_cb_1shot1 : 1;
13349 		mmr_t	data_cont1     : 1;
13350 		mmr_t	data_1shot1    : 1;
13351 		mmr_t	reserved_1     : 4;
13352 		mmr_t	byte1          : 8;
13353 		mmr_t	data_cb_cont0  : 1;
13354 		mmr_t	data_cb_1shot0 : 1;
13355 		mmr_t	data_cont0     : 1;
13356 		mmr_t	data_1shot0    : 1;
13357 		mmr_t	reserved_0     : 4;
13358 		mmr_t	byte0          : 8;
13369 	mmr_t	sh_xnmd_ecc0_inj_mask_reg_regval;
13371 		mmr_t	mask_ecc0   : 64;
13376 	mmr_t	sh_xnmd_ecc0_inj_mask_reg_regval;
13378 		mmr_t	mask_ecc0   : 64;
13389 	mmr_t	sh_xnmd_ecc1_inj_mask_reg_regval;
13391 		mmr_t	mask_ecc1   : 64;
13396 	mmr_t	sh_xnmd_ecc1_inj_mask_reg_regval;
13398 		mmr_t	mask_ecc1   : 64;
13409 	mmr_t	sh_xnmd_ecc2_inj_mask_reg_regval;
13411 		mmr_t	mask_ecc2   : 64;
13416 	mmr_t	sh_xnmd_ecc2_inj_mask_reg_regval;
13418 		mmr_t	mask_ecc2   : 64;
13429 	mmr_t	sh_xnmd_ecc3_inj_mask_reg_regval;
13431 		mmr_t	mask_ecc3   : 64;
13436 	mmr_t	sh_xnmd_ecc3_inj_mask_reg_regval;
13438 		mmr_t	mask_ecc3   : 64;
13449 	mmr_t	sh_xnmd_ecc_err_report_regval;
13451 		mmr_t	ecc_disable0 : 1;
13452 		mmr_t	reserved_0   : 15;
13453 		mmr_t	ecc_disable1 : 1;
13454 		mmr_t	reserved_1   : 15;
13455 		mmr_t	ecc_disable2 : 1;
13456 		mmr_t	reserved_2   : 15;
13457 		mmr_t	ecc_disable3 : 1;
13458 		mmr_t	reserved_3   : 15;
13463 	mmr_t	sh_xnmd_ecc_err_report_regval;
13465 		mmr_t	reserved_3   : 15;
13466 		mmr_t	ecc_disable3 : 1;
13467 		mmr_t	reserved_2   : 15;
13468 		mmr_t	ecc_disable2 : 1;
13469 		mmr_t	reserved_1   : 15;
13470 		mmr_t	ecc_disable1 : 1;
13471 		mmr_t	reserved_0   : 15;
13472 		mmr_t	ecc_disable0 : 1;
13484 	mmr_t	sh_ni0_error_summary_1_regval;
13486 		mmr_t	overflow_fifo02_debit0        : 1;
13487 		mmr_t	overflow_fifo02_debit2        : 1;
13488 		mmr_t	overflow_fifo13_debit0        : 1;
13489 		mmr_t	overflow_fifo13_debit2        : 1;
13490 		mmr_t	overflow_fifo02_vc0_pop       : 1;
13491 		mmr_t	overflow_fifo02_vc2_pop       : 1;
13492 		mmr_t	overflow_fifo13_vc1_pop       : 1;
13493 		mmr_t	overflow_fifo13_vc3_pop       : 1;
13494 		mmr_t	overflow_fifo02_vc0_push      : 1;
13495 		mmr_t	overflow_fifo02_vc2_push      : 1;
13496 		mmr_t	overflow_fifo13_vc1_push      : 1;
13497 		mmr_t	overflow_fifo13_vc3_push      : 1;
13498 		mmr_t	overflow_fifo02_vc0_credit    : 1;
13499 		mmr_t	overflow_fifo02_vc2_credit    : 1;
13500 		mmr_t	overflow_fifo13_vc0_credit    : 1;
13501 		mmr_t	overflow_fifo13_vc2_credit    : 1;
13502 		mmr_t	overflow0_vc0_credit          : 1;
13503 		mmr_t	overflow1_vc0_credit          : 1;
13504 		mmr_t	overflow2_vc0_credit          : 1;
13505 		mmr_t	overflow0_vc2_credit          : 1;
13506 		mmr_t	overflow1_vc2_credit          : 1;
13507 		mmr_t	overflow2_vc2_credit          : 1;
13508 		mmr_t	overflow_pi_fifo_debit0       : 1;
13509 		mmr_t	overflow_pi_fifo_debit2       : 1;
13510 		mmr_t	overflow_iilb_fifo_debit0     : 1;
13511 		mmr_t	overflow_iilb_fifo_debit2     : 1;
13512 		mmr_t	overflow_md_fifo_debit0       : 1;
13513 		mmr_t	overflow_md_fifo_debit2       : 1;
13514 		mmr_t	overflow_ni_fifo_debit0       : 1;
13515 		mmr_t	overflow_ni_fifo_debit1       : 1;
13516 		mmr_t	overflow_ni_fifo_debit2       : 1;
13517 		mmr_t	overflow_ni_fifo_debit3       : 1;
13518 		mmr_t	overflow_pi_fifo_vc0_pop      : 1;
13519 		mmr_t	overflow_pi_fifo_vc2_pop      : 1;
13520 		mmr_t	overflow_iilb_fifo_vc0_pop    : 1;
13521 		mmr_t	overflow_iilb_fifo_vc2_pop    : 1;
13522 		mmr_t	overflow_md_fifo_vc0_pop      : 1;
13523 		mmr_t	overflow_md_fifo_vc2_pop      : 1;
13524 		mmr_t	overflow_ni_fifo_vc0_pop      : 1;
13525 		mmr_t	overflow_ni_fifo_vc2_pop      : 1;
13526 		mmr_t	overflow_pi_fifo_vc0_push     : 1;
13527 		mmr_t	overflow_pi_fifo_vc2_push     : 1;
13528 		mmr_t	overflow_iilb_fifo_vc0_push   : 1;
13529 		mmr_t	overflow_iilb_fifo_vc2_push   : 1;
13530 		mmr_t	overflow_md_fifo_vc0_push     : 1;
13531 		mmr_t	overflow_md_fifo_vc2_push     : 1;
13532 		mmr_t	overflow_pi_fifo_vc0_credit   : 1;
13533 		mmr_t	overflow_pi_fifo_vc2_credit   : 1;
13534 		mmr_t	overflow_iilb_fifo_vc0_credit : 1;
13535 		mmr_t	overflow_iilb_fifo_vc2_credit : 1;
13536 		mmr_t	overflow_md_fifo_vc0_credit   : 1;
13537 		mmr_t	overflow_md_fifo_vc2_credit   : 1;
13538 		mmr_t	overflow_ni_fifo_vc0_credit   : 1;
13539 		mmr_t	overflow_ni_fifo_vc1_credit   : 1;
13540 		mmr_t	overflow_ni_fifo_vc2_credit   : 1;
13541 		mmr_t	overflow_ni_fifo_vc3_credit   : 1;
13542 		mmr_t	tail_timeout_fifo02_vc0       : 1;
13543 		mmr_t	tail_timeout_fifo02_vc2       : 1;
13544 		mmr_t	tail_timeout_fifo13_vc1       : 1;
13545 		mmr_t	tail_timeout_fifo13_vc3       : 1;
13546 		mmr_t	tail_timeout_ni_vc0           : 1;
13547 		mmr_t	tail_timeout_ni_vc1           : 1;
13548 		mmr_t	tail_timeout_ni_vc2           : 1;
13549 		mmr_t	tail_timeout_ni_vc3           : 1;
13554 	mmr_t	sh_ni0_error_summary_1_regval;
13556 		mmr_t	tail_timeout_ni_vc3           : 1;
13557 		mmr_t	tail_timeout_ni_vc2           : 1;
13558 		mmr_t	tail_timeout_ni_vc1           : 1;
13559 		mmr_t	tail_timeout_ni_vc0           : 1;
13560 		mmr_t	tail_timeout_fifo13_vc3       : 1;
13561 		mmr_t	tail_timeout_fifo13_vc1       : 1;
13562 		mmr_t	tail_timeout_fifo02_vc2       : 1;
13563 		mmr_t	tail_timeout_fifo02_vc0       : 1;
13564 		mmr_t	overflow_ni_fifo_vc3_credit   : 1;
13565 		mmr_t	overflow_ni_fifo_vc2_credit   : 1;
13566 		mmr_t	overflow_ni_fifo_vc1_credit   : 1;
13567 		mmr_t	overflow_ni_fifo_vc0_credit   : 1;
13568 		mmr_t	overflow_md_fifo_vc2_credit   : 1;
13569 		mmr_t	overflow_md_fifo_vc0_credit   : 1;
13570 		mmr_t	overflow_iilb_fifo_vc2_credit : 1;
13571 		mmr_t	overflow_iilb_fifo_vc0_credit : 1;
13572 		mmr_t	overflow_pi_fifo_vc2_credit   : 1;
13573 		mmr_t	overflow_pi_fifo_vc0_credit   : 1;
13574 		mmr_t	overflow_md_fifo_vc2_push     : 1;
13575 		mmr_t	overflow_md_fifo_vc0_push     : 1;
13576 		mmr_t	overflow_iilb_fifo_vc2_push   : 1;
13577 		mmr_t	overflow_iilb_fifo_vc0_push   : 1;
13578 		mmr_t	overflow_pi_fifo_vc2_push     : 1;
13579 		mmr_t	overflow_pi_fifo_vc0_push     : 1;
13580 		mmr_t	overflow_ni_fifo_vc2_pop      : 1;
13581 		mmr_t	overflow_ni_fifo_vc0_pop      : 1;
13582 		mmr_t	overflow_md_fifo_vc2_pop      : 1;
13583 		mmr_t	overflow_md_fifo_vc0_pop      : 1;
13584 		mmr_t	overflow_iilb_fifo_vc2_pop    : 1;
13585 		mmr_t	overflow_iilb_fifo_vc0_pop    : 1;
13586 		mmr_t	overflow_pi_fifo_vc2_pop      : 1;
13587 		mmr_t	overflow_pi_fifo_vc0_pop      : 1;
13588 		mmr_t	overflow_ni_fifo_debit3       : 1;
13589 		mmr_t	overflow_ni_fifo_debit2       : 1;
13590 		mmr_t	overflow_ni_fifo_debit1       : 1;
13591 		mmr_t	overflow_ni_fifo_debit0       : 1;
13592 		mmr_t	overflow_md_fifo_debit2       : 1;
13593 		mmr_t	overflow_md_fifo_debit0       : 1;
13594 		mmr_t	overflow_iilb_fifo_debit2     : 1;
13595 		mmr_t	overflow_iilb_fifo_debit0     : 1;
13596 		mmr_t	overflow_pi_fifo_debit2       : 1;
13597 		mmr_t	overflow_pi_fifo_debit0       : 1;
13598 		mmr_t	overflow2_vc2_credit          : 1;
13599 		mmr_t	overflow1_vc2_credit          : 1;
13600 		mmr_t	overflow0_vc2_credit          : 1;
13601 		mmr_t	overflow2_vc0_credit          : 1;
13602 		mmr_t	overflow1_vc0_credit          : 1;
13603 		mmr_t	overflow0_vc0_credit          : 1;
13604 		mmr_t	overflow_fifo13_vc2_credit    : 1;
13605 		mmr_t	overflow_fifo13_vc0_credit    : 1;
13606 		mmr_t	overflow_fifo02_vc2_credit    : 1;
13607 		mmr_t	overflow_fifo02_vc0_credit    : 1;
13608 		mmr_t	overflow_fifo13_vc3_push      : 1;
13609 		mmr_t	overflow_fifo13_vc1_push      : 1;
13610 		mmr_t	overflow_fifo02_vc2_push      : 1;
13611 		mmr_t	overflow_fifo02_vc0_push      : 1;
13612 		mmr_t	overflow_fifo13_vc3_pop       : 1;
13613 		mmr_t	overflow_fifo13_vc1_pop       : 1;
13614 		mmr_t	overflow_fifo02_vc2_pop       : 1;
13615 		mmr_t	overflow_fifo02_vc0_pop       : 1;
13616 		mmr_t	overflow_fifo13_debit2        : 1;
13617 		mmr_t	overflow_fifo13_debit0        : 1;
13618 		mmr_t	overflow_fifo02_debit2        : 1;
13619 		mmr_t	overflow_fifo02_debit0        : 1;
13631 	mmr_t	sh_ni0_error_summary_2_regval;
13633 		mmr_t	illegal_vcni                   : 1;
13634 		mmr_t	illegal_vcpi                   : 1;
13635 		mmr_t	illegal_vcmd                   : 1;
13636 		mmr_t	illegal_vciilb                 : 1;
13637 		mmr_t	underflow_fifo02_vc0_pop       : 1;
13638 		mmr_t	underflow_fifo02_vc2_pop       : 1;
13639 		mmr_t	underflow_fifo13_vc1_pop       : 1;
13640 		mmr_t	underflow_fifo13_vc3_pop       : 1;
13641 		mmr_t	underflow_fifo02_vc0_push      : 1;
13642 		mmr_t	underflow_fifo02_vc2_push      : 1;
13643 		mmr_t	underflow_fifo13_vc1_push      : 1;
13644 		mmr_t	underflow_fifo13_vc3_push      : 1;
13645 		mmr_t	underflow_fifo02_vc0_credit    : 1;
13646 		mmr_t	underflow_fifo02_vc2_credit    : 1;
13647 		mmr_t	underflow_fifo13_vc0_credit    : 1;
13648 		mmr_t	underflow_fifo13_vc2_credit    : 1;
13649 		mmr_t	underflow0_vc0_credit          : 1;
13650 		mmr_t	underflow1_vc0_credit          : 1;
13651 		mmr_t	underflow2_vc0_credit          : 1;
13652 		mmr_t	underflow0_vc2_credit          : 1;
13653 		mmr_t	underflow1_vc2_credit          : 1;
13654 		mmr_t	underflow2_vc2_credit          : 1;
13655 		mmr_t	reserved_0                     : 10;
13656 		mmr_t	underflow_pi_fifo_vc0_pop      : 1;
13657 		mmr_t	underflow_pi_fifo_vc2_pop      : 1;
13658 		mmr_t	underflow_iilb_fifo_vc0_pop    : 1;
13659 		mmr_t	underflow_iilb_fifo_vc2_pop    : 1;
13660 		mmr_t	underflow_md_fifo_vc0_pop      : 1;
13661 		mmr_t	underflow_md_fifo_vc2_pop      : 1;
13662 		mmr_t	underflow_ni_fifo_vc0_pop      : 1;
13663 		mmr_t	underflow_ni_fifo_vc2_pop      : 1;
13664 		mmr_t	underflow_pi_fifo_vc0_push     : 1;
13665 		mmr_t	underflow_pi_fifo_vc2_push     : 1;
13666 		mmr_t	underflow_iilb_fifo_vc0_push   : 1;
13667 		mmr_t	underflow_iilb_fifo_vc2_push   : 1;
13668 		mmr_t	underflow_md_fifo_vc0_push     : 1;
13669 		mmr_t	underflow_md_fifo_vc2_push     : 1;
13670 		mmr_t	underflow_pi_fifo_vc0_credit   : 1;
13671 		mmr_t	underflow_pi_fifo_vc2_credit   : 1;
13672 		mmr_t	underflow_iilb_fifo_vc0_credit : 1;
13673 		mmr_t	underflow_iilb_fifo_vc2_credit : 1;
13674 		mmr_t	underflow_md_fifo_vc0_credit   : 1;
13675 		mmr_t	underflow_md_fifo_vc2_credit   : 1;
13676 		mmr_t	underflow_ni_fifo_vc0_credit   : 1;
13677 		mmr_t	underflow_ni_fifo_vc1_credit   : 1;
13678 		mmr_t	underflow_ni_fifo_vc2_credit   : 1;
13679 		mmr_t	underflow_ni_fifo_vc3_credit   : 1;
13680 		mmr_t	llp_deadlock_vc0               : 1;
13681 		mmr_t	llp_deadlock_vc1               : 1;
13682 		mmr_t	llp_deadlock_vc2               : 1;
13683 		mmr_t	llp_deadlock_vc3               : 1;
13684 		mmr_t	chiplet_nomatch                : 1;
13685 		mmr_t	lut_read_error                 : 1;
13686 		mmr_t	retry_timeout_error            : 1;
13687 		mmr_t	reserved_1                     : 1;
13692 	mmr_t	sh_ni0_error_summary_2_regval;
13694 		mmr_t	reserved_1                     : 1;
13695 		mmr_t	retry_timeout_error            : 1;
13696 		mmr_t	lut_read_error                 : 1;
13697 		mmr_t	chiplet_nomatch                : 1;
13698 		mmr_t	llp_deadlock_vc3               : 1;
13699 		mmr_t	llp_deadlock_vc2               : 1;
13700 		mmr_t	llp_deadlock_vc1               : 1;
13701 		mmr_t	llp_deadlock_vc0               : 1;
13702 		mmr_t	underflow_ni_fifo_vc3_credit   : 1;
13703 		mmr_t	underflow_ni_fifo_vc2_credit   : 1;
13704 		mmr_t	underflow_ni_fifo_vc1_credit   : 1;
13705 		mmr_t	underflow_ni_fifo_vc0_credit   : 1;
13706 		mmr_t	underflow_md_fifo_vc2_credit   : 1;
13707 		mmr_t	underflow_md_fifo_vc0_credit   : 1;
13708 		mmr_t	underflow_iilb_fifo_vc2_credit : 1;
13709 		mmr_t	underflow_iilb_fifo_vc0_credit : 1;
13710 		mmr_t	underflow_pi_fifo_vc2_credit   : 1;
13711 		mmr_t	underflow_pi_fifo_vc0_credit   : 1;
13712 		mmr_t	underflow_md_fifo_vc2_push     : 1;
13713 		mmr_t	underflow_md_fifo_vc0_push     : 1;
13714 		mmr_t	underflow_iilb_fifo_vc2_push   : 1;
13715 		mmr_t	underflow_iilb_fifo_vc0_push   : 1;
13716 		mmr_t	underflow_pi_fifo_vc2_push     : 1;
13717 		mmr_t	underflow_pi_fifo_vc0_push     : 1;
13718 		mmr_t	underflow_ni_fifo_vc2_pop      : 1;
13719 		mmr_t	underflow_ni_fifo_vc0_pop      : 1;
13720 		mmr_t	underflow_md_fifo_vc2_pop      : 1;
13721 		mmr_t	underflow_md_fifo_vc0_pop      : 1;
13722 		mmr_t	underflow_iilb_fifo_vc2_pop    : 1;
13723 		mmr_t	underflow_iilb_fifo_vc0_pop    : 1;
13724 		mmr_t	underflow_pi_fifo_vc2_pop      : 1;
13725 		mmr_t	underflow_pi_fifo_vc0_pop      : 1;
13726 		mmr_t	reserved_0                     : 10;
13727 		mmr_t	underflow2_vc2_credit          : 1;
13728 		mmr_t	underflow1_vc2_credit          : 1;
13729 		mmr_t	underflow0_vc2_credit          : 1;
13730 		mmr_t	underflow2_vc0_credit          : 1;
13731 		mmr_t	underflow1_vc0_credit          : 1;
13732 		mmr_t	underflow0_vc0_credit          : 1;
13733 		mmr_t	underflow_fifo13_vc2_credit    : 1;
13734 		mmr_t	underflow_fifo13_vc0_credit    : 1;
13735 		mmr_t	underflow_fifo02_vc2_credit    : 1;
13736 		mmr_t	underflow_fifo02_vc0_credit    : 1;
13737 		mmr_t	underflow_fifo13_vc3_push      : 1;
13738 		mmr_t	underflow_fifo13_vc1_push      : 1;
13739 		mmr_t	underflow_fifo02_vc2_push      : 1;
13740 		mmr_t	underflow_fifo02_vc0_push      : 1;
13741 		mmr_t	underflow_fifo13_vc3_pop       : 1;
13742 		mmr_t	underflow_fifo13_vc1_pop       : 1;
13743 		mmr_t	underflow_fifo02_vc2_pop       : 1;
13744 		mmr_t	underflow_fifo02_vc0_pop       : 1;
13745 		mmr_t	illegal_vciilb                 : 1;
13746 		mmr_t	illegal_vcmd                   : 1;
13747 		mmr_t	illegal_vcpi                   : 1;
13748 		mmr_t	illegal_vcni                   : 1;
13760 	mmr_t	sh_ni0_error_overflow_1_regval;
13762 		mmr_t	overflow_fifo02_debit0        : 1;
13763 		mmr_t	overflow_fifo02_debit2        : 1;
13764 		mmr_t	overflow_fifo13_debit0        : 1;
13765 		mmr_t	overflow_fifo13_debit2        : 1;
13766 		mmr_t	overflow_fifo02_vc0_pop       : 1;
13767 		mmr_t	overflow_fifo02_vc2_pop       : 1;
13768 		mmr_t	overflow_fifo13_vc1_pop       : 1;
13769 		mmr_t	overflow_fifo13_vc3_pop       : 1;
13770 		mmr_t	overflow_fifo02_vc0_push      : 1;
13771 		mmr_t	overflow_fifo02_vc2_push      : 1;
13772 		mmr_t	overflow_fifo13_vc1_push      : 1;
13773 		mmr_t	overflow_fifo13_vc3_push      : 1;
13774 		mmr_t	overflow_fifo02_vc0_credit    : 1;
13775 		mmr_t	overflow_fifo02_vc2_credit    : 1;
13776 		mmr_t	overflow_fifo13_vc0_credit    : 1;
13777 		mmr_t	overflow_fifo13_vc2_credit    : 1;
13778 		mmr_t	overflow0_vc0_credit          : 1;
13779 		mmr_t	overflow1_vc0_credit          : 1;
13780 		mmr_t	overflow2_vc0_credit          : 1;
13781 		mmr_t	overflow0_vc2_credit          : 1;
13782 		mmr_t	overflow1_vc2_credit          : 1;
13783 		mmr_t	overflow2_vc2_credit          : 1;
13784 		mmr_t	overflow_pi_fifo_debit0       : 1;
13785 		mmr_t	overflow_pi_fifo_debit2       : 1;
13786 		mmr_t	overflow_iilb_fifo_debit0     : 1;
13787 		mmr_t	overflow_iilb_fifo_debit2     : 1;
13788 		mmr_t	overflow_md_fifo_debit0       : 1;
13789 		mmr_t	overflow_md_fifo_debit2       : 1;
13790 		mmr_t	overflow_ni_fifo_debit0       : 1;
13791 		mmr_t	overflow_ni_fifo_debit1       : 1;
13792 		mmr_t	overflow_ni_fifo_debit2       : 1;
13793 		mmr_t	overflow_ni_fifo_debit3       : 1;
13794 		mmr_t	overflow_pi_fifo_vc0_pop      : 1;
13795 		mmr_t	overflow_pi_fifo_vc2_pop      : 1;
13796 		mmr_t	overflow_iilb_fifo_vc0_pop    : 1;
13797 		mmr_t	overflow_iilb_fifo_vc2_pop    : 1;
13798 		mmr_t	overflow_md_fifo_vc0_pop      : 1;
13799 		mmr_t	overflow_md_fifo_vc2_pop      : 1;
13800 		mmr_t	overflow_ni_fifo_vc0_pop      : 1;
13801 		mmr_t	overflow_ni_fifo_vc2_pop      : 1;
13802 		mmr_t	overflow_pi_fifo_vc0_push     : 1;
13803 		mmr_t	overflow_pi_fifo_vc2_push     : 1;
13804 		mmr_t	overflow_iilb_fifo_vc0_push   : 1;
13805 		mmr_t	overflow_iilb_fifo_vc2_push   : 1;
13806 		mmr_t	overflow_md_fifo_vc0_push     : 1;
13807 		mmr_t	overflow_md_fifo_vc2_push     : 1;
13808 		mmr_t	overflow_pi_fifo_vc0_credit   : 1;
13809 		mmr_t	overflow_pi_fifo_vc2_credit   : 1;
13810 		mmr_t	overflow_iilb_fifo_vc0_credit : 1;
13811 		mmr_t	overflow_iilb_fifo_vc2_credit : 1;
13812 		mmr_t	overflow_md_fifo_vc0_credit   : 1;
13813 		mmr_t	overflow_md_fifo_vc2_credit   : 1;
13814 		mmr_t	overflow_ni_fifo_vc0_credit   : 1;
13815 		mmr_t	overflow_ni_fifo_vc1_credit   : 1;
13816 		mmr_t	overflow_ni_fifo_vc2_credit   : 1;
13817 		mmr_t	overflow_ni_fifo_vc3_credit   : 1;
13818 		mmr_t	tail_timeout_fifo02_vc0       : 1;
13819 		mmr_t	tail_timeout_fifo02_vc2       : 1;
13820 		mmr_t	tail_timeout_fifo13_vc1       : 1;
13821 		mmr_t	tail_timeout_fifo13_vc3       : 1;
13822 		mmr_t	tail_timeout_ni_vc0           : 1;
13823 		mmr_t	tail_timeout_ni_vc1           : 1;
13824 		mmr_t	tail_timeout_ni_vc2           : 1;
13825 		mmr_t	tail_timeout_ni_vc3           : 1;
13830 	mmr_t	sh_ni0_error_overflow_1_regval;
13832 		mmr_t	tail_timeout_ni_vc3           : 1;
13833 		mmr_t	tail_timeout_ni_vc2           : 1;
13834 		mmr_t	tail_timeout_ni_vc1           : 1;
13835 		mmr_t	tail_timeout_ni_vc0           : 1;
13836 		mmr_t	tail_timeout_fifo13_vc3       : 1;
13837 		mmr_t	tail_timeout_fifo13_vc1       : 1;
13838 		mmr_t	tail_timeout_fifo02_vc2       : 1;
13839 		mmr_t	tail_timeout_fifo02_vc0       : 1;
13840 		mmr_t	overflow_ni_fifo_vc3_credit   : 1;
13841 		mmr_t	overflow_ni_fifo_vc2_credit   : 1;
13842 		mmr_t	overflow_ni_fifo_vc1_credit   : 1;
13843 		mmr_t	overflow_ni_fifo_vc0_credit   : 1;
13844 		mmr_t	overflow_md_fifo_vc2_credit   : 1;
13845 		mmr_t	overflow_md_fifo_vc0_credit   : 1;
13846 		mmr_t	overflow_iilb_fifo_vc2_credit : 1;
13847 		mmr_t	overflow_iilb_fifo_vc0_credit : 1;
13848 		mmr_t	overflow_pi_fifo_vc2_credit   : 1;
13849 		mmr_t	overflow_pi_fifo_vc0_credit   : 1;
13850 		mmr_t	overflow_md_fifo_vc2_push     : 1;
13851 		mmr_t	overflow_md_fifo_vc0_push     : 1;
13852 		mmr_t	overflow_iilb_fifo_vc2_push   : 1;
13853 		mmr_t	overflow_iilb_fifo_vc0_push   : 1;
13854 		mmr_t	overflow_pi_fifo_vc2_push     : 1;
13855 		mmr_t	overflow_pi_fifo_vc0_push     : 1;
13856 		mmr_t	overflow_ni_fifo_vc2_pop      : 1;
13857 		mmr_t	overflow_ni_fifo_vc0_pop      : 1;
13858 		mmr_t	overflow_md_fifo_vc2_pop      : 1;
13859 		mmr_t	overflow_md_fifo_vc0_pop      : 1;
13860 		mmr_t	overflow_iilb_fifo_vc2_pop    : 1;
13861 		mmr_t	overflow_iilb_fifo_vc0_pop    : 1;
13862 		mmr_t	overflow_pi_fifo_vc2_pop      : 1;
13863 		mmr_t	overflow_pi_fifo_vc0_pop      : 1;
13864 		mmr_t	overflow_ni_fifo_debit3       : 1;
13865 		mmr_t	overflow_ni_fifo_debit2       : 1;
13866 		mmr_t	overflow_ni_fifo_debit1       : 1;
13867 		mmr_t	overflow_ni_fifo_debit0       : 1;
13868 		mmr_t	overflow_md_fifo_debit2       : 1;
13869 		mmr_t	overflow_md_fifo_debit0       : 1;
13870 		mmr_t	overflow_iilb_fifo_debit2     : 1;
13871 		mmr_t	overflow_iilb_fifo_debit0     : 1;
13872 		mmr_t	overflow_pi_fifo_debit2       : 1;
13873 		mmr_t	overflow_pi_fifo_debit0       : 1;
13874 		mmr_t	overflow2_vc2_credit          : 1;
13875 		mmr_t	overflow1_vc2_credit          : 1;
13876 		mmr_t	overflow0_vc2_credit          : 1;
13877 		mmr_t	overflow2_vc0_credit          : 1;
13878 		mmr_t	overflow1_vc0_credit          : 1;
13879 		mmr_t	overflow0_vc0_credit          : 1;
13880 		mmr_t	overflow_fifo13_vc2_credit    : 1;
13881 		mmr_t	overflow_fifo13_vc0_credit    : 1;
13882 		mmr_t	overflow_fifo02_vc2_credit    : 1;
13883 		mmr_t	overflow_fifo02_vc0_credit    : 1;
13884 		mmr_t	overflow_fifo13_vc3_push      : 1;
13885 		mmr_t	overflow_fifo13_vc1_push      : 1;
13886 		mmr_t	overflow_fifo02_vc2_push      : 1;
13887 		mmr_t	overflow_fifo02_vc0_push      : 1;
13888 		mmr_t	overflow_fifo13_vc3_pop       : 1;
13889 		mmr_t	overflow_fifo13_vc1_pop       : 1;
13890 		mmr_t	overflow_fifo02_vc2_pop       : 1;
13891 		mmr_t	overflow_fifo02_vc0_pop       : 1;
13892 		mmr_t	overflow_fifo13_debit2        : 1;
13893 		mmr_t	overflow_fifo13_debit0        : 1;
13894 		mmr_t	overflow_fifo02_debit2        : 1;
13895 		mmr_t	overflow_fifo02_debit0        : 1;
13907 	mmr_t	sh_ni0_error_overflow_2_regval;
13909 		mmr_t	illegal_vcni                   : 1;
13910 		mmr_t	illegal_vcpi                   : 1;
13911 		mmr_t	illegal_vcmd                   : 1;
13912 		mmr_t	illegal_vciilb                 : 1;
13913 		mmr_t	underflow_fifo02_vc0_pop       : 1;
13914 		mmr_t	underflow_fifo02_vc2_pop       : 1;
13915 		mmr_t	underflow_fifo13_vc1_pop       : 1;
13916 		mmr_t	underflow_fifo13_vc3_pop       : 1;
13917 		mmr_t	underflow_fifo02_vc0_push      : 1;
13918 		mmr_t	underflow_fifo02_vc2_push      : 1;
13919 		mmr_t	underflow_fifo13_vc1_push      : 1;
13920 		mmr_t	underflow_fifo13_vc3_push      : 1;
13921 		mmr_t	underflow_fifo02_vc0_credit    : 1;
13922 		mmr_t	underflow_fifo02_vc2_credit    : 1;
13923 		mmr_t	underflow_fifo13_vc0_credit    : 1;
13924 		mmr_t	underflow_fifo13_vc2_credit    : 1;
13925 		mmr_t	underflow0_vc0_credit          : 1;
13926 		mmr_t	underflow1_vc0_credit          : 1;
13927 		mmr_t	underflow2_vc0_credit          : 1;
13928 		mmr_t	underflow0_vc2_credit          : 1;
13929 		mmr_t	underflow1_vc2_credit          : 1;
13930 		mmr_t	underflow2_vc2_credit          : 1;
13931 		mmr_t	reserved_0                     : 10;
13932 		mmr_t	underflow_pi_fifo_vc0_pop      : 1;
13933 		mmr_t	underflow_pi_fifo_vc2_pop      : 1;
13934 		mmr_t	underflow_iilb_fifo_vc0_pop    : 1;
13935 		mmr_t	underflow_iilb_fifo_vc2_pop    : 1;
13936 		mmr_t	underflow_md_fifo_vc0_pop      : 1;
13937 		mmr_t	underflow_md_fifo_vc2_pop      : 1;
13938 		mmr_t	underflow_ni_fifo_vc0_pop      : 1;
13939 		mmr_t	underflow_ni_fifo_vc2_pop      : 1;
13940 		mmr_t	underflow_pi_fifo_vc0_push     : 1;
13941 		mmr_t	underflow_pi_fifo_vc2_push     : 1;
13942 		mmr_t	underflow_iilb_fifo_vc0_push   : 1;
13943 		mmr_t	underflow_iilb_fifo_vc2_push   : 1;
13944 		mmr_t	underflow_md_fifo_vc0_push     : 1;
13945 		mmr_t	underflow_md_fifo_vc2_push     : 1;
13946 		mmr_t	underflow_pi_fifo_vc0_credit   : 1;
13947 		mmr_t	underflow_pi_fifo_vc2_credit   : 1;
13948 		mmr_t	underflow_iilb_fifo_vc0_credit : 1;
13949 		mmr_t	underflow_iilb_fifo_vc2_credit : 1;
13950 		mmr_t	underflow_md_fifo_vc0_credit   : 1;
13951 		mmr_t	underflow_md_fifo_vc2_credit   : 1;
13952 		mmr_t	underflow_ni_fifo_vc0_credit   : 1;
13953 		mmr_t	underflow_ni_fifo_vc1_credit   : 1;
13954 		mmr_t	underflow_ni_fifo_vc2_credit   : 1;
13955 		mmr_t	underflow_ni_fifo_vc3_credit   : 1;
13956 		mmr_t	llp_deadlock_vc0               : 1;
13957 		mmr_t	llp_deadlock_vc1               : 1;
13958 		mmr_t	llp_deadlock_vc2               : 1;
13959 		mmr_t	llp_deadlock_vc3               : 1;
13960 		mmr_t	chiplet_nomatch                : 1;
13961 		mmr_t	lut_read_error                 : 1;
13962 		mmr_t	retry_timeout_error            : 1;
13963 		mmr_t	reserved_1                     : 1;
13968 	mmr_t	sh_ni0_error_overflow_2_regval;
13970 		mmr_t	reserved_1                     : 1;
13971 		mmr_t	retry_timeout_error            : 1;
13972 		mmr_t	lut_read_error                 : 1;
13973 		mmr_t	chiplet_nomatch                : 1;
13974 		mmr_t	llp_deadlock_vc3               : 1;
13975 		mmr_t	llp_deadlock_vc2               : 1;
13976 		mmr_t	llp_deadlock_vc1               : 1;
13977 		mmr_t	llp_deadlock_vc0               : 1;
13978 		mmr_t	underflow_ni_fifo_vc3_credit   : 1;
13979 		mmr_t	underflow_ni_fifo_vc2_credit   : 1;
13980 		mmr_t	underflow_ni_fifo_vc1_credit   : 1;
13981 		mmr_t	underflow_ni_fifo_vc0_credit   : 1;
13982 		mmr_t	underflow_md_fifo_vc2_credit   : 1;
13983 		mmr_t	underflow_md_fifo_vc0_credit   : 1;
13984 		mmr_t	underflow_iilb_fifo_vc2_credit : 1;
13985 		mmr_t	underflow_iilb_fifo_vc0_credit : 1;
13986 		mmr_t	underflow_pi_fifo_vc2_credit   : 1;
13987 		mmr_t	underflow_pi_fifo_vc0_credit   : 1;
13988 		mmr_t	underflow_md_fifo_vc2_push     : 1;
13989 		mmr_t	underflow_md_fifo_vc0_push     : 1;
13990 		mmr_t	underflow_iilb_fifo_vc2_push   : 1;
13991 		mmr_t	underflow_iilb_fifo_vc0_push   : 1;
13992 		mmr_t	underflow_pi_fifo_vc2_push     : 1;
13993 		mmr_t	underflow_pi_fifo_vc0_push     : 1;
13994 		mmr_t	underflow_ni_fifo_vc2_pop      : 1;
13995 		mmr_t	underflow_ni_fifo_vc0_pop      : 1;
13996 		mmr_t	underflow_md_fifo_vc2_pop      : 1;
13997 		mmr_t	underflow_md_fifo_vc0_pop      : 1;
13998 		mmr_t	underflow_iilb_fifo_vc2_pop    : 1;
13999 		mmr_t	underflow_iilb_fifo_vc0_pop    : 1;
14000 		mmr_t	underflow_pi_fifo_vc2_pop      : 1;
14001 		mmr_t	underflow_pi_fifo_vc0_pop      : 1;
14002 		mmr_t	reserved_0                     : 10;
14003 		mmr_t	underflow2_vc2_credit          : 1;
14004 		mmr_t	underflow1_vc2_credit          : 1;
14005 		mmr_t	underflow0_vc2_credit          : 1;
14006 		mmr_t	underflow2_vc0_credit          : 1;
14007 		mmr_t	underflow1_vc0_credit          : 1;
14008 		mmr_t	underflow0_vc0_credit          : 1;
14009 		mmr_t	underflow_fifo13_vc2_credit    : 1;
14010 		mmr_t	underflow_fifo13_vc0_credit    : 1;
14011 		mmr_t	underflow_fifo02_vc2_credit    : 1;
14012 		mmr_t	underflow_fifo02_vc0_credit    : 1;
14013 		mmr_t	underflow_fifo13_vc3_push      : 1;
14014 		mmr_t	underflow_fifo13_vc1_push      : 1;
14015 		mmr_t	underflow_fifo02_vc2_push      : 1;
14016 		mmr_t	underflow_fifo02_vc0_push      : 1;
14017 		mmr_t	underflow_fifo13_vc3_pop       : 1;
14018 		mmr_t	underflow_fifo13_vc1_pop       : 1;
14019 		mmr_t	underflow_fifo02_vc2_pop       : 1;
14020 		mmr_t	underflow_fifo02_vc0_pop       : 1;
14021 		mmr_t	illegal_vciilb                 : 1;
14022 		mmr_t	illegal_vcmd                   : 1;
14023 		mmr_t	illegal_vcpi                   : 1;
14024 		mmr_t	illegal_vcni                   : 1;
14036 	mmr_t	sh_ni0_error_mask_1_regval;
14038 		mmr_t	overflow_fifo02_debit0        : 1;
14039 		mmr_t	overflow_fifo02_debit2        : 1;
14040 		mmr_t	overflow_fifo13_debit0        : 1;
14041 		mmr_t	overflow_fifo13_debit2        : 1;
14042 		mmr_t	overflow_fifo02_vc0_pop       : 1;
14043 		mmr_t	overflow_fifo02_vc2_pop       : 1;
14044 		mmr_t	overflow_fifo13_vc1_pop       : 1;
14045 		mmr_t	overflow_fifo13_vc3_pop       : 1;
14046 		mmr_t	overflow_fifo02_vc0_push      : 1;
14047 		mmr_t	overflow_fifo02_vc2_push      : 1;
14048 		mmr_t	overflow_fifo13_vc1_push      : 1;
14049 		mmr_t	overflow_fifo13_vc3_push      : 1;
14050 		mmr_t	overflow_fifo02_vc0_credit    : 1;
14051 		mmr_t	overflow_fifo02_vc2_credit    : 1;
14052 		mmr_t	overflow_fifo13_vc0_credit    : 1;
14053 		mmr_t	overflow_fifo13_vc2_credit    : 1;
14054 		mmr_t	overflow0_vc0_credit          : 1;
14055 		mmr_t	overflow1_vc0_credit          : 1;
14056 		mmr_t	overflow2_vc0_credit          : 1;
14057 		mmr_t	overflow0_vc2_credit          : 1;
14058 		mmr_t	overflow1_vc2_credit          : 1;
14059 		mmr_t	overflow2_vc2_credit          : 1;
14060 		mmr_t	overflow_pi_fifo_debit0       : 1;
14061 		mmr_t	overflow_pi_fifo_debit2       : 1;
14062 		mmr_t	overflow_iilb_fifo_debit0     : 1;
14063 		mmr_t	overflow_iilb_fifo_debit2     : 1;
14064 		mmr_t	overflow_md_fifo_debit0       : 1;
14065 		mmr_t	overflow_md_fifo_debit2       : 1;
14066 		mmr_t	overflow_ni_fifo_debit0       : 1;
14067 		mmr_t	overflow_ni_fifo_debit1       : 1;
14068 		mmr_t	overflow_ni_fifo_debit2       : 1;
14069 		mmr_t	overflow_ni_fifo_debit3       : 1;
14070 		mmr_t	overflow_pi_fifo_vc0_pop      : 1;
14071 		mmr_t	overflow_pi_fifo_vc2_pop      : 1;
14072 		mmr_t	overflow_iilb_fifo_vc0_pop    : 1;
14073 		mmr_t	overflow_iilb_fifo_vc2_pop    : 1;
14074 		mmr_t	overflow_md_fifo_vc0_pop      : 1;
14075 		mmr_t	overflow_md_fifo_vc2_pop      : 1;
14076 		mmr_t	overflow_ni_fifo_vc0_pop      : 1;
14077 		mmr_t	overflow_ni_fifo_vc2_pop      : 1;
14078 		mmr_t	overflow_pi_fifo_vc0_push     : 1;
14079 		mmr_t	overflow_pi_fifo_vc2_push     : 1;
14080 		mmr_t	overflow_iilb_fifo_vc0_push   : 1;
14081 		mmr_t	overflow_iilb_fifo_vc2_push   : 1;
14082 		mmr_t	overflow_md_fifo_vc0_push     : 1;
14083 		mmr_t	overflow_md_fifo_vc2_push     : 1;
14084 		mmr_t	overflow_pi_fifo_vc0_credit   : 1;
14085 		mmr_t	overflow_pi_fifo_vc2_credit   : 1;
14086 		mmr_t	overflow_iilb_fifo_vc0_credit : 1;
14087 		mmr_t	overflow_iilb_fifo_vc2_credit : 1;
14088 		mmr_t	overflow_md_fifo_vc0_credit   : 1;
14089 		mmr_t	overflow_md_fifo_vc2_credit   : 1;
14090 		mmr_t	overflow_ni_fifo_vc0_credit   : 1;
14091 		mmr_t	overflow_ni_fifo_vc1_credit   : 1;
14092 		mmr_t	overflow_ni_fifo_vc2_credit   : 1;
14093 		mmr_t	overflow_ni_fifo_vc3_credit   : 1;
14094 		mmr_t	tail_timeout_fifo02_vc0       : 1;
14095 		mmr_t	tail_timeout_fifo02_vc2       : 1;
14096 		mmr_t	tail_timeout_fifo13_vc1       : 1;
14097 		mmr_t	tail_timeout_fifo13_vc3       : 1;
14098 		mmr_t	tail_timeout_ni_vc0           : 1;
14099 		mmr_t	tail_timeout_ni_vc1           : 1;
14100 		mmr_t	tail_timeout_ni_vc2           : 1;
14101 		mmr_t	tail_timeout_ni_vc3           : 1;
14106 	mmr_t	sh_ni0_error_mask_1_regval;
14108 		mmr_t	tail_timeout_ni_vc3           : 1;
14109 		mmr_t	tail_timeout_ni_vc2           : 1;
14110 		mmr_t	tail_timeout_ni_vc1           : 1;
14111 		mmr_t	tail_timeout_ni_vc0           : 1;
14112 		mmr_t	tail_timeout_fifo13_vc3       : 1;
14113 		mmr_t	tail_timeout_fifo13_vc1       : 1;
14114 		mmr_t	tail_timeout_fifo02_vc2       : 1;
14115 		mmr_t	tail_timeout_fifo02_vc0       : 1;
14116 		mmr_t	overflow_ni_fifo_vc3_credit   : 1;
14117 		mmr_t	overflow_ni_fifo_vc2_credit   : 1;
14118 		mmr_t	overflow_ni_fifo_vc1_credit   : 1;
14119 		mmr_t	overflow_ni_fifo_vc0_credit   : 1;
14120 		mmr_t	overflow_md_fifo_vc2_credit   : 1;
14121 		mmr_t	overflow_md_fifo_vc0_credit   : 1;
14122 		mmr_t	overflow_iilb_fifo_vc2_credit : 1;
14123 		mmr_t	overflow_iilb_fifo_vc0_credit : 1;
14124 		mmr_t	overflow_pi_fifo_vc2_credit   : 1;
14125 		mmr_t	overflow_pi_fifo_vc0_credit   : 1;
14126 		mmr_t	overflow_md_fifo_vc2_push     : 1;
14127 		mmr_t	overflow_md_fifo_vc0_push     : 1;
14128 		mmr_t	overflow_iilb_fifo_vc2_push   : 1;
14129 		mmr_t	overflow_iilb_fifo_vc0_push   : 1;
14130 		mmr_t	overflow_pi_fifo_vc2_push     : 1;
14131 		mmr_t	overflow_pi_fifo_vc0_push     : 1;
14132 		mmr_t	overflow_ni_fifo_vc2_pop      : 1;
14133 		mmr_t	overflow_ni_fifo_vc0_pop      : 1;
14134 		mmr_t	overflow_md_fifo_vc2_pop      : 1;
14135 		mmr_t	overflow_md_fifo_vc0_pop      : 1;
14136 		mmr_t	overflow_iilb_fifo_vc2_pop    : 1;
14137 		mmr_t	overflow_iilb_fifo_vc0_pop    : 1;
14138 		mmr_t	overflow_pi_fifo_vc2_pop      : 1;
14139 		mmr_t	overflow_pi_fifo_vc0_pop      : 1;
14140 		mmr_t	overflow_ni_fifo_debit3       : 1;
14141 		mmr_t	overflow_ni_fifo_debit2       : 1;
14142 		mmr_t	overflow_ni_fifo_debit1       : 1;
14143 		mmr_t	overflow_ni_fifo_debit0       : 1;
14144 		mmr_t	overflow_md_fifo_debit2       : 1;
14145 		mmr_t	overflow_md_fifo_debit0       : 1;
14146 		mmr_t	overflow_iilb_fifo_debit2     : 1;
14147 		mmr_t	overflow_iilb_fifo_debit0     : 1;
14148 		mmr_t	overflow_pi_fifo_debit2       : 1;
14149 		mmr_t	overflow_pi_fifo_debit0       : 1;
14150 		mmr_t	overflow2_vc2_credit          : 1;
14151 		mmr_t	overflow1_vc2_credit          : 1;
14152 		mmr_t	overflow0_vc2_credit          : 1;
14153 		mmr_t	overflow2_vc0_credit          : 1;
14154 		mmr_t	overflow1_vc0_credit          : 1;
14155 		mmr_t	overflow0_vc0_credit          : 1;
14156 		mmr_t	overflow_fifo13_vc2_credit    : 1;
14157 		mmr_t	overflow_fifo13_vc0_credit    : 1;
14158 		mmr_t	overflow_fifo02_vc2_credit    : 1;
14159 		mmr_t	overflow_fifo02_vc0_credit    : 1;
14160 		mmr_t	overflow_fifo13_vc3_push      : 1;
14161 		mmr_t	overflow_fifo13_vc1_push      : 1;
14162 		mmr_t	overflow_fifo02_vc2_push      : 1;
14163 		mmr_t	overflow_fifo02_vc0_push      : 1;
14164 		mmr_t	overflow_fifo13_vc3_pop       : 1;
14165 		mmr_t	overflow_fifo13_vc1_pop       : 1;
14166 		mmr_t	overflow_fifo02_vc2_pop       : 1;
14167 		mmr_t	overflow_fifo02_vc0_pop       : 1;
14168 		mmr_t	overflow_fifo13_debit2        : 1;
14169 		mmr_t	overflow_fifo13_debit0        : 1;
14170 		mmr_t	overflow_fifo02_debit2        : 1;
14171 		mmr_t	overflow_fifo02_debit0        : 1;
14183 	mmr_t	sh_ni0_error_mask_2_regval;
14185 		mmr_t	illegal_vcni                   : 1;
14186 		mmr_t	illegal_vcpi                   : 1;
14187 		mmr_t	illegal_vcmd                   : 1;
14188 		mmr_t	illegal_vciilb                 : 1;
14189 		mmr_t	underflow_fifo02_vc0_pop       : 1;
14190 		mmr_t	underflow_fifo02_vc2_pop       : 1;
14191 		mmr_t	underflow_fifo13_vc1_pop       : 1;
14192 		mmr_t	underflow_fifo13_vc3_pop       : 1;
14193 		mmr_t	underflow_fifo02_vc0_push      : 1;
14194 		mmr_t	underflow_fifo02_vc2_push      : 1;
14195 		mmr_t	underflow_fifo13_vc1_push      : 1;
14196 		mmr_t	underflow_fifo13_vc3_push      : 1;
14197 		mmr_t	underflow_fifo02_vc0_credit    : 1;
14198 		mmr_t	underflow_fifo02_vc2_credit    : 1;
14199 		mmr_t	underflow_fifo13_vc0_credit    : 1;
14200 		mmr_t	underflow_fifo13_vc2_credit    : 1;
14201 		mmr_t	underflow0_vc0_credit          : 1;
14202 		mmr_t	underflow1_vc0_credit          : 1;
14203 		mmr_t	underflow2_vc0_credit          : 1;
14204 		mmr_t	underflow0_vc2_credit          : 1;
14205 		mmr_t	underflow1_vc2_credit          : 1;
14206 		mmr_t	underflow2_vc2_credit          : 1;
14207 		mmr_t	reserved_0                     : 10;
14208 		mmr_t	underflow_pi_fifo_vc0_pop      : 1;
14209 		mmr_t	underflow_pi_fifo_vc2_pop      : 1;
14210 		mmr_t	underflow_iilb_fifo_vc0_pop    : 1;
14211 		mmr_t	underflow_iilb_fifo_vc2_pop    : 1;
14212 		mmr_t	underflow_md_fifo_vc0_pop      : 1;
14213 		mmr_t	underflow_md_fifo_vc2_pop      : 1;
14214 		mmr_t	underflow_ni_fifo_vc0_pop      : 1;
14215 		mmr_t	underflow_ni_fifo_vc2_pop      : 1;
14216 		mmr_t	underflow_pi_fifo_vc0_push     : 1;
14217 		mmr_t	underflow_pi_fifo_vc2_push     : 1;
14218 		mmr_t	underflow_iilb_fifo_vc0_push   : 1;
14219 		mmr_t	underflow_iilb_fifo_vc2_push   : 1;
14220 		mmr_t	underflow_md_fifo_vc0_push     : 1;
14221 		mmr_t	underflow_md_fifo_vc2_push     : 1;
14222 		mmr_t	underflow_pi_fifo_vc0_credit   : 1;
14223 		mmr_t	underflow_pi_fifo_vc2_credit   : 1;
14224 		mmr_t	underflow_iilb_fifo_vc0_credit : 1;
14225 		mmr_t	underflow_iilb_fifo_vc2_credit : 1;
14226 		mmr_t	underflow_md_fifo_vc0_credit   : 1;
14227 		mmr_t	underflow_md_fifo_vc2_credit   : 1;
14228 		mmr_t	underflow_ni_fifo_vc0_credit   : 1;
14229 		mmr_t	underflow_ni_fifo_vc1_credit   : 1;
14230 		mmr_t	underflow_ni_fifo_vc2_credit   : 1;
14231 		mmr_t	underflow_ni_fifo_vc3_credit   : 1;
14232 		mmr_t	llp_deadlock_vc0               : 1;
14233 		mmr_t	llp_deadlock_vc1               : 1;
14234 		mmr_t	llp_deadlock_vc2               : 1;
14235 		mmr_t	llp_deadlock_vc3               : 1;
14236 		mmr_t	chiplet_nomatch                : 1;
14237 		mmr_t	lut_read_error                 : 1;
14238 		mmr_t	retry_timeout_error            : 1;
14239 		mmr_t	reserved_1                     : 1;
14244 	mmr_t	sh_ni0_error_mask_2_regval;
14246 		mmr_t	reserved_1                     : 1;
14247 		mmr_t	retry_timeout_error            : 1;
14248 		mmr_t	lut_read_error                 : 1;
14249 		mmr_t	chiplet_nomatch                : 1;
14250 		mmr_t	llp_deadlock_vc3               : 1;
14251 		mmr_t	llp_deadlock_vc2               : 1;
14252 		mmr_t	llp_deadlock_vc1               : 1;
14253 		mmr_t	llp_deadlock_vc0               : 1;
14254 		mmr_t	underflow_ni_fifo_vc3_credit   : 1;
14255 		mmr_t	underflow_ni_fifo_vc2_credit   : 1;
14256 		mmr_t	underflow_ni_fifo_vc1_credit   : 1;
14257 		mmr_t	underflow_ni_fifo_vc0_credit   : 1;
14258 		mmr_t	underflow_md_fifo_vc2_credit   : 1;
14259 		mmr_t	underflow_md_fifo_vc0_credit   : 1;
14260 		mmr_t	underflow_iilb_fifo_vc2_credit : 1;
14261 		mmr_t	underflow_iilb_fifo_vc0_credit : 1;
14262 		mmr_t	underflow_pi_fifo_vc2_credit   : 1;
14263 		mmr_t	underflow_pi_fifo_vc0_credit   : 1;
14264 		mmr_t	underflow_md_fifo_vc2_push     : 1;
14265 		mmr_t	underflow_md_fifo_vc0_push     : 1;
14266 		mmr_t	underflow_iilb_fifo_vc2_push   : 1;
14267 		mmr_t	underflow_iilb_fifo_vc0_push   : 1;
14268 		mmr_t	underflow_pi_fifo_vc2_push     : 1;
14269 		mmr_t	underflow_pi_fifo_vc0_push     : 1;
14270 		mmr_t	underflow_ni_fifo_vc2_pop      : 1;
14271 		mmr_t	underflow_ni_fifo_vc0_pop      : 1;
14272 		mmr_t	underflow_md_fifo_vc2_pop      : 1;
14273 		mmr_t	underflow_md_fifo_vc0_pop      : 1;
14274 		mmr_t	underflow_iilb_fifo_vc2_pop    : 1;
14275 		mmr_t	underflow_iilb_fifo_vc0_pop    : 1;
14276 		mmr_t	underflow_pi_fifo_vc2_pop      : 1;
14277 		mmr_t	underflow_pi_fifo_vc0_pop      : 1;
14278 		mmr_t	reserved_0                     : 10;
14279 		mmr_t	underflow2_vc2_credit          : 1;
14280 		mmr_t	underflow1_vc2_credit          : 1;
14281 		mmr_t	underflow0_vc2_credit          : 1;
14282 		mmr_t	underflow2_vc0_credit          : 1;
14283 		mmr_t	underflow1_vc0_credit          : 1;
14284 		mmr_t	underflow0_vc0_credit          : 1;
14285 		mmr_t	underflow_fifo13_vc2_credit    : 1;
14286 		mmr_t	underflow_fifo13_vc0_credit    : 1;
14287 		mmr_t	underflow_fifo02_vc2_credit    : 1;
14288 		mmr_t	underflow_fifo02_vc0_credit    : 1;
14289 		mmr_t	underflow_fifo13_vc3_push      : 1;
14290 		mmr_t	underflow_fifo13_vc1_push      : 1;
14291 		mmr_t	underflow_fifo02_vc2_push      : 1;
14292 		mmr_t	underflow_fifo02_vc0_push      : 1;
14293 		mmr_t	underflow_fifo13_vc3_pop       : 1;
14294 		mmr_t	underflow_fifo13_vc1_pop       : 1;
14295 		mmr_t	underflow_fifo02_vc2_pop       : 1;
14296 		mmr_t	underflow_fifo02_vc0_pop       : 1;
14297 		mmr_t	illegal_vciilb                 : 1;
14298 		mmr_t	illegal_vcmd                   : 1;
14299 		mmr_t	illegal_vcpi                   : 1;
14300 		mmr_t	illegal_vcni                   : 1;
14312 	mmr_t	sh_ni0_first_error_1_regval;
14314 		mmr_t	overflow_fifo02_debit0        : 1;
14315 		mmr_t	overflow_fifo02_debit2        : 1;
14316 		mmr_t	overflow_fifo13_debit0        : 1;
14317 		mmr_t	overflow_fifo13_debit2        : 1;
14318 		mmr_t	overflow_fifo02_vc0_pop       : 1;
14319 		mmr_t	overflow_fifo02_vc2_pop       : 1;
14320 		mmr_t	overflow_fifo13_vc1_pop       : 1;
14321 		mmr_t	overflow_fifo13_vc3_pop       : 1;
14322 		mmr_t	overflow_fifo02_vc0_push      : 1;
14323 		mmr_t	overflow_fifo02_vc2_push      : 1;
14324 		mmr_t	overflow_fifo13_vc1_push      : 1;
14325 		mmr_t	overflow_fifo13_vc3_push      : 1;
14326 		mmr_t	overflow_fifo02_vc0_credit    : 1;
14327 		mmr_t	overflow_fifo02_vc2_credit    : 1;
14328 		mmr_t	overflow_fifo13_vc0_credit    : 1;
14329 		mmr_t	overflow_fifo13_vc2_credit    : 1;
14330 		mmr_t	overflow0_vc0_credit          : 1;
14331 		mmr_t	overflow1_vc0_credit          : 1;
14332 		mmr_t	overflow2_vc0_credit          : 1;
14333 		mmr_t	overflow0_vc2_credit          : 1;
14334 		mmr_t	overflow1_vc2_credit          : 1;
14335 		mmr_t	overflow2_vc2_credit          : 1;
14336 		mmr_t	overflow_pi_fifo_debit0       : 1;
14337 		mmr_t	overflow_pi_fifo_debit2       : 1;
14338 		mmr_t	overflow_iilb_fifo_debit0     : 1;
14339 		mmr_t	overflow_iilb_fifo_debit2     : 1;
14340 		mmr_t	overflow_md_fifo_debit0       : 1;
14341 		mmr_t	overflow_md_fifo_debit2       : 1;
14342 		mmr_t	overflow_ni_fifo_debit0       : 1;
14343 		mmr_t	overflow_ni_fifo_debit1       : 1;
14344 		mmr_t	overflow_ni_fifo_debit2       : 1;
14345 		mmr_t	overflow_ni_fifo_debit3       : 1;
14346 		mmr_t	overflow_pi_fifo_vc0_pop      : 1;
14347 		mmr_t	overflow_pi_fifo_vc2_pop      : 1;
14348 		mmr_t	overflow_iilb_fifo_vc0_pop    : 1;
14349 		mmr_t	overflow_iilb_fifo_vc2_pop    : 1;
14350 		mmr_t	overflow_md_fifo_vc0_pop      : 1;
14351 		mmr_t	overflow_md_fifo_vc2_pop      : 1;
14352 		mmr_t	overflow_ni_fifo_vc0_pop      : 1;
14353 		mmr_t	overflow_ni_fifo_vc2_pop      : 1;
14354 		mmr_t	overflow_pi_fifo_vc0_push     : 1;
14355 		mmr_t	overflow_pi_fifo_vc2_push     : 1;
14356 		mmr_t	overflow_iilb_fifo_vc0_push   : 1;
14357 		mmr_t	overflow_iilb_fifo_vc2_push   : 1;
14358 		mmr_t	overflow_md_fifo_vc0_push     : 1;
14359 		mmr_t	overflow_md_fifo_vc2_push     : 1;
14360 		mmr_t	overflow_pi_fifo_vc0_credit   : 1;
14361 		mmr_t	overflow_pi_fifo_vc2_credit   : 1;
14362 		mmr_t	overflow_iilb_fifo_vc0_credit : 1;
14363 		mmr_t	overflow_iilb_fifo_vc2_credit : 1;
14364 		mmr_t	overflow_md_fifo_vc0_credit   : 1;
14365 		mmr_t	overflow_md_fifo_vc2_credit   : 1;
14366 		mmr_t	overflow_ni_fifo_vc0_credit   : 1;
14367 		mmr_t	overflow_ni_fifo_vc1_credit   : 1;
14368 		mmr_t	overflow_ni_fifo_vc2_credit   : 1;
14369 		mmr_t	overflow_ni_fifo_vc3_credit   : 1;
14370 		mmr_t	tail_timeout_fifo02_vc0       : 1;
14371 		mmr_t	tail_timeout_fifo02_vc2       : 1;
14372 		mmr_t	tail_timeout_fifo13_vc1       : 1;
14373 		mmr_t	tail_timeout_fifo13_vc3       : 1;
14374 		mmr_t	tail_timeout_ni_vc0           : 1;
14375 		mmr_t	tail_timeout_ni_vc1           : 1;
14376 		mmr_t	tail_timeout_ni_vc2           : 1;
14377 		mmr_t	tail_timeout_ni_vc3           : 1;
14382 	mmr_t	sh_ni0_first_error_1_regval;
14384 		mmr_t	tail_timeout_ni_vc3           : 1;
14385 		mmr_t	tail_timeout_ni_vc2           : 1;
14386 		mmr_t	tail_timeout_ni_vc1           : 1;
14387 		mmr_t	tail_timeout_ni_vc0           : 1;
14388 		mmr_t	tail_timeout_fifo13_vc3       : 1;
14389 		mmr_t	tail_timeout_fifo13_vc1       : 1;
14390 		mmr_t	tail_timeout_fifo02_vc2       : 1;
14391 		mmr_t	tail_timeout_fifo02_vc0       : 1;
14392 		mmr_t	overflow_ni_fifo_vc3_credit   : 1;
14393 		mmr_t	overflow_ni_fifo_vc2_credit   : 1;
14394 		mmr_t	overflow_ni_fifo_vc1_credit   : 1;
14395 		mmr_t	overflow_ni_fifo_vc0_credit   : 1;
14396 		mmr_t	overflow_md_fifo_vc2_credit   : 1;
14397 		mmr_t	overflow_md_fifo_vc0_credit   : 1;
14398 		mmr_t	overflow_iilb_fifo_vc2_credit : 1;
14399 		mmr_t	overflow_iilb_fifo_vc0_credit : 1;
14400 		mmr_t	overflow_pi_fifo_vc2_credit   : 1;
14401 		mmr_t	overflow_pi_fifo_vc0_credit   : 1;
14402 		mmr_t	overflow_md_fifo_vc2_push     : 1;
14403 		mmr_t	overflow_md_fifo_vc0_push     : 1;
14404 		mmr_t	overflow_iilb_fifo_vc2_push   : 1;
14405 		mmr_t	overflow_iilb_fifo_vc0_push   : 1;
14406 		mmr_t	overflow_pi_fifo_vc2_push     : 1;
14407 		mmr_t	overflow_pi_fifo_vc0_push     : 1;
14408 		mmr_t	overflow_ni_fifo_vc2_pop      : 1;
14409 		mmr_t	overflow_ni_fifo_vc0_pop      : 1;
14410 		mmr_t	overflow_md_fifo_vc2_pop      : 1;
14411 		mmr_t	overflow_md_fifo_vc0_pop      : 1;
14412 		mmr_t	overflow_iilb_fifo_vc2_pop    : 1;
14413 		mmr_t	overflow_iilb_fifo_vc0_pop    : 1;
14414 		mmr_t	overflow_pi_fifo_vc2_pop      : 1;
14415 		mmr_t	overflow_pi_fifo_vc0_pop      : 1;
14416 		mmr_t	overflow_ni_fifo_debit3       : 1;
14417 		mmr_t	overflow_ni_fifo_debit2       : 1;
14418 		mmr_t	overflow_ni_fifo_debit1       : 1;
14419 		mmr_t	overflow_ni_fifo_debit0       : 1;
14420 		mmr_t	overflow_md_fifo_debit2       : 1;
14421 		mmr_t	overflow_md_fifo_debit0       : 1;
14422 		mmr_t	overflow_iilb_fifo_debit2     : 1;
14423 		mmr_t	overflow_iilb_fifo_debit0     : 1;
14424 		mmr_t	overflow_pi_fifo_debit2       : 1;
14425 		mmr_t	overflow_pi_fifo_debit0       : 1;
14426 		mmr_t	overflow2_vc2_credit          : 1;
14427 		mmr_t	overflow1_vc2_credit          : 1;
14428 		mmr_t	overflow0_vc2_credit          : 1;
14429 		mmr_t	overflow2_vc0_credit          : 1;
14430 		mmr_t	overflow1_vc0_credit          : 1;
14431 		mmr_t	overflow0_vc0_credit          : 1;
14432 		mmr_t	overflow_fifo13_vc2_credit    : 1;
14433 		mmr_t	overflow_fifo13_vc0_credit    : 1;
14434 		mmr_t	overflow_fifo02_vc2_credit    : 1;
14435 		mmr_t	overflow_fifo02_vc0_credit    : 1;
14436 		mmr_t	overflow_fifo13_vc3_push      : 1;
14437 		mmr_t	overflow_fifo13_vc1_push      : 1;
14438 		mmr_t	overflow_fifo02_vc2_push      : 1;
14439 		mmr_t	overflow_fifo02_vc0_push      : 1;
14440 		mmr_t	overflow_fifo13_vc3_pop       : 1;
14441 		mmr_t	overflow_fifo13_vc1_pop       : 1;
14442 		mmr_t	overflow_fifo02_vc2_pop       : 1;
14443 		mmr_t	overflow_fifo02_vc0_pop       : 1;
14444 		mmr_t	overflow_fifo13_debit2        : 1;
14445 		mmr_t	overflow_fifo13_debit0        : 1;
14446 		mmr_t	overflow_fifo02_debit2        : 1;
14447 		mmr_t	overflow_fifo02_debit0        : 1;
14459 	mmr_t	sh_ni0_first_error_2_regval;
14461 		mmr_t	illegal_vcni                   : 1;
14462 		mmr_t	illegal_vcpi                   : 1;
14463 		mmr_t	illegal_vcmd                   : 1;
14464 		mmr_t	illegal_vciilb                 : 1;
14465 		mmr_t	underflow_fifo02_vc0_pop       : 1;
14466 		mmr_t	underflow_fifo02_vc2_pop       : 1;
14467 		mmr_t	underflow_fifo13_vc1_pop       : 1;
14468 		mmr_t	underflow_fifo13_vc3_pop       : 1;
14469 		mmr_t	underflow_fifo02_vc0_push      : 1;
14470 		mmr_t	underflow_fifo02_vc2_push      : 1;
14471 		mmr_t	underflow_fifo13_vc1_push      : 1;
14472 		mmr_t	underflow_fifo13_vc3_push      : 1;
14473 		mmr_t	underflow_fifo02_vc0_credit    : 1;
14474 		mmr_t	underflow_fifo02_vc2_credit    : 1;
14475 		mmr_t	underflow_fifo13_vc0_credit    : 1;
14476 		mmr_t	underflow_fifo13_vc2_credit    : 1;
14477 		mmr_t	underflow0_vc0_credit          : 1;
14478 		mmr_t	underflow1_vc0_credit          : 1;
14479 		mmr_t	underflow2_vc0_credit          : 1;
14480 		mmr_t	underflow0_vc2_credit          : 1;
14481 		mmr_t	underflow1_vc2_credit          : 1;
14482 		mmr_t	underflow2_vc2_credit          : 1;
14483 		mmr_t	reserved_0                     : 10;
14484 		mmr_t	underflow_pi_fifo_vc0_pop      : 1;
14485 		mmr_t	underflow_pi_fifo_vc2_pop      : 1;
14486 		mmr_t	underflow_iilb_fifo_vc0_pop    : 1;
14487 		mmr_t	underflow_iilb_fifo_vc2_pop    : 1;
14488 		mmr_t	underflow_md_fifo_vc0_pop      : 1;
14489 		mmr_t	underflow_md_fifo_vc2_pop      : 1;
14490 		mmr_t	underflow_ni_fifo_vc0_pop      : 1;
14491 		mmr_t	underflow_ni_fifo_vc2_pop      : 1;
14492 		mmr_t	underflow_pi_fifo_vc0_push     : 1;
14493 		mmr_t	underflow_pi_fifo_vc2_push     : 1;
14494 		mmr_t	underflow_iilb_fifo_vc0_push   : 1;
14495 		mmr_t	underflow_iilb_fifo_vc2_push   : 1;
14496 		mmr_t	underflow_md_fifo_vc0_push     : 1;
14497 		mmr_t	underflow_md_fifo_vc2_push     : 1;
14498 		mmr_t	underflow_pi_fifo_vc0_credit   : 1;
14499 		mmr_t	underflow_pi_fifo_vc2_credit   : 1;
14500 		mmr_t	underflow_iilb_fifo_vc0_credit : 1;
14501 		mmr_t	underflow_iilb_fifo_vc2_credit : 1;
14502 		mmr_t	underflow_md_fifo_vc0_credit   : 1;
14503 		mmr_t	underflow_md_fifo_vc2_credit   : 1;
14504 		mmr_t	underflow_ni_fifo_vc0_credit   : 1;
14505 		mmr_t	underflow_ni_fifo_vc1_credit   : 1;
14506 		mmr_t	underflow_ni_fifo_vc2_credit   : 1;
14507 		mmr_t	underflow_ni_fifo_vc3_credit   : 1;
14508 		mmr_t	llp_deadlock_vc0               : 1;
14509 		mmr_t	llp_deadlock_vc1               : 1;
14510 		mmr_t	llp_deadlock_vc2               : 1;
14511 		mmr_t	llp_deadlock_vc3               : 1;
14512 		mmr_t	chiplet_nomatch                : 1;
14513 		mmr_t	lut_read_error                 : 1;
14514 		mmr_t	retry_timeout_error            : 1;
14515 		mmr_t	reserved_1                     : 1;
14520 	mmr_t	sh_ni0_first_error_2_regval;
14522 		mmr_t	reserved_1                     : 1;
14523 		mmr_t	retry_timeout_error            : 1;
14524 		mmr_t	lut_read_error                 : 1;
14525 		mmr_t	chiplet_nomatch                : 1;
14526 		mmr_t	llp_deadlock_vc3               : 1;
14527 		mmr_t	llp_deadlock_vc2               : 1;
14528 		mmr_t	llp_deadlock_vc1               : 1;
14529 		mmr_t	llp_deadlock_vc0               : 1;
14530 		mmr_t	underflow_ni_fifo_vc3_credit   : 1;
14531 		mmr_t	underflow_ni_fifo_vc2_credit   : 1;
14532 		mmr_t	underflow_ni_fifo_vc1_credit   : 1;
14533 		mmr_t	underflow_ni_fifo_vc0_credit   : 1;
14534 		mmr_t	underflow_md_fifo_vc2_credit   : 1;
14535 		mmr_t	underflow_md_fifo_vc0_credit   : 1;
14536 		mmr_t	underflow_iilb_fifo_vc2_credit : 1;
14537 		mmr_t	underflow_iilb_fifo_vc0_credit : 1;
14538 		mmr_t	underflow_pi_fifo_vc2_credit   : 1;
14539 		mmr_t	underflow_pi_fifo_vc0_credit   : 1;
14540 		mmr_t	underflow_md_fifo_vc2_push     : 1;
14541 		mmr_t	underflow_md_fifo_vc0_push     : 1;
14542 		mmr_t	underflow_iilb_fifo_vc2_push   : 1;
14543 		mmr_t	underflow_iilb_fifo_vc0_push   : 1;
14544 		mmr_t	underflow_pi_fifo_vc2_push     : 1;
14545 		mmr_t	underflow_pi_fifo_vc0_push     : 1;
14546 		mmr_t	underflow_ni_fifo_vc2_pop      : 1;
14547 		mmr_t	underflow_ni_fifo_vc0_pop      : 1;
14548 		mmr_t	underflow_md_fifo_vc2_pop      : 1;
14549 		mmr_t	underflow_md_fifo_vc0_pop      : 1;
14550 		mmr_t	underflow_iilb_fifo_vc2_pop    : 1;
14551 		mmr_t	underflow_iilb_fifo_vc0_pop    : 1;
14552 		mmr_t	underflow_pi_fifo_vc2_pop      : 1;
14553 		mmr_t	underflow_pi_fifo_vc0_pop      : 1;
14554 		mmr_t	reserved_0                     : 10;
14555 		mmr_t	underflow2_vc2_credit          : 1;
14556 		mmr_t	underflow1_vc2_credit          : 1;
14557 		mmr_t	underflow0_vc2_credit          : 1;
14558 		mmr_t	underflow2_vc0_credit          : 1;
14559 		mmr_t	underflow1_vc0_credit          : 1;
14560 		mmr_t	underflow0_vc0_credit          : 1;
14561 		mmr_t	underflow_fifo13_vc2_credit    : 1;
14562 		mmr_t	underflow_fifo13_vc0_credit    : 1;
14563 		mmr_t	underflow_fifo02_vc2_credit    : 1;
14564 		mmr_t	underflow_fifo02_vc0_credit    : 1;
14565 		mmr_t	underflow_fifo13_vc3_push      : 1;
14566 		mmr_t	underflow_fifo13_vc1_push      : 1;
14567 		mmr_t	underflow_fifo02_vc2_push      : 1;
14568 		mmr_t	underflow_fifo02_vc0_push      : 1;
14569 		mmr_t	underflow_fifo13_vc3_pop       : 1;
14570 		mmr_t	underflow_fifo13_vc1_pop       : 1;
14571 		mmr_t	underflow_fifo02_vc2_pop       : 1;
14572 		mmr_t	underflow_fifo02_vc0_pop       : 1;
14573 		mmr_t	illegal_vciilb                 : 1;
14574 		mmr_t	illegal_vcmd                   : 1;
14575 		mmr_t	illegal_vcpi                   : 1;
14576 		mmr_t	illegal_vcni                   : 1;
14588 	mmr_t	sh_ni0_error_detail_1_regval;
14590 		mmr_t	header      : 64;
14595 	mmr_t	sh_ni0_error_detail_1_regval;
14597 		mmr_t	header      : 64;
14609 	mmr_t	sh_ni0_error_detail_2_regval;
14611 		mmr_t	header      : 64;
14616 	mmr_t	sh_ni0_error_detail_2_regval;
14618 		mmr_t	header      : 64;
14630 	mmr_t	sh_ni1_error_summary_1_regval;
14632 		mmr_t	overflow_fifo02_debit0        : 1;
14633 		mmr_t	overflow_fifo02_debit2        : 1;
14634 		mmr_t	overflow_fifo13_debit0        : 1;
14635 		mmr_t	overflow_fifo13_debit2        : 1;
14636 		mmr_t	overflow_fifo02_vc0_pop       : 1;
14637 		mmr_t	overflow_fifo02_vc2_pop       : 1;
14638 		mmr_t	overflow_fifo13_vc1_pop       : 1;
14639 		mmr_t	overflow_fifo13_vc3_pop       : 1;
14640 		mmr_t	overflow_fifo02_vc0_push      : 1;
14641 		mmr_t	overflow_fifo02_vc2_push      : 1;
14642 		mmr_t	overflow_fifo13_vc1_push      : 1;
14643 		mmr_t	overflow_fifo13_vc3_push      : 1;
14644 		mmr_t	overflow_fifo02_vc0_credit    : 1;
14645 		mmr_t	overflow_fifo02_vc2_credit    : 1;
14646 		mmr_t	overflow_fifo13_vc0_credit    : 1;
14647 		mmr_t	overflow_fifo13_vc2_credit    : 1;
14648 		mmr_t	overflow0_vc0_credit          : 1;
14649 		mmr_t	overflow1_vc0_credit          : 1;
14650 		mmr_t	overflow2_vc0_credit          : 1;
14651 		mmr_t	overflow0_vc2_credit          : 1;
14652 		mmr_t	overflow1_vc2_credit          : 1;
14653 		mmr_t	overflow2_vc2_credit          : 1;
14654 		mmr_t	overflow_pi_fifo_debit0       : 1;
14655 		mmr_t	overflow_pi_fifo_debit2       : 1;
14656 		mmr_t	overflow_iilb_fifo_debit0     : 1;
14657 		mmr_t	overflow_iilb_fifo_debit2     : 1;
14658 		mmr_t	overflow_md_fifo_debit0       : 1;
14659 		mmr_t	overflow_md_fifo_debit2       : 1;
14660 		mmr_t	overflow_ni_fifo_debit0       : 1;
14661 		mmr_t	overflow_ni_fifo_debit1       : 1;
14662 		mmr_t	overflow_ni_fifo_debit2       : 1;
14663 		mmr_t	overflow_ni_fifo_debit3       : 1;
14664 		mmr_t	overflow_pi_fifo_vc0_pop      : 1;
14665 		mmr_t	overflow_pi_fifo_vc2_pop      : 1;
14666 		mmr_t	overflow_iilb_fifo_vc0_pop    : 1;
14667 		mmr_t	overflow_iilb_fifo_vc2_pop    : 1;
14668 		mmr_t	overflow_md_fifo_vc0_pop      : 1;
14669 		mmr_t	overflow_md_fifo_vc2_pop      : 1;
14670 		mmr_t	overflow_ni_fifo_vc0_pop      : 1;
14671 		mmr_t	overflow_ni_fifo_vc2_pop      : 1;
14672 		mmr_t	overflow_pi_fifo_vc0_push     : 1;
14673 		mmr_t	overflow_pi_fifo_vc2_push     : 1;
14674 		mmr_t	overflow_iilb_fifo_vc0_push   : 1;
14675 		mmr_t	overflow_iilb_fifo_vc2_push   : 1;
14676 		mmr_t	overflow_md_fifo_vc0_push     : 1;
14677 		mmr_t	overflow_md_fifo_vc2_push     : 1;
14678 		mmr_t	overflow_pi_fifo_vc0_credit   : 1;
14679 		mmr_t	overflow_pi_fifo_vc2_credit   : 1;
14680 		mmr_t	overflow_iilb_fifo_vc0_credit : 1;
14681 		mmr_t	overflow_iilb_fifo_vc2_credit : 1;
14682 		mmr_t	overflow_md_fifo_vc0_credit   : 1;
14683 		mmr_t	overflow_md_fifo_vc2_credit   : 1;
14684 		mmr_t	overflow_ni_fifo_vc0_credit   : 1;
14685 		mmr_t	overflow_ni_fifo_vc1_credit   : 1;
14686 		mmr_t	overflow_ni_fifo_vc2_credit   : 1;
14687 		mmr_t	overflow_ni_fifo_vc3_credit   : 1;
14688 		mmr_t	tail_timeout_fifo02_vc0       : 1;
14689 		mmr_t	tail_timeout_fifo02_vc2       : 1;
14690 		mmr_t	tail_timeout_fifo13_vc1       : 1;
14691 		mmr_t	tail_timeout_fifo13_vc3       : 1;
14692 		mmr_t	tail_timeout_ni_vc0           : 1;
14693 		mmr_t	tail_timeout_ni_vc1           : 1;
14694 		mmr_t	tail_timeout_ni_vc2           : 1;
14695 		mmr_t	tail_timeout_ni_vc3           : 1;
14700 	mmr_t	sh_ni1_error_summary_1_regval;
14702 		mmr_t	tail_timeout_ni_vc3           : 1;
14703 		mmr_t	tail_timeout_ni_vc2           : 1;
14704 		mmr_t	tail_timeout_ni_vc1           : 1;
14705 		mmr_t	tail_timeout_ni_vc0           : 1;
14706 		mmr_t	tail_timeout_fifo13_vc3       : 1;
14707 		mmr_t	tail_timeout_fifo13_vc1       : 1;
14708 		mmr_t	tail_timeout_fifo02_vc2       : 1;
14709 		mmr_t	tail_timeout_fifo02_vc0       : 1;
14710 		mmr_t	overflow_ni_fifo_vc3_credit   : 1;
14711 		mmr_t	overflow_ni_fifo_vc2_credit   : 1;
14712 		mmr_t	overflow_ni_fifo_vc1_credit   : 1;
14713 		mmr_t	overflow_ni_fifo_vc0_credit   : 1;
14714 		mmr_t	overflow_md_fifo_vc2_credit   : 1;
14715 		mmr_t	overflow_md_fifo_vc0_credit   : 1;
14716 		mmr_t	overflow_iilb_fifo_vc2_credit : 1;
14717 		mmr_t	overflow_iilb_fifo_vc0_credit : 1;
14718 		mmr_t	overflow_pi_fifo_vc2_credit   : 1;
14719 		mmr_t	overflow_pi_fifo_vc0_credit   : 1;
14720 		mmr_t	overflow_md_fifo_vc2_push     : 1;
14721 		mmr_t	overflow_md_fifo_vc0_push     : 1;
14722 		mmr_t	overflow_iilb_fifo_vc2_push   : 1;
14723 		mmr_t	overflow_iilb_fifo_vc0_push   : 1;
14724 		mmr_t	overflow_pi_fifo_vc2_push     : 1;
14725 		mmr_t	overflow_pi_fifo_vc0_push     : 1;
14726 		mmr_t	overflow_ni_fifo_vc2_pop      : 1;
14727 		mmr_t	overflow_ni_fifo_vc0_pop      : 1;
14728 		mmr_t	overflow_md_fifo_vc2_pop      : 1;
14729 		mmr_t	overflow_md_fifo_vc0_pop      : 1;
14730 		mmr_t	overflow_iilb_fifo_vc2_pop    : 1;
14731 		mmr_t	overflow_iilb_fifo_vc0_pop    : 1;
14732 		mmr_t	overflow_pi_fifo_vc2_pop      : 1;
14733 		mmr_t	overflow_pi_fifo_vc0_pop      : 1;
14734 		mmr_t	overflow_ni_fifo_debit3       : 1;
14735 		mmr_t	overflow_ni_fifo_debit2       : 1;
14736 		mmr_t	overflow_ni_fifo_debit1       : 1;
14737 		mmr_t	overflow_ni_fifo_debit0       : 1;
14738 		mmr_t	overflow_md_fifo_debit2       : 1;
14739 		mmr_t	overflow_md_fifo_debit0       : 1;
14740 		mmr_t	overflow_iilb_fifo_debit2     : 1;
14741 		mmr_t	overflow_iilb_fifo_debit0     : 1;
14742 		mmr_t	overflow_pi_fifo_debit2       : 1;
14743 		mmr_t	overflow_pi_fifo_debit0       : 1;
14744 		mmr_t	overflow2_vc2_credit          : 1;
14745 		mmr_t	overflow1_vc2_credit          : 1;
14746 		mmr_t	overflow0_vc2_credit          : 1;
14747 		mmr_t	overflow2_vc0_credit          : 1;
14748 		mmr_t	overflow1_vc0_credit          : 1;
14749 		mmr_t	overflow0_vc0_credit          : 1;
14750 		mmr_t	overflow_fifo13_vc2_credit    : 1;
14751 		mmr_t	overflow_fifo13_vc0_credit    : 1;
14752 		mmr_t	overflow_fifo02_vc2_credit    : 1;
14753 		mmr_t	overflow_fifo02_vc0_credit    : 1;
14754 		mmr_t	overflow_fifo13_vc3_push      : 1;
14755 		mmr_t	overflow_fifo13_vc1_push      : 1;
14756 		mmr_t	overflow_fifo02_vc2_push      : 1;
14757 		mmr_t	overflow_fifo02_vc0_push      : 1;
14758 		mmr_t	overflow_fifo13_vc3_pop       : 1;
14759 		mmr_t	overflow_fifo13_vc1_pop       : 1;
14760 		mmr_t	overflow_fifo02_vc2_pop       : 1;
14761 		mmr_t	overflow_fifo02_vc0_pop       : 1;
14762 		mmr_t	overflow_fifo13_debit2        : 1;
14763 		mmr_t	overflow_fifo13_debit0        : 1;
14764 		mmr_t	overflow_fifo02_debit2        : 1;
14765 		mmr_t	overflow_fifo02_debit0        : 1;
14777 	mmr_t	sh_ni1_error_summary_2_regval;
14779 		mmr_t	illegal_vcni                   : 1;
14780 		mmr_t	illegal_vcpi                   : 1;
14781 		mmr_t	illegal_vcmd                   : 1;
14782 		mmr_t	illegal_vciilb                 : 1;
14783 		mmr_t	underflow_fifo02_vc0_pop       : 1;
14784 		mmr_t	underflow_fifo02_vc2_pop       : 1;
14785 		mmr_t	underflow_fifo13_vc1_pop       : 1;
14786 		mmr_t	underflow_fifo13_vc3_pop       : 1;
14787 		mmr_t	underflow_fifo02_vc0_push      : 1;
14788 		mmr_t	underflow_fifo02_vc2_push      : 1;
14789 		mmr_t	underflow_fifo13_vc1_push      : 1;
14790 		mmr_t	underflow_fifo13_vc3_push      : 1;
14791 		mmr_t	underflow_fifo02_vc0_credit    : 1;
14792 		mmr_t	underflow_fifo02_vc2_credit    : 1;
14793 		mmr_t	underflow_fifo13_vc0_credit    : 1;
14794 		mmr_t	underflow_fifo13_vc2_credit    : 1;
14795 		mmr_t	underflow0_vc0_credit          : 1;
14796 		mmr_t	underflow1_vc0_credit          : 1;
14797 		mmr_t	underflow2_vc0_credit          : 1;
14798 		mmr_t	underflow0_vc2_credit          : 1;
14799 		mmr_t	underflow1_vc2_credit          : 1;
14800 		mmr_t	underflow2_vc2_credit          : 1;
14801 		mmr_t	reserved_0                     : 10;
14802 		mmr_t	underflow_pi_fifo_vc0_pop      : 1;
14803 		mmr_t	underflow_pi_fifo_vc2_pop      : 1;
14804 		mmr_t	underflow_iilb_fifo_vc0_pop    : 1;
14805 		mmr_t	underflow_iilb_fifo_vc2_pop    : 1;
14806 		mmr_t	underflow_md_fifo_vc0_pop      : 1;
14807 		mmr_t	underflow_md_fifo_vc2_pop      : 1;
14808 		mmr_t	underflow_ni_fifo_vc0_pop      : 1;
14809 		mmr_t	underflow_ni_fifo_vc2_pop      : 1;
14810 		mmr_t	underflow_pi_fifo_vc0_push     : 1;
14811 		mmr_t	underflow_pi_fifo_vc2_push     : 1;
14812 		mmr_t	underflow_iilb_fifo_vc0_push   : 1;
14813 		mmr_t	underflow_iilb_fifo_vc2_push   : 1;
14814 		mmr_t	underflow_md_fifo_vc0_push     : 1;
14815 		mmr_t	underflow_md_fifo_vc2_push     : 1;
14816 		mmr_t	underflow_pi_fifo_vc0_credit   : 1;
14817 		mmr_t	underflow_pi_fifo_vc2_credit   : 1;
14818 		mmr_t	underflow_iilb_fifo_vc0_credit : 1;
14819 		mmr_t	underflow_iilb_fifo_vc2_credit : 1;
14820 		mmr_t	underflow_md_fifo_vc0_credit   : 1;
14821 		mmr_t	underflow_md_fifo_vc2_credit   : 1;
14822 		mmr_t	underflow_ni_fifo_vc0_credit   : 1;
14823 		mmr_t	underflow_ni_fifo_vc1_credit   : 1;
14824 		mmr_t	underflow_ni_fifo_vc2_credit   : 1;
14825 		mmr_t	underflow_ni_fifo_vc3_credit   : 1;
14826 		mmr_t	llp_deadlock_vc0               : 1;
14827 		mmr_t	llp_deadlock_vc1               : 1;
14828 		mmr_t	llp_deadlock_vc2               : 1;
14829 		mmr_t	llp_deadlock_vc3               : 1;
14830 		mmr_t	chiplet_nomatch                : 1;
14831 		mmr_t	lut_read_error                 : 1;
14832 		mmr_t	retry_timeout_error            : 1;
14833 		mmr_t	reserved_1                     : 1;
14838 	mmr_t	sh_ni1_error_summary_2_regval;
14840 		mmr_t	reserved_1                     : 1;
14841 		mmr_t	retry_timeout_error            : 1;
14842 		mmr_t	lut_read_error                 : 1;
14843 		mmr_t	chiplet_nomatch                : 1;
14844 		mmr_t	llp_deadlock_vc3               : 1;
14845 		mmr_t	llp_deadlock_vc2               : 1;
14846 		mmr_t	llp_deadlock_vc1               : 1;
14847 		mmr_t	llp_deadlock_vc0               : 1;
14848 		mmr_t	underflow_ni_fifo_vc3_credit   : 1;
14849 		mmr_t	underflow_ni_fifo_vc2_credit   : 1;
14850 		mmr_t	underflow_ni_fifo_vc1_credit   : 1;
14851 		mmr_t	underflow_ni_fifo_vc0_credit   : 1;
14852 		mmr_t	underflow_md_fifo_vc2_credit   : 1;
14853 		mmr_t	underflow_md_fifo_vc0_credit   : 1;
14854 		mmr_t	underflow_iilb_fifo_vc2_credit : 1;
14855 		mmr_t	underflow_iilb_fifo_vc0_credit : 1;
14856 		mmr_t	underflow_pi_fifo_vc2_credit   : 1;
14857 		mmr_t	underflow_pi_fifo_vc0_credit   : 1;
14858 		mmr_t	underflow_md_fifo_vc2_push     : 1;
14859 		mmr_t	underflow_md_fifo_vc0_push     : 1;
14860 		mmr_t	underflow_iilb_fifo_vc2_push   : 1;
14861 		mmr_t	underflow_iilb_fifo_vc0_push   : 1;
14862 		mmr_t	underflow_pi_fifo_vc2_push     : 1;
14863 		mmr_t	underflow_pi_fifo_vc0_push     : 1;
14864 		mmr_t	underflow_ni_fifo_vc2_pop      : 1;
14865 		mmr_t	underflow_ni_fifo_vc0_pop      : 1;
14866 		mmr_t	underflow_md_fifo_vc2_pop      : 1;
14867 		mmr_t	underflow_md_fifo_vc0_pop      : 1;
14868 		mmr_t	underflow_iilb_fifo_vc2_pop    : 1;
14869 		mmr_t	underflow_iilb_fifo_vc0_pop    : 1;
14870 		mmr_t	underflow_pi_fifo_vc2_pop      : 1;
14871 		mmr_t	underflow_pi_fifo_vc0_pop      : 1;
14872 		mmr_t	reserved_0                     : 10;
14873 		mmr_t	underflow2_vc2_credit          : 1;
14874 		mmr_t	underflow1_vc2_credit          : 1;
14875 		mmr_t	underflow0_vc2_credit          : 1;
14876 		mmr_t	underflow2_vc0_credit          : 1;
14877 		mmr_t	underflow1_vc0_credit          : 1;
14878 		mmr_t	underflow0_vc0_credit          : 1;
14879 		mmr_t	underflow_fifo13_vc2_credit    : 1;
14880 		mmr_t	underflow_fifo13_vc0_credit    : 1;
14881 		mmr_t	underflow_fifo02_vc2_credit    : 1;
14882 		mmr_t	underflow_fifo02_vc0_credit    : 1;
14883 		mmr_t	underflow_fifo13_vc3_push      : 1;
14884 		mmr_t	underflow_fifo13_vc1_push      : 1;
14885 		mmr_t	underflow_fifo02_vc2_push      : 1;
14886 		mmr_t	underflow_fifo02_vc0_push      : 1;
14887 		mmr_t	underflow_fifo13_vc3_pop       : 1;
14888 		mmr_t	underflow_fifo13_vc1_pop       : 1;
14889 		mmr_t	underflow_fifo02_vc2_pop       : 1;
14890 		mmr_t	underflow_fifo02_vc0_pop       : 1;
14891 		mmr_t	illegal_vciilb                 : 1;
14892 		mmr_t	illegal_vcmd                   : 1;
14893 		mmr_t	illegal_vcpi                   : 1;
14894 		mmr_t	illegal_vcni                   : 1;
14906 	mmr_t	sh_ni1_error_overflow_1_regval;
14908 		mmr_t	overflow_fifo02_debit0        : 1;
14909 		mmr_t	overflow_fifo02_debit2        : 1;
14910 		mmr_t	overflow_fifo13_debit0        : 1;
14911 		mmr_t	overflow_fifo13_debit2        : 1;
14912 		mmr_t	overflow_fifo02_vc0_pop       : 1;
14913 		mmr_t	overflow_fifo02_vc2_pop       : 1;
14914 		mmr_t	overflow_fifo13_vc1_pop       : 1;
14915 		mmr_t	overflow_fifo13_vc3_pop       : 1;
14916 		mmr_t	overflow_fifo02_vc0_push      : 1;
14917 		mmr_t	overflow_fifo02_vc2_push      : 1;
14918 		mmr_t	overflow_fifo13_vc1_push      : 1;
14919 		mmr_t	overflow_fifo13_vc3_push      : 1;
14920 		mmr_t	overflow_fifo02_vc0_credit    : 1;
14921 		mmr_t	overflow_fifo02_vc2_credit    : 1;
14922 		mmr_t	overflow_fifo13_vc0_credit    : 1;
14923 		mmr_t	overflow_fifo13_vc2_credit    : 1;
14924 		mmr_t	overflow0_vc0_credit          : 1;
14925 		mmr_t	overflow1_vc0_credit          : 1;
14926 		mmr_t	overflow2_vc0_credit          : 1;
14927 		mmr_t	overflow0_vc2_credit          : 1;
14928 		mmr_t	overflow1_vc2_credit          : 1;
14929 		mmr_t	overflow2_vc2_credit          : 1;
14930 		mmr_t	overflow_pi_fifo_debit0       : 1;
14931 		mmr_t	overflow_pi_fifo_debit2       : 1;
14932 		mmr_t	overflow_iilb_fifo_debit0     : 1;
14933 		mmr_t	overflow_iilb_fifo_debit2     : 1;
14934 		mmr_t	overflow_md_fifo_debit0       : 1;
14935 		mmr_t	overflow_md_fifo_debit2       : 1;
14936 		mmr_t	overflow_ni_fifo_debit0       : 1;
14937 		mmr_t	overflow_ni_fifo_debit1       : 1;
14938 		mmr_t	overflow_ni_fifo_debit2       : 1;
14939 		mmr_t	overflow_ni_fifo_debit3       : 1;
14940 		mmr_t	overflow_pi_fifo_vc0_pop      : 1;
14941 		mmr_t	overflow_pi_fifo_vc2_pop      : 1;
14942 		mmr_t	overflow_iilb_fifo_vc0_pop    : 1;
14943 		mmr_t	overflow_iilb_fifo_vc2_pop    : 1;
14944 		mmr_t	overflow_md_fifo_vc0_pop      : 1;
14945 		mmr_t	overflow_md_fifo_vc2_pop      : 1;
14946 		mmr_t	overflow_ni_fifo_vc0_pop      : 1;
14947 		mmr_t	overflow_ni_fifo_vc2_pop      : 1;
14948 		mmr_t	overflow_pi_fifo_vc0_push     : 1;
14949 		mmr_t	overflow_pi_fifo_vc2_push     : 1;
14950 		mmr_t	overflow_iilb_fifo_vc0_push   : 1;
14951 		mmr_t	overflow_iilb_fifo_vc2_push   : 1;
14952 		mmr_t	overflow_md_fifo_vc0_push     : 1;
14953 		mmr_t	overflow_md_fifo_vc2_push     : 1;
14954 		mmr_t	overflow_pi_fifo_vc0_credit   : 1;
14955 		mmr_t	overflow_pi_fifo_vc2_credit   : 1;
14956 		mmr_t	overflow_iilb_fifo_vc0_credit : 1;
14957 		mmr_t	overflow_iilb_fifo_vc2_credit : 1;
14958 		mmr_t	overflow_md_fifo_vc0_credit   : 1;
14959 		mmr_t	overflow_md_fifo_vc2_credit   : 1;
14960 		mmr_t	overflow_ni_fifo_vc0_credit   : 1;
14961 		mmr_t	overflow_ni_fifo_vc1_credit   : 1;
14962 		mmr_t	overflow_ni_fifo_vc2_credit   : 1;
14963 		mmr_t	overflow_ni_fifo_vc3_credit   : 1;
14964 		mmr_t	tail_timeout_fifo02_vc0       : 1;
14965 		mmr_t	tail_timeout_fifo02_vc2       : 1;
14966 		mmr_t	tail_timeout_fifo13_vc1       : 1;
14967 		mmr_t	tail_timeout_fifo13_vc3       : 1;
14968 		mmr_t	tail_timeout_ni_vc0           : 1;
14969 		mmr_t	tail_timeout_ni_vc1           : 1;
14970 		mmr_t	tail_timeout_ni_vc2           : 1;
14971 		mmr_t	tail_timeout_ni_vc3           : 1;
14976 	mmr_t	sh_ni1_error_overflow_1_regval;
14978 		mmr_t	tail_timeout_ni_vc3           : 1;
14979 		mmr_t	tail_timeout_ni_vc2           : 1;
14980 		mmr_t	tail_timeout_ni_vc1           : 1;
14981 		mmr_t	tail_timeout_ni_vc0           : 1;
14982 		mmr_t	tail_timeout_fifo13_vc3       : 1;
14983 		mmr_t	tail_timeout_fifo13_vc1       : 1;
14984 		mmr_t	tail_timeout_fifo02_vc2       : 1;
14985 		mmr_t	tail_timeout_fifo02_vc0       : 1;
14986 		mmr_t	overflow_ni_fifo_vc3_credit   : 1;
14987 		mmr_t	overflow_ni_fifo_vc2_credit   : 1;
14988 		mmr_t	overflow_ni_fifo_vc1_credit   : 1;
14989 		mmr_t	overflow_ni_fifo_vc0_credit   : 1;
14990 		mmr_t	overflow_md_fifo_vc2_credit   : 1;
14991 		mmr_t	overflow_md_fifo_vc0_credit   : 1;
14992 		mmr_t	overflow_iilb_fifo_vc2_credit : 1;
14993 		mmr_t	overflow_iilb_fifo_vc0_credit : 1;
14994 		mmr_t	overflow_pi_fifo_vc2_credit   : 1;
14995 		mmr_t	overflow_pi_fifo_vc0_credit   : 1;
14996 		mmr_t	overflow_md_fifo_vc2_push     : 1;
14997 		mmr_t	overflow_md_fifo_vc0_push     : 1;
14998 		mmr_t	overflow_iilb_fifo_vc2_push   : 1;
14999 		mmr_t	overflow_iilb_fifo_vc0_push   : 1;
15000 		mmr_t	overflow_pi_fifo_vc2_push     : 1;
15001 		mmr_t	overflow_pi_fifo_vc0_push     : 1;
15002 		mmr_t	overflow_ni_fifo_vc2_pop      : 1;
15003 		mmr_t	overflow_ni_fifo_vc0_pop      : 1;
15004 		mmr_t	overflow_md_fifo_vc2_pop      : 1;
15005 		mmr_t	overflow_md_fifo_vc0_pop      : 1;
15006 		mmr_t	overflow_iilb_fifo_vc2_pop    : 1;
15007 		mmr_t	overflow_iilb_fifo_vc0_pop    : 1;
15008 		mmr_t	overflow_pi_fifo_vc2_pop      : 1;
15009 		mmr_t	overflow_pi_fifo_vc0_pop      : 1;
15010 		mmr_t	overflow_ni_fifo_debit3       : 1;
15011 		mmr_t	overflow_ni_fifo_debit2       : 1;
15012 		mmr_t	overflow_ni_fifo_debit1       : 1;
15013 		mmr_t	overflow_ni_fifo_debit0       : 1;
15014 		mmr_t	overflow_md_fifo_debit2       : 1;
15015 		mmr_t	overflow_md_fifo_debit0       : 1;
15016 		mmr_t	overflow_iilb_fifo_debit2     : 1;
15017 		mmr_t	overflow_iilb_fifo_debit0     : 1;
15018 		mmr_t	overflow_pi_fifo_debit2       : 1;
15019 		mmr_t	overflow_pi_fifo_debit0       : 1;
15020 		mmr_t	overflow2_vc2_credit          : 1;
15021 		mmr_t	overflow1_vc2_credit          : 1;
15022 		mmr_t	overflow0_vc2_credit          : 1;
15023 		mmr_t	overflow2_vc0_credit          : 1;
15024 		mmr_t	overflow1_vc0_credit          : 1;
15025 		mmr_t	overflow0_vc0_credit          : 1;
15026 		mmr_t	overflow_fifo13_vc2_credit    : 1;
15027 		mmr_t	overflow_fifo13_vc0_credit    : 1;
15028 		mmr_t	overflow_fifo02_vc2_credit    : 1;
15029 		mmr_t	overflow_fifo02_vc0_credit    : 1;
15030 		mmr_t	overflow_fifo13_vc3_push      : 1;
15031 		mmr_t	overflow_fifo13_vc1_push      : 1;
15032 		mmr_t	overflow_fifo02_vc2_push      : 1;
15033 		mmr_t	overflow_fifo02_vc0_push      : 1;
15034 		mmr_t	overflow_fifo13_vc3_pop       : 1;
15035 		mmr_t	overflow_fifo13_vc1_pop       : 1;
15036 		mmr_t	overflow_fifo02_vc2_pop       : 1;
15037 		mmr_t	overflow_fifo02_vc0_pop       : 1;
15038 		mmr_t	overflow_fifo13_debit2        : 1;
15039 		mmr_t	overflow_fifo13_debit0        : 1;
15040 		mmr_t	overflow_fifo02_debit2        : 1;
15041 		mmr_t	overflow_fifo02_debit0        : 1;
15053 	mmr_t	sh_ni1_error_overflow_2_regval;
15055 		mmr_t	illegal_vcni                   : 1;
15056 		mmr_t	illegal_vcpi                   : 1;
15057 		mmr_t	illegal_vcmd                   : 1;
15058 		mmr_t	illegal_vciilb                 : 1;
15059 		mmr_t	underflow_fifo02_vc0_pop       : 1;
15060 		mmr_t	underflow_fifo02_vc2_pop       : 1;
15061 		mmr_t	underflow_fifo13_vc1_pop       : 1;
15062 		mmr_t	underflow_fifo13_vc3_pop       : 1;
15063 		mmr_t	underflow_fifo02_vc0_push      : 1;
15064 		mmr_t	underflow_fifo02_vc2_push      : 1;
15065 		mmr_t	underflow_fifo13_vc1_push      : 1;
15066 		mmr_t	underflow_fifo13_vc3_push      : 1;
15067 		mmr_t	underflow_fifo02_vc0_credit    : 1;
15068 		mmr_t	underflow_fifo02_vc2_credit    : 1;
15069 		mmr_t	underflow_fifo13_vc0_credit    : 1;
15070 		mmr_t	underflow_fifo13_vc2_credit    : 1;
15071 		mmr_t	underflow0_vc0_credit          : 1;
15072 		mmr_t	underflow1_vc0_credit          : 1;
15073 		mmr_t	underflow2_vc0_credit          : 1;
15074 		mmr_t	underflow0_vc2_credit          : 1;
15075 		mmr_t	underflow1_vc2_credit          : 1;
15076 		mmr_t	underflow2_vc2_credit          : 1;
15077 		mmr_t	reserved_0                     : 10;
15078 		mmr_t	underflow_pi_fifo_vc0_pop      : 1;
15079 		mmr_t	underflow_pi_fifo_vc2_pop      : 1;
15080 		mmr_t	underflow_iilb_fifo_vc0_pop    : 1;
15081 		mmr_t	underflow_iilb_fifo_vc2_pop    : 1;
15082 		mmr_t	underflow_md_fifo_vc0_pop      : 1;
15083 		mmr_t	underflow_md_fifo_vc2_pop      : 1;
15084 		mmr_t	underflow_ni_fifo_vc0_pop      : 1;
15085 		mmr_t	underflow_ni_fifo_vc2_pop      : 1;
15086 		mmr_t	underflow_pi_fifo_vc0_push     : 1;
15087 		mmr_t	underflow_pi_fifo_vc2_push     : 1;
15088 		mmr_t	underflow_iilb_fifo_vc0_push   : 1;
15089 		mmr_t	underflow_iilb_fifo_vc2_push   : 1;
15090 		mmr_t	underflow_md_fifo_vc0_push     : 1;
15091 		mmr_t	underflow_md_fifo_vc2_push     : 1;
15092 		mmr_t	underflow_pi_fifo_vc0_credit   : 1;
15093 		mmr_t	underflow_pi_fifo_vc2_credit   : 1;
15094 		mmr_t	underflow_iilb_fifo_vc0_credit : 1;
15095 		mmr_t	underflow_iilb_fifo_vc2_credit : 1;
15096 		mmr_t	underflow_md_fifo_vc0_credit   : 1;
15097 		mmr_t	underflow_md_fifo_vc2_credit   : 1;
15098 		mmr_t	underflow_ni_fifo_vc0_credit   : 1;
15099 		mmr_t	underflow_ni_fifo_vc1_credit   : 1;
15100 		mmr_t	underflow_ni_fifo_vc2_credit   : 1;
15101 		mmr_t	underflow_ni_fifo_vc3_credit   : 1;
15102 		mmr_t	llp_deadlock_vc0               : 1;
15103 		mmr_t	llp_deadlock_vc1               : 1;
15104 		mmr_t	llp_deadlock_vc2               : 1;
15105 		mmr_t	llp_deadlock_vc3               : 1;
15106 		mmr_t	chiplet_nomatch                : 1;
15107 		mmr_t	lut_read_error                 : 1;
15108 		mmr_t	retry_timeout_error            : 1;
15109 		mmr_t	reserved_1                     : 1;
15114 	mmr_t	sh_ni1_error_overflow_2_regval;
15116 		mmr_t	reserved_1                     : 1;
15117 		mmr_t	retry_timeout_error            : 1;
15118 		mmr_t	lut_read_error                 : 1;
15119 		mmr_t	chiplet_nomatch                : 1;
15120 		mmr_t	llp_deadlock_vc3               : 1;
15121 		mmr_t	llp_deadlock_vc2               : 1;
15122 		mmr_t	llp_deadlock_vc1               : 1;
15123 		mmr_t	llp_deadlock_vc0               : 1;
15124 		mmr_t	underflow_ni_fifo_vc3_credit   : 1;
15125 		mmr_t	underflow_ni_fifo_vc2_credit   : 1;
15126 		mmr_t	underflow_ni_fifo_vc1_credit   : 1;
15127 		mmr_t	underflow_ni_fifo_vc0_credit   : 1;
15128 		mmr_t	underflow_md_fifo_vc2_credit   : 1;
15129 		mmr_t	underflow_md_fifo_vc0_credit   : 1;
15130 		mmr_t	underflow_iilb_fifo_vc2_credit : 1;
15131 		mmr_t	underflow_iilb_fifo_vc0_credit : 1;
15132 		mmr_t	underflow_pi_fifo_vc2_credit   : 1;
15133 		mmr_t	underflow_pi_fifo_vc0_credit   : 1;
15134 		mmr_t	underflow_md_fifo_vc2_push     : 1;
15135 		mmr_t	underflow_md_fifo_vc0_push     : 1;
15136 		mmr_t	underflow_iilb_fifo_vc2_push   : 1;
15137 		mmr_t	underflow_iilb_fifo_vc0_push   : 1;
15138 		mmr_t	underflow_pi_fifo_vc2_push     : 1;
15139 		mmr_t	underflow_pi_fifo_vc0_push     : 1;
15140 		mmr_t	underflow_ni_fifo_vc2_pop      : 1;
15141 		mmr_t	underflow_ni_fifo_vc0_pop      : 1;
15142 		mmr_t	underflow_md_fifo_vc2_pop      : 1;
15143 		mmr_t	underflow_md_fifo_vc0_pop      : 1;
15144 		mmr_t	underflow_iilb_fifo_vc2_pop    : 1;
15145 		mmr_t	underflow_iilb_fifo_vc0_pop    : 1;
15146 		mmr_t	underflow_pi_fifo_vc2_pop      : 1;
15147 		mmr_t	underflow_pi_fifo_vc0_pop      : 1;
15148 		mmr_t	reserved_0                     : 10;
15149 		mmr_t	underflow2_vc2_credit          : 1;
15150 		mmr_t	underflow1_vc2_credit          : 1;
15151 		mmr_t	underflow0_vc2_credit          : 1;
15152 		mmr_t	underflow2_vc0_credit          : 1;
15153 		mmr_t	underflow1_vc0_credit          : 1;
15154 		mmr_t	underflow0_vc0_credit          : 1;
15155 		mmr_t	underflow_fifo13_vc2_credit    : 1;
15156 		mmr_t	underflow_fifo13_vc0_credit    : 1;
15157 		mmr_t	underflow_fifo02_vc2_credit    : 1;
15158 		mmr_t	underflow_fifo02_vc0_credit    : 1;
15159 		mmr_t	underflow_fifo13_vc3_push      : 1;
15160 		mmr_t	underflow_fifo13_vc1_push      : 1;
15161 		mmr_t	underflow_fifo02_vc2_push      : 1;
15162 		mmr_t	underflow_fifo02_vc0_push      : 1;
15163 		mmr_t	underflow_fifo13_vc3_pop       : 1;
15164 		mmr_t	underflow_fifo13_vc1_pop       : 1;
15165 		mmr_t	underflow_fifo02_vc2_pop       : 1;
15166 		mmr_t	underflow_fifo02_vc0_pop       : 1;
15167 		mmr_t	illegal_vciilb                 : 1;
15168 		mmr_t	illegal_vcmd                   : 1;
15169 		mmr_t	illegal_vcpi                   : 1;
15170 		mmr_t	illegal_vcni                   : 1;
15182 	mmr_t	sh_ni1_error_mask_1_regval;
15184 		mmr_t	overflow_fifo02_debit0        : 1;
15185 		mmr_t	overflow_fifo02_debit2        : 1;
15186 		mmr_t	overflow_fifo13_debit0        : 1;
15187 		mmr_t	overflow_fifo13_debit2        : 1;
15188 		mmr_t	overflow_fifo02_vc0_pop       : 1;
15189 		mmr_t	overflow_fifo02_vc2_pop       : 1;
15190 		mmr_t	overflow_fifo13_vc1_pop       : 1;
15191 		mmr_t	overflow_fifo13_vc3_pop       : 1;
15192 		mmr_t	overflow_fifo02_vc0_push      : 1;
15193 		mmr_t	overflow_fifo02_vc2_push      : 1;
15194 		mmr_t	overflow_fifo13_vc1_push      : 1;
15195 		mmr_t	overflow_fifo13_vc3_push      : 1;
15196 		mmr_t	overflow_fifo02_vc0_credit    : 1;
15197 		mmr_t	overflow_fifo02_vc2_credit    : 1;
15198 		mmr_t	overflow_fifo13_vc0_credit    : 1;
15199 		mmr_t	overflow_fifo13_vc2_credit    : 1;
15200 		mmr_t	overflow0_vc0_credit          : 1;
15201 		mmr_t	overflow1_vc0_credit          : 1;
15202 		mmr_t	overflow2_vc0_credit          : 1;
15203 		mmr_t	overflow0_vc2_credit          : 1;
15204 		mmr_t	overflow1_vc2_credit          : 1;
15205 		mmr_t	overflow2_vc2_credit          : 1;
15206 		mmr_t	overflow_pi_fifo_debit0       : 1;
15207 		mmr_t	overflow_pi_fifo_debit2       : 1;
15208 		mmr_t	overflow_iilb_fifo_debit0     : 1;
15209 		mmr_t	overflow_iilb_fifo_debit2     : 1;
15210 		mmr_t	overflow_md_fifo_debit0       : 1;
15211 		mmr_t	overflow_md_fifo_debit2       : 1;
15212 		mmr_t	overflow_ni_fifo_debit0       : 1;
15213 		mmr_t	overflow_ni_fifo_debit1       : 1;
15214 		mmr_t	overflow_ni_fifo_debit2       : 1;
15215 		mmr_t	overflow_ni_fifo_debit3       : 1;
15216 		mmr_t	overflow_pi_fifo_vc0_pop      : 1;
15217 		mmr_t	overflow_pi_fifo_vc2_pop      : 1;
15218 		mmr_t	overflow_iilb_fifo_vc0_pop    : 1;
15219 		mmr_t	overflow_iilb_fifo_vc2_pop    : 1;
15220 		mmr_t	overflow_md_fifo_vc0_pop      : 1;
15221 		mmr_t	overflow_md_fifo_vc2_pop      : 1;
15222 		mmr_t	overflow_ni_fifo_vc0_pop      : 1;
15223 		mmr_t	overflow_ni_fifo_vc2_pop      : 1;
15224 		mmr_t	overflow_pi_fifo_vc0_push     : 1;
15225 		mmr_t	overflow_pi_fifo_vc2_push     : 1;
15226 		mmr_t	overflow_iilb_fifo_vc0_push   : 1;
15227 		mmr_t	overflow_iilb_fifo_vc2_push   : 1;
15228 		mmr_t	overflow_md_fifo_vc0_push     : 1;
15229 		mmr_t	overflow_md_fifo_vc2_push     : 1;
15230 		mmr_t	overflow_pi_fifo_vc0_credit   : 1;
15231 		mmr_t	overflow_pi_fifo_vc2_credit   : 1;
15232 		mmr_t	overflow_iilb_fifo_vc0_credit : 1;
15233 		mmr_t	overflow_iilb_fifo_vc2_credit : 1;
15234 		mmr_t	overflow_md_fifo_vc0_credit   : 1;
15235 		mmr_t	overflow_md_fifo_vc2_credit   : 1;
15236 		mmr_t	overflow_ni_fifo_vc0_credit   : 1;
15237 		mmr_t	overflow_ni_fifo_vc1_credit   : 1;
15238 		mmr_t	overflow_ni_fifo_vc2_credit   : 1;
15239 		mmr_t	overflow_ni_fifo_vc3_credit   : 1;
15240 		mmr_t	tail_timeout_fifo02_vc0       : 1;
15241 		mmr_t	tail_timeout_fifo02_vc2       : 1;
15242 		mmr_t	tail_timeout_fifo13_vc1       : 1;
15243 		mmr_t	tail_timeout_fifo13_vc3       : 1;
15244 		mmr_t	tail_timeout_ni_vc0           : 1;
15245 		mmr_t	tail_timeout_ni_vc1           : 1;
15246 		mmr_t	tail_timeout_ni_vc2           : 1;
15247 		mmr_t	tail_timeout_ni_vc3           : 1;
15252 	mmr_t	sh_ni1_error_mask_1_regval;
15254 		mmr_t	tail_timeout_ni_vc3           : 1;
15255 		mmr_t	tail_timeout_ni_vc2           : 1;
15256 		mmr_t	tail_timeout_ni_vc1           : 1;
15257 		mmr_t	tail_timeout_ni_vc0           : 1;
15258 		mmr_t	tail_timeout_fifo13_vc3       : 1;
15259 		mmr_t	tail_timeout_fifo13_vc1       : 1;
15260 		mmr_t	tail_timeout_fifo02_vc2       : 1;
15261 		mmr_t	tail_timeout_fifo02_vc0       : 1;
15262 		mmr_t	overflow_ni_fifo_vc3_credit   : 1;
15263 		mmr_t	overflow_ni_fifo_vc2_credit   : 1;
15264 		mmr_t	overflow_ni_fifo_vc1_credit   : 1;
15265 		mmr_t	overflow_ni_fifo_vc0_credit   : 1;
15266 		mmr_t	overflow_md_fifo_vc2_credit   : 1;
15267 		mmr_t	overflow_md_fifo_vc0_credit   : 1;
15268 		mmr_t	overflow_iilb_fifo_vc2_credit : 1;
15269 		mmr_t	overflow_iilb_fifo_vc0_credit : 1;
15270 		mmr_t	overflow_pi_fifo_vc2_credit   : 1;
15271 		mmr_t	overflow_pi_fifo_vc0_credit   : 1;
15272 		mmr_t	overflow_md_fifo_vc2_push     : 1;
15273 		mmr_t	overflow_md_fifo_vc0_push     : 1;
15274 		mmr_t	overflow_iilb_fifo_vc2_push   : 1;
15275 		mmr_t	overflow_iilb_fifo_vc0_push   : 1;
15276 		mmr_t	overflow_pi_fifo_vc2_push     : 1;
15277 		mmr_t	overflow_pi_fifo_vc0_push     : 1;
15278 		mmr_t	overflow_ni_fifo_vc2_pop      : 1;
15279 		mmr_t	overflow_ni_fifo_vc0_pop      : 1;
15280 		mmr_t	overflow_md_fifo_vc2_pop      : 1;
15281 		mmr_t	overflow_md_fifo_vc0_pop      : 1;
15282 		mmr_t	overflow_iilb_fifo_vc2_pop    : 1;
15283 		mmr_t	overflow_iilb_fifo_vc0_pop    : 1;
15284 		mmr_t	overflow_pi_fifo_vc2_pop      : 1;
15285 		mmr_t	overflow_pi_fifo_vc0_pop      : 1;
15286 		mmr_t	overflow_ni_fifo_debit3       : 1;
15287 		mmr_t	overflow_ni_fifo_debit2       : 1;
15288 		mmr_t	overflow_ni_fifo_debit1       : 1;
15289 		mmr_t	overflow_ni_fifo_debit0       : 1;
15290 		mmr_t	overflow_md_fifo_debit2       : 1;
15291 		mmr_t	overflow_md_fifo_debit0       : 1;
15292 		mmr_t	overflow_iilb_fifo_debit2     : 1;
15293 		mmr_t	overflow_iilb_fifo_debit0     : 1;
15294 		mmr_t	overflow_pi_fifo_debit2       : 1;
15295 		mmr_t	overflow_pi_fifo_debit0       : 1;
15296 		mmr_t	overflow2_vc2_credit          : 1;
15297 		mmr_t	overflow1_vc2_credit          : 1;
15298 		mmr_t	overflow0_vc2_credit          : 1;
15299 		mmr_t	overflow2_vc0_credit          : 1;
15300 		mmr_t	overflow1_vc0_credit          : 1;
15301 		mmr_t	overflow0_vc0_credit          : 1;
15302 		mmr_t	overflow_fifo13_vc2_credit    : 1;
15303 		mmr_t	overflow_fifo13_vc0_credit    : 1;
15304 		mmr_t	overflow_fifo02_vc2_credit    : 1;
15305 		mmr_t	overflow_fifo02_vc0_credit    : 1;
15306 		mmr_t	overflow_fifo13_vc3_push      : 1;
15307 		mmr_t	overflow_fifo13_vc1_push      : 1;
15308 		mmr_t	overflow_fifo02_vc2_push      : 1;
15309 		mmr_t	overflow_fifo02_vc0_push      : 1;
15310 		mmr_t	overflow_fifo13_vc3_pop       : 1;
15311 		mmr_t	overflow_fifo13_vc1_pop       : 1;
15312 		mmr_t	overflow_fifo02_vc2_pop       : 1;
15313 		mmr_t	overflow_fifo02_vc0_pop       : 1;
15314 		mmr_t	overflow_fifo13_debit2        : 1;
15315 		mmr_t	overflow_fifo13_debit0        : 1;
15316 		mmr_t	overflow_fifo02_debit2        : 1;
15317 		mmr_t	overflow_fifo02_debit0        : 1;
15329 	mmr_t	sh_ni1_error_mask_2_regval;
15331 		mmr_t	illegal_vcni                   : 1;
15332 		mmr_t	illegal_vcpi                   : 1;
15333 		mmr_t	illegal_vcmd                   : 1;
15334 		mmr_t	illegal_vciilb                 : 1;
15335 		mmr_t	underflow_fifo02_vc0_pop       : 1;
15336 		mmr_t	underflow_fifo02_vc2_pop       : 1;
15337 		mmr_t	underflow_fifo13_vc1_pop       : 1;
15338 		mmr_t	underflow_fifo13_vc3_pop       : 1;
15339 		mmr_t	underflow_fifo02_vc0_push      : 1;
15340 		mmr_t	underflow_fifo02_vc2_push      : 1;
15341 		mmr_t	underflow_fifo13_vc1_push      : 1;
15342 		mmr_t	underflow_fifo13_vc3_push      : 1;
15343 		mmr_t	underflow_fifo02_vc0_credit    : 1;
15344 		mmr_t	underflow_fifo02_vc2_credit    : 1;
15345 		mmr_t	underflow_fifo13_vc0_credit    : 1;
15346 		mmr_t	underflow_fifo13_vc2_credit    : 1;
15347 		mmr_t	underflow0_vc0_credit          : 1;
15348 		mmr_t	underflow1_vc0_credit          : 1;
15349 		mmr_t	underflow2_vc0_credit          : 1;
15350 		mmr_t	underflow0_vc2_credit          : 1;
15351 		mmr_t	underflow1_vc2_credit          : 1;
15352 		mmr_t	underflow2_vc2_credit          : 1;
15353 		mmr_t	reserved_0                     : 10;
15354 		mmr_t	underflow_pi_fifo_vc0_pop      : 1;
15355 		mmr_t	underflow_pi_fifo_vc2_pop      : 1;
15356 		mmr_t	underflow_iilb_fifo_vc0_pop    : 1;
15357 		mmr_t	underflow_iilb_fifo_vc2_pop    : 1;
15358 		mmr_t	underflow_md_fifo_vc0_pop      : 1;
15359 		mmr_t	underflow_md_fifo_vc2_pop      : 1;
15360 		mmr_t	underflow_ni_fifo_vc0_pop      : 1;
15361 		mmr_t	underflow_ni_fifo_vc2_pop      : 1;
15362 		mmr_t	underflow_pi_fifo_vc0_push     : 1;
15363 		mmr_t	underflow_pi_fifo_vc2_push     : 1;
15364 		mmr_t	underflow_iilb_fifo_vc0_push   : 1;
15365 		mmr_t	underflow_iilb_fifo_vc2_push   : 1;
15366 		mmr_t	underflow_md_fifo_vc0_push     : 1;
15367 		mmr_t	underflow_md_fifo_vc2_push     : 1;
15368 		mmr_t	underflow_pi_fifo_vc0_credit   : 1;
15369 		mmr_t	underflow_pi_fifo_vc2_credit   : 1;
15370 		mmr_t	underflow_iilb_fifo_vc0_credit : 1;
15371 		mmr_t	underflow_iilb_fifo_vc2_credit : 1;
15372 		mmr_t	underflow_md_fifo_vc0_credit   : 1;
15373 		mmr_t	underflow_md_fifo_vc2_credit   : 1;
15374 		mmr_t	underflow_ni_fifo_vc0_credit   : 1;
15375 		mmr_t	underflow_ni_fifo_vc1_credit   : 1;
15376 		mmr_t	underflow_ni_fifo_vc2_credit   : 1;
15377 		mmr_t	underflow_ni_fifo_vc3_credit   : 1;
15378 		mmr_t	llp_deadlock_vc0               : 1;
15379 		mmr_t	llp_deadlock_vc1               : 1;
15380 		mmr_t	llp_deadlock_vc2               : 1;
15381 		mmr_t	llp_deadlock_vc3               : 1;
15382 		mmr_t	chiplet_nomatch                : 1;
15383 		mmr_t	lut_read_error                 : 1;
15384 		mmr_t	retry_timeout_error            : 1;
15385 		mmr_t	reserved_1                     : 1;
15390 	mmr_t	sh_ni1_error_mask_2_regval;
15392 		mmr_t	reserved_1                     : 1;
15393 		mmr_t	retry_timeout_error            : 1;
15394 		mmr_t	lut_read_error                 : 1;
15395 		mmr_t	chiplet_nomatch                : 1;
15396 		mmr_t	llp_deadlock_vc3               : 1;
15397 		mmr_t	llp_deadlock_vc2               : 1;
15398 		mmr_t	llp_deadlock_vc1               : 1;
15399 		mmr_t	llp_deadlock_vc0               : 1;
15400 		mmr_t	underflow_ni_fifo_vc3_credit   : 1;
15401 		mmr_t	underflow_ni_fifo_vc2_credit   : 1;
15402 		mmr_t	underflow_ni_fifo_vc1_credit   : 1;
15403 		mmr_t	underflow_ni_fifo_vc0_credit   : 1;
15404 		mmr_t	underflow_md_fifo_vc2_credit   : 1;
15405 		mmr_t	underflow_md_fifo_vc0_credit   : 1;
15406 		mmr_t	underflow_iilb_fifo_vc2_credit : 1;
15407 		mmr_t	underflow_iilb_fifo_vc0_credit : 1;
15408 		mmr_t	underflow_pi_fifo_vc2_credit   : 1;
15409 		mmr_t	underflow_pi_fifo_vc0_credit   : 1;
15410 		mmr_t	underflow_md_fifo_vc2_push     : 1;
15411 		mmr_t	underflow_md_fifo_vc0_push     : 1;
15412 		mmr_t	underflow_iilb_fifo_vc2_push   : 1;
15413 		mmr_t	underflow_iilb_fifo_vc0_push   : 1;
15414 		mmr_t	underflow_pi_fifo_vc2_push     : 1;
15415 		mmr_t	underflow_pi_fifo_vc0_push     : 1;
15416 		mmr_t	underflow_ni_fifo_vc2_pop      : 1;
15417 		mmr_t	underflow_ni_fifo_vc0_pop      : 1;
15418 		mmr_t	underflow_md_fifo_vc2_pop      : 1;
15419 		mmr_t	underflow_md_fifo_vc0_pop      : 1;
15420 		mmr_t	underflow_iilb_fifo_vc2_pop    : 1;
15421 		mmr_t	underflow_iilb_fifo_vc0_pop    : 1;
15422 		mmr_t	underflow_pi_fifo_vc2_pop      : 1;
15423 		mmr_t	underflow_pi_fifo_vc0_pop      : 1;
15424 		mmr_t	reserved_0                     : 10;
15425 		mmr_t	underflow2_vc2_credit          : 1;
15426 		mmr_t	underflow1_vc2_credit          : 1;
15427 		mmr_t	underflow0_vc2_credit          : 1;
15428 		mmr_t	underflow2_vc0_credit          : 1;
15429 		mmr_t	underflow1_vc0_credit          : 1;
15430 		mmr_t	underflow0_vc0_credit          : 1;
15431 		mmr_t	underflow_fifo13_vc2_credit    : 1;
15432 		mmr_t	underflow_fifo13_vc0_credit    : 1;
15433 		mmr_t	underflow_fifo02_vc2_credit    : 1;
15434 		mmr_t	underflow_fifo02_vc0_credit    : 1;
15435 		mmr_t	underflow_fifo13_vc3_push      : 1;
15436 		mmr_t	underflow_fifo13_vc1_push      : 1;
15437 		mmr_t	underflow_fifo02_vc2_push      : 1;
15438 		mmr_t	underflow_fifo02_vc0_push      : 1;
15439 		mmr_t	underflow_fifo13_vc3_pop       : 1;
15440 		mmr_t	underflow_fifo13_vc1_pop       : 1;
15441 		mmr_t	underflow_fifo02_vc2_pop       : 1;
15442 		mmr_t	underflow_fifo02_vc0_pop       : 1;
15443 		mmr_t	illegal_vciilb                 : 1;
15444 		mmr_t	illegal_vcmd                   : 1;
15445 		mmr_t	illegal_vcpi                   : 1;
15446 		mmr_t	illegal_vcni                   : 1;
15458 	mmr_t	sh_ni1_first_error_1_regval;
15460 		mmr_t	overflow_fifo02_debit0        : 1;
15461 		mmr_t	overflow_fifo02_debit2        : 1;
15462 		mmr_t	overflow_fifo13_debit0        : 1;
15463 		mmr_t	overflow_fifo13_debit2        : 1;
15464 		mmr_t	overflow_fifo02_vc0_pop       : 1;
15465 		mmr_t	overflow_fifo02_vc2_pop       : 1;
15466 		mmr_t	overflow_fifo13_vc1_pop       : 1;
15467 		mmr_t	overflow_fifo13_vc3_pop       : 1;
15468 		mmr_t	overflow_fifo02_vc0_push      : 1;
15469 		mmr_t	overflow_fifo02_vc2_push      : 1;
15470 		mmr_t	overflow_fifo13_vc1_push      : 1;
15471 		mmr_t	overflow_fifo13_vc3_push      : 1;
15472 		mmr_t	overflow_fifo02_vc0_credit    : 1;
15473 		mmr_t	overflow_fifo02_vc2_credit    : 1;
15474 		mmr_t	overflow_fifo13_vc0_credit    : 1;
15475 		mmr_t	overflow_fifo13_vc2_credit    : 1;
15476 		mmr_t	overflow0_vc0_credit          : 1;
15477 		mmr_t	overflow1_vc0_credit          : 1;
15478 		mmr_t	overflow2_vc0_credit          : 1;
15479 		mmr_t	overflow0_vc2_credit          : 1;
15480 		mmr_t	overflow1_vc2_credit          : 1;
15481 		mmr_t	overflow2_vc2_credit          : 1;
15482 		mmr_t	overflow_pi_fifo_debit0       : 1;
15483 		mmr_t	overflow_pi_fifo_debit2       : 1;
15484 		mmr_t	overflow_iilb_fifo_debit0     : 1;
15485 		mmr_t	overflow_iilb_fifo_debit2     : 1;
15486 		mmr_t	overflow_md_fifo_debit0       : 1;
15487 		mmr_t	overflow_md_fifo_debit2       : 1;
15488 		mmr_t	overflow_ni_fifo_debit0       : 1;
15489 		mmr_t	overflow_ni_fifo_debit1       : 1;
15490 		mmr_t	overflow_ni_fifo_debit2       : 1;
15491 		mmr_t	overflow_ni_fifo_debit3       : 1;
15492 		mmr_t	overflow_pi_fifo_vc0_pop      : 1;
15493 		mmr_t	overflow_pi_fifo_vc2_pop      : 1;
15494 		mmr_t	overflow_iilb_fifo_vc0_pop    : 1;
15495 		mmr_t	overflow_iilb_fifo_vc2_pop    : 1;
15496 		mmr_t	overflow_md_fifo_vc0_pop      : 1;
15497 		mmr_t	overflow_md_fifo_vc2_pop      : 1;
15498 		mmr_t	overflow_ni_fifo_vc0_pop      : 1;
15499 		mmr_t	overflow_ni_fifo_vc2_pop      : 1;
15500 		mmr_t	overflow_pi_fifo_vc0_push     : 1;
15501 		mmr_t	overflow_pi_fifo_vc2_push     : 1;
15502 		mmr_t	overflow_iilb_fifo_vc0_push   : 1;
15503 		mmr_t	overflow_iilb_fifo_vc2_push   : 1;
15504 		mmr_t	overflow_md_fifo_vc0_push     : 1;
15505 		mmr_t	overflow_md_fifo_vc2_push     : 1;
15506 		mmr_t	overflow_pi_fifo_vc0_credit   : 1;
15507 		mmr_t	overflow_pi_fifo_vc2_credit   : 1;
15508 		mmr_t	overflow_iilb_fifo_vc0_credit : 1;
15509 		mmr_t	overflow_iilb_fifo_vc2_credit : 1;
15510 		mmr_t	overflow_md_fifo_vc0_credit   : 1;
15511 		mmr_t	overflow_md_fifo_vc2_credit   : 1;
15512 		mmr_t	overflow_ni_fifo_vc0_credit   : 1;
15513 		mmr_t	overflow_ni_fifo_vc1_credit   : 1;
15514 		mmr_t	overflow_ni_fifo_vc2_credit   : 1;
15515 		mmr_t	overflow_ni_fifo_vc3_credit   : 1;
15516 		mmr_t	tail_timeout_fifo02_vc0       : 1;
15517 		mmr_t	tail_timeout_fifo02_vc2       : 1;
15518 		mmr_t	tail_timeout_fifo13_vc1       : 1;
15519 		mmr_t	tail_timeout_fifo13_vc3       : 1;
15520 		mmr_t	tail_timeout_ni_vc0           : 1;
15521 		mmr_t	tail_timeout_ni_vc1           : 1;
15522 		mmr_t	tail_timeout_ni_vc2           : 1;
15523 		mmr_t	tail_timeout_ni_vc3           : 1;
15528 	mmr_t	sh_ni1_first_error_1_regval;
15530 		mmr_t	tail_timeout_ni_vc3           : 1;
15531 		mmr_t	tail_timeout_ni_vc2           : 1;
15532 		mmr_t	tail_timeout_ni_vc1           : 1;
15533 		mmr_t	tail_timeout_ni_vc0           : 1;
15534 		mmr_t	tail_timeout_fifo13_vc3       : 1;
15535 		mmr_t	tail_timeout_fifo13_vc1       : 1;
15536 		mmr_t	tail_timeout_fifo02_vc2       : 1;
15537 		mmr_t	tail_timeout_fifo02_vc0       : 1;
15538 		mmr_t	overflow_ni_fifo_vc3_credit   : 1;
15539 		mmr_t	overflow_ni_fifo_vc2_credit   : 1;
15540 		mmr_t	overflow_ni_fifo_vc1_credit   : 1;
15541 		mmr_t	overflow_ni_fifo_vc0_credit   : 1;
15542 		mmr_t	overflow_md_fifo_vc2_credit   : 1;
15543 		mmr_t	overflow_md_fifo_vc0_credit   : 1;
15544 		mmr_t	overflow_iilb_fifo_vc2_credit : 1;
15545 		mmr_t	overflow_iilb_fifo_vc0_credit : 1;
15546 		mmr_t	overflow_pi_fifo_vc2_credit   : 1;
15547 		mmr_t	overflow_pi_fifo_vc0_credit   : 1;
15548 		mmr_t	overflow_md_fifo_vc2_push     : 1;
15549 		mmr_t	overflow_md_fifo_vc0_push     : 1;
15550 		mmr_t	overflow_iilb_fifo_vc2_push   : 1;
15551 		mmr_t	overflow_iilb_fifo_vc0_push   : 1;
15552 		mmr_t	overflow_pi_fifo_vc2_push     : 1;
15553 		mmr_t	overflow_pi_fifo_vc0_push     : 1;
15554 		mmr_t	overflow_ni_fifo_vc2_pop      : 1;
15555 		mmr_t	overflow_ni_fifo_vc0_pop      : 1;
15556 		mmr_t	overflow_md_fifo_vc2_pop      : 1;
15557 		mmr_t	overflow_md_fifo_vc0_pop      : 1;
15558 		mmr_t	overflow_iilb_fifo_vc2_pop    : 1;
15559 		mmr_t	overflow_iilb_fifo_vc0_pop    : 1;
15560 		mmr_t	overflow_pi_fifo_vc2_pop      : 1;
15561 		mmr_t	overflow_pi_fifo_vc0_pop      : 1;
15562 		mmr_t	overflow_ni_fifo_debit3       : 1;
15563 		mmr_t	overflow_ni_fifo_debit2       : 1;
15564 		mmr_t	overflow_ni_fifo_debit1       : 1;
15565 		mmr_t	overflow_ni_fifo_debit0       : 1;
15566 		mmr_t	overflow_md_fifo_debit2       : 1;
15567 		mmr_t	overflow_md_fifo_debit0       : 1;
15568 		mmr_t	overflow_iilb_fifo_debit2     : 1;
15569 		mmr_t	overflow_iilb_fifo_debit0     : 1;
15570 		mmr_t	overflow_pi_fifo_debit2       : 1;
15571 		mmr_t	overflow_pi_fifo_debit0       : 1;
15572 		mmr_t	overflow2_vc2_credit          : 1;
15573 		mmr_t	overflow1_vc2_credit          : 1;
15574 		mmr_t	overflow0_vc2_credit          : 1;
15575 		mmr_t	overflow2_vc0_credit          : 1;
15576 		mmr_t	overflow1_vc0_credit          : 1;
15577 		mmr_t	overflow0_vc0_credit          : 1;
15578 		mmr_t	overflow_fifo13_vc2_credit    : 1;
15579 		mmr_t	overflow_fifo13_vc0_credit    : 1;
15580 		mmr_t	overflow_fifo02_vc2_credit    : 1;
15581 		mmr_t	overflow_fifo02_vc0_credit    : 1;
15582 		mmr_t	overflow_fifo13_vc3_push      : 1;
15583 		mmr_t	overflow_fifo13_vc1_push      : 1;
15584 		mmr_t	overflow_fifo02_vc2_push      : 1;
15585 		mmr_t	overflow_fifo02_vc0_push      : 1;
15586 		mmr_t	overflow_fifo13_vc3_pop       : 1;
15587 		mmr_t	overflow_fifo13_vc1_pop       : 1;
15588 		mmr_t	overflow_fifo02_vc2_pop       : 1;
15589 		mmr_t	overflow_fifo02_vc0_pop       : 1;
15590 		mmr_t	overflow_fifo13_debit2        : 1;
15591 		mmr_t	overflow_fifo13_debit0        : 1;
15592 		mmr_t	overflow_fifo02_debit2        : 1;
15593 		mmr_t	overflow_fifo02_debit0        : 1;
15605 	mmr_t	sh_ni1_first_error_2_regval;
15607 		mmr_t	illegal_vcni                   : 1;
15608 		mmr_t	illegal_vcpi                   : 1;
15609 		mmr_t	illegal_vcmd                   : 1;
15610 		mmr_t	illegal_vciilb                 : 1;
15611 		mmr_t	underflow_fifo02_vc0_pop       : 1;
15612 		mmr_t	underflow_fifo02_vc2_pop       : 1;
15613 		mmr_t	underflow_fifo13_vc1_pop       : 1;
15614 		mmr_t	underflow_fifo13_vc3_pop       : 1;
15615 		mmr_t	underflow_fifo02_vc0_push      : 1;
15616 		mmr_t	underflow_fifo02_vc2_push      : 1;
15617 		mmr_t	underflow_fifo13_vc1_push      : 1;
15618 		mmr_t	underflow_fifo13_vc3_push      : 1;
15619 		mmr_t	underflow_fifo02_vc0_credit    : 1;
15620 		mmr_t	underflow_fifo02_vc2_credit    : 1;
15621 		mmr_t	underflow_fifo13_vc0_credit    : 1;
15622 		mmr_t	underflow_fifo13_vc2_credit    : 1;
15623 		mmr_t	underflow0_vc0_credit          : 1;
15624 		mmr_t	underflow1_vc0_credit          : 1;
15625 		mmr_t	underflow2_vc0_credit          : 1;
15626 		mmr_t	underflow0_vc2_credit          : 1;
15627 		mmr_t	underflow1_vc2_credit          : 1;
15628 		mmr_t	underflow2_vc2_credit          : 1;
15629 		mmr_t	reserved_0                     : 10;
15630 		mmr_t	underflow_pi_fifo_vc0_pop      : 1;
15631 		mmr_t	underflow_pi_fifo_vc2_pop      : 1;
15632 		mmr_t	underflow_iilb_fifo_vc0_pop    : 1;
15633 		mmr_t	underflow_iilb_fifo_vc2_pop    : 1;
15634 		mmr_t	underflow_md_fifo_vc0_pop      : 1;
15635 		mmr_t	underflow_md_fifo_vc2_pop      : 1;
15636 		mmr_t	underflow_ni_fifo_vc0_pop      : 1;
15637 		mmr_t	underflow_ni_fifo_vc2_pop      : 1;
15638 		mmr_t	underflow_pi_fifo_vc0_push     : 1;
15639 		mmr_t	underflow_pi_fifo_vc2_push     : 1;
15640 		mmr_t	underflow_iilb_fifo_vc0_push   : 1;
15641 		mmr_t	underflow_iilb_fifo_vc2_push   : 1;
15642 		mmr_t	underflow_md_fifo_vc0_push     : 1;
15643 		mmr_t	underflow_md_fifo_vc2_push     : 1;
15644 		mmr_t	underflow_pi_fifo_vc0_credit   : 1;
15645 		mmr_t	underflow_pi_fifo_vc2_credit   : 1;
15646 		mmr_t	underflow_iilb_fifo_vc0_credit : 1;
15647 		mmr_t	underflow_iilb_fifo_vc2_credit : 1;
15648 		mmr_t	underflow_md_fifo_vc0_credit   : 1;
15649 		mmr_t	underflow_md_fifo_vc2_credit   : 1;
15650 		mmr_t	underflow_ni_fifo_vc0_credit   : 1;
15651 		mmr_t	underflow_ni_fifo_vc1_credit   : 1;
15652 		mmr_t	underflow_ni_fifo_vc2_credit   : 1;
15653 		mmr_t	underflow_ni_fifo_vc3_credit   : 1;
15654 		mmr_t	llp_deadlock_vc0               : 1;
15655 		mmr_t	llp_deadlock_vc1               : 1;
15656 		mmr_t	llp_deadlock_vc2               : 1;
15657 		mmr_t	llp_deadlock_vc3               : 1;
15658 		mmr_t	chiplet_nomatch                : 1;
15659 		mmr_t	lut_read_error                 : 1;
15660 		mmr_t	retry_timeout_error            : 1;
15661 		mmr_t	reserved_1                     : 1;
15666 	mmr_t	sh_ni1_first_error_2_regval;
15668 		mmr_t	reserved_1                     : 1;
15669 		mmr_t	retry_timeout_error            : 1;
15670 		mmr_t	lut_read_error                 : 1;
15671 		mmr_t	chiplet_nomatch                : 1;
15672 		mmr_t	llp_deadlock_vc3               : 1;
15673 		mmr_t	llp_deadlock_vc2               : 1;
15674 		mmr_t	llp_deadlock_vc1               : 1;
15675 		mmr_t	llp_deadlock_vc0               : 1;
15676 		mmr_t	underflow_ni_fifo_vc3_credit   : 1;
15677 		mmr_t	underflow_ni_fifo_vc2_credit   : 1;
15678 		mmr_t	underflow_ni_fifo_vc1_credit   : 1;
15679 		mmr_t	underflow_ni_fifo_vc0_credit   : 1;
15680 		mmr_t	underflow_md_fifo_vc2_credit   : 1;
15681 		mmr_t	underflow_md_fifo_vc0_credit   : 1;
15682 		mmr_t	underflow_iilb_fifo_vc2_credit : 1;
15683 		mmr_t	underflow_iilb_fifo_vc0_credit : 1;
15684 		mmr_t	underflow_pi_fifo_vc2_credit   : 1;
15685 		mmr_t	underflow_pi_fifo_vc0_credit   : 1;
15686 		mmr_t	underflow_md_fifo_vc2_push     : 1;
15687 		mmr_t	underflow_md_fifo_vc0_push     : 1;
15688 		mmr_t	underflow_iilb_fifo_vc2_push   : 1;
15689 		mmr_t	underflow_iilb_fifo_vc0_push   : 1;
15690 		mmr_t	underflow_pi_fifo_vc2_push     : 1;
15691 		mmr_t	underflow_pi_fifo_vc0_push     : 1;
15692 		mmr_t	underflow_ni_fifo_vc2_pop      : 1;
15693 		mmr_t	underflow_ni_fifo_vc0_pop      : 1;
15694 		mmr_t	underflow_md_fifo_vc2_pop      : 1;
15695 		mmr_t	underflow_md_fifo_vc0_pop      : 1;
15696 		mmr_t	underflow_iilb_fifo_vc2_pop    : 1;
15697 		mmr_t	underflow_iilb_fifo_vc0_pop    : 1;
15698 		mmr_t	underflow_pi_fifo_vc2_pop      : 1;
15699 		mmr_t	underflow_pi_fifo_vc0_pop      : 1;
15700 		mmr_t	reserved_0                     : 10;
15701 		mmr_t	underflow2_vc2_credit          : 1;
15702 		mmr_t	underflow1_vc2_credit          : 1;
15703 		mmr_t	underflow0_vc2_credit          : 1;
15704 		mmr_t	underflow2_vc0_credit          : 1;
15705 		mmr_t	underflow1_vc0_credit          : 1;
15706 		mmr_t	underflow0_vc0_credit          : 1;
15707 		mmr_t	underflow_fifo13_vc2_credit    : 1;
15708 		mmr_t	underflow_fifo13_vc0_credit    : 1;
15709 		mmr_t	underflow_fifo02_vc2_credit    : 1;
15710 		mmr_t	underflow_fifo02_vc0_credit    : 1;
15711 		mmr_t	underflow_fifo13_vc3_push      : 1;
15712 		mmr_t	underflow_fifo13_vc1_push      : 1;
15713 		mmr_t	underflow_fifo02_vc2_push      : 1;
15714 		mmr_t	underflow_fifo02_vc0_push      : 1;
15715 		mmr_t	underflow_fifo13_vc3_pop       : 1;
15716 		mmr_t	underflow_fifo13_vc1_pop       : 1;
15717 		mmr_t	underflow_fifo02_vc2_pop       : 1;
15718 		mmr_t	underflow_fifo02_vc0_pop       : 1;
15719 		mmr_t	illegal_vciilb                 : 1;
15720 		mmr_t	illegal_vcmd                   : 1;
15721 		mmr_t	illegal_vcpi                   : 1;
15722 		mmr_t	illegal_vcni                   : 1;
15734 	mmr_t	sh_ni1_error_detail_1_regval;
15736 		mmr_t	header      : 64;
15741 	mmr_t	sh_ni1_error_detail_1_regval;
15743 		mmr_t	header      : 64;
15755 	mmr_t	sh_ni1_error_detail_2_regval;
15757 		mmr_t	header      : 64;
15762 	mmr_t	sh_ni1_error_detail_2_regval;
15764 		mmr_t	header      : 64;
15776 	mmr_t	sh_xn_corrected_detail_1_regval;
15778 		mmr_t	ecc0_syndrome : 8;
15779 		mmr_t	ecc0_wc       : 2;
15780 		mmr_t	ecc0_vc       : 2;
15781 		mmr_t	reserved_0    : 4;
15782 		mmr_t	ecc1_syndrome : 8;
15783 		mmr_t	ecc1_wc       : 2;
15784 		mmr_t	ecc1_vc       : 2;
15785 		mmr_t	reserved_1    : 4;
15786 		mmr_t	ecc2_syndrome : 8;
15787 		mmr_t	ecc2_wc       : 2;
15788 		mmr_t	ecc2_vc       : 2;
15789 		mmr_t	reserved_2    : 4;
15790 		mmr_t	ecc3_syndrome : 8;
15791 		mmr_t	ecc3_wc       : 2;
15792 		mmr_t	ecc3_vc       : 2;
15793 		mmr_t	reserved_3    : 4;
15798 	mmr_t	sh_xn_corrected_detail_1_regval;
15800 		mmr_t	reserved_3    : 4;
15801 		mmr_t	ecc3_vc       : 2;
15802 		mmr_t	ecc3_wc       : 2;
15803 		mmr_t	ecc3_syndrome : 8;
15804 		mmr_t	reserved_2    : 4;
15805 		mmr_t	ecc2_vc       : 2;
15806 		mmr_t	ecc2_wc       : 2;
15807 		mmr_t	ecc2_syndrome : 8;
15808 		mmr_t	reserved_1    : 4;
15809 		mmr_t	ecc1_vc       : 2;
15810 		mmr_t	ecc1_wc       : 2;
15811 		mmr_t	ecc1_syndrome : 8;
15812 		mmr_t	reserved_0    : 4;
15813 		mmr_t	ecc0_vc       : 2;
15814 		mmr_t	ecc0_wc       : 2;
15815 		mmr_t	ecc0_syndrome : 8;
15827 	mmr_t	sh_xn_corrected_detail_2_regval;
15829 		mmr_t	data        : 64;
15834 	mmr_t	sh_xn_corrected_detail_2_regval;
15836 		mmr_t	data        : 64;
15848 	mmr_t	sh_xn_corrected_detail_3_regval;
15850 		mmr_t	header0     : 64;
15855 	mmr_t	sh_xn_corrected_detail_3_regval;
15857 		mmr_t	header0     : 64;
15869 	mmr_t	sh_xn_corrected_detail_4_regval;
15871 		mmr_t	header1     : 42;
15872 		mmr_t	reserved_0  : 20;
15873 		mmr_t	err_group   : 2;
15878 	mmr_t	sh_xn_corrected_detail_4_regval;
15880 		mmr_t	err_group   : 2;
15881 		mmr_t	reserved_0  : 20;
15882 		mmr_t	header1     : 42;
15894 	mmr_t	sh_xn_uncorrected_detail_1_regval;
15896 		mmr_t	ecc0_syndrome : 8;
15897 		mmr_t	ecc0_wc       : 2;
15898 		mmr_t	ecc0_vc       : 2;
15899 		mmr_t	reserved_0    : 4;
15900 		mmr_t	ecc1_syndrome : 8;
15901 		mmr_t	ecc1_wc       : 2;
15902 		mmr_t	ecc1_vc       : 2;
15903 		mmr_t	reserved_1    : 4;
15904 		mmr_t	ecc2_syndrome : 8;
15905 		mmr_t	ecc2_wc       : 2;
15906 		mmr_t	ecc2_vc       : 2;
15907 		mmr_t	reserved_2    : 4;
15908 		mmr_t	ecc3_syndrome : 8;
15909 		mmr_t	ecc3_wc       : 2;
15910 		mmr_t	ecc3_vc       : 2;
15911 		mmr_t	reserved_3    : 4;
15916 	mmr_t	sh_xn_uncorrected_detail_1_regval;
15918 		mmr_t	reserved_3    : 4;
15919 		mmr_t	ecc3_vc       : 2;
15920 		mmr_t	ecc3_wc       : 2;
15921 		mmr_t	ecc3_syndrome : 8;
15922 		mmr_t	reserved_2    : 4;
15923 		mmr_t	ecc2_vc       : 2;
15924 		mmr_t	ecc2_wc       : 2;
15925 		mmr_t	ecc2_syndrome : 8;
15926 		mmr_t	reserved_1    : 4;
15927 		mmr_t	ecc1_vc       : 2;
15928 		mmr_t	ecc1_wc       : 2;
15929 		mmr_t	ecc1_syndrome : 8;
15930 		mmr_t	reserved_0    : 4;
15931 		mmr_t	ecc0_vc       : 2;
15932 		mmr_t	ecc0_wc       : 2;
15933 		mmr_t	ecc0_syndrome : 8;
15945 	mmr_t	sh_xn_uncorrected_detail_2_regval;
15947 		mmr_t	data        : 64;
15952 	mmr_t	sh_xn_uncorrected_detail_2_regval;
15954 		mmr_t	data        : 64;
15966 	mmr_t	sh_xn_uncorrected_detail_3_regval;
15968 		mmr_t	header0     : 64;
15973 	mmr_t	sh_xn_uncorrected_detail_3_regval;
15975 		mmr_t	header0     : 64;
15987 	mmr_t	sh_xn_uncorrected_detail_4_regval;
15989 		mmr_t	header1     : 42;
15990 		mmr_t	reserved_0  : 20;
15991 		mmr_t	err_group   : 2;
15996 	mmr_t	sh_xn_uncorrected_detail_4_regval;
15998 		mmr_t	err_group   : 2;
15999 		mmr_t	reserved_0  : 20;
16000 		mmr_t	header1     : 42;
16012 	mmr_t	sh_xnmd_error_detail_1_regval;
16014 		mmr_t	lut_addr    : 11;
16015 		mmr_t	reserved_0  : 53;
16020 	mmr_t	sh_xnmd_error_detail_1_regval;
16022 		mmr_t	reserved_0  : 53;
16023 		mmr_t	lut_addr    : 11;
16035 	mmr_t	sh_xnpi_error_detail_1_regval;
16037 		mmr_t	lut_addr    : 11;
16038 		mmr_t	reserved_0  : 53;
16043 	mmr_t	sh_xnpi_error_detail_1_regval;
16045 		mmr_t	reserved_0  : 53;
16046 		mmr_t	lut_addr    : 11;
16058 	mmr_t	sh_xniilb_error_detail_1_regval;
16060 		mmr_t	header      : 64;
16065 	mmr_t	sh_xniilb_error_detail_1_regval;
16067 		mmr_t	header      : 64;
16079 	mmr_t	sh_xniilb_error_detail_2_regval;
16081 		mmr_t	header      : 64;
16086 	mmr_t	sh_xniilb_error_detail_2_regval;
16088 		mmr_t	header      : 64;
16100 	mmr_t	sh_xniilb_error_detail_3_regval;
16102 		mmr_t	lut_addr    : 11;
16103 		mmr_t	reserved_0  : 53;
16108 	mmr_t	sh_xniilb_error_detail_3_regval;
16110 		mmr_t	reserved_0  : 53;
16111 		mmr_t	lut_addr    : 11;
16123 	mmr_t	sh_ni0_error_detail_3_regval;
16125 		mmr_t	lut_addr    : 11;
16126 		mmr_t	reserved_0  : 53;
16131 	mmr_t	sh_ni0_error_detail_3_regval;
16133 		mmr_t	reserved_0  : 53;
16134 		mmr_t	lut_addr    : 11;
16146 	mmr_t	sh_ni1_error_detail_3_regval;
16148 		mmr_t	lut_addr    : 11;
16149 		mmr_t	reserved_0  : 53;
16154 	mmr_t	sh_ni1_error_detail_3_regval;
16156 		mmr_t	reserved_0  : 53;
16157 		mmr_t	lut_addr    : 11;
16168 	mmr_t	sh_xn_error_summary_regval;
16170 		mmr_t	ni0_pop_overflow        : 1;
16171 		mmr_t	ni0_push_overflow       : 1;
16172 		mmr_t	ni0_credit_overflow     : 1;
16173 		mmr_t	ni0_debit_overflow      : 1;
16174 		mmr_t	ni0_pop_underflow       : 1;
16175 		mmr_t	ni0_push_underflow      : 1;
16176 		mmr_t	ni0_credit_underflow    : 1;
16177 		mmr_t	ni0_llp_error           : 1;
16178 		mmr_t	ni0_pipe_error          : 1;
16179 		mmr_t	ni1_pop_overflow        : 1;
16180 		mmr_t	ni1_push_overflow       : 1;
16181 		mmr_t	ni1_credit_overflow     : 1;
16182 		mmr_t	ni1_debit_overflow      : 1;
16183 		mmr_t	ni1_pop_underflow       : 1;
16184 		mmr_t	ni1_push_underflow      : 1;
16185 		mmr_t	ni1_credit_underflow    : 1;
16186 		mmr_t	ni1_llp_error           : 1;
16187 		mmr_t	ni1_pipe_error          : 1;
16188 		mmr_t	xnmd_credit_overflow    : 1;
16189 		mmr_t	xnmd_debit_overflow     : 1;
16190 		mmr_t	xnmd_data_buff_overflow : 1;
16191 		mmr_t	xnmd_credit_underflow   : 1;
16192 		mmr_t	xnmd_sbe_error          : 1;
16193 		mmr_t	xnmd_uce_error          : 1;
16194 		mmr_t	xnmd_lut_error          : 1;
16195 		mmr_t	xnpi_credit_overflow    : 1;
16196 		mmr_t	xnpi_debit_overflow     : 1;
16197 		mmr_t	xnpi_data_buff_overflow : 1;
16198 		mmr_t	xnpi_credit_underflow   : 1;
16199 		mmr_t	xnpi_sbe_error          : 1;
16200 		mmr_t	xnpi_uce_error          : 1;
16201 		mmr_t	xnpi_lut_error          : 1;
16202 		mmr_t	iilb_debit_overflow     : 1;
16203 		mmr_t	iilb_credit_overflow    : 1;
16204 		mmr_t	iilb_fifo_overflow      : 1;
16205 		mmr_t	iilb_credit_underflow   : 1;
16206 		mmr_t	iilb_fifo_underflow     : 1;
16207 		mmr_t	iilb_chiplet_or_lut     : 1;
16208 		mmr_t	reserved_0              : 26;
16213 	mmr_t	sh_xn_error_summary_regval;
16215 		mmr_t	reserved_0              : 26;
16216 		mmr_t	iilb_chiplet_or_lut     : 1;
16217 		mmr_t	iilb_fifo_underflow     : 1;
16218 		mmr_t	iilb_credit_underflow   : 1;
16219 		mmr_t	iilb_fifo_overflow      : 1;
16220 		mmr_t	iilb_credit_overflow    : 1;
16221 		mmr_t	iilb_debit_overflow     : 1;
16222 		mmr_t	xnpi_lut_error          : 1;
16223 		mmr_t	xnpi_uce_error          : 1;
16224 		mmr_t	xnpi_sbe_error          : 1;
16225 		mmr_t	xnpi_credit_underflow   : 1;
16226 		mmr_t	xnpi_data_buff_overflow : 1;
16227 		mmr_t	xnpi_debit_overflow     : 1;
16228 		mmr_t	xnpi_credit_overflow    : 1;
16229 		mmr_t	xnmd_lut_error          : 1;
16230 		mmr_t	xnmd_uce_error          : 1;
16231 		mmr_t	xnmd_sbe_error          : 1;
16232 		mmr_t	xnmd_credit_underflow   : 1;
16233 		mmr_t	xnmd_data_buff_overflow : 1;
16234 		mmr_t	xnmd_debit_overflow     : 1;
16235 		mmr_t	xnmd_credit_overflow    : 1;
16236 		mmr_t	ni1_pipe_error          : 1;
16237 		mmr_t	ni1_llp_error           : 1;
16238 		mmr_t	ni1_credit_underflow    : 1;
16239 		mmr_t	ni1_push_underflow      : 1;
16240 		mmr_t	ni1_pop_underflow       : 1;
16241 		mmr_t	ni1_debit_overflow      : 1;
16242 		mmr_t	ni1_credit_overflow     : 1;
16243 		mmr_t	ni1_push_overflow       : 1;
16244 		mmr_t	ni1_pop_overflow        : 1;
16245 		mmr_t	ni0_pipe_error          : 1;
16246 		mmr_t	ni0_llp_error           : 1;
16247 		mmr_t	ni0_credit_underflow    : 1;
16248 		mmr_t	ni0_push_underflow      : 1;
16249 		mmr_t	ni0_pop_underflow       : 1;
16250 		mmr_t	ni0_debit_overflow      : 1;
16251 		mmr_t	ni0_credit_overflow     : 1;
16252 		mmr_t	ni0_push_overflow       : 1;
16253 		mmr_t	ni0_pop_overflow        : 1;
16264 	mmr_t	sh_xn_error_overflow_regval;
16266 		mmr_t	ni0_pop_overflow        : 1;
16267 		mmr_t	ni0_push_overflow       : 1;
16268 		mmr_t	ni0_credit_overflow     : 1;
16269 		mmr_t	ni0_debit_overflow      : 1;
16270 		mmr_t	ni0_pop_underflow       : 1;
16271 		mmr_t	ni0_push_underflow      : 1;
16272 		mmr_t	ni0_credit_underflow    : 1;
16273 		mmr_t	ni0_llp_error           : 1;
16274 		mmr_t	ni0_pipe_error          : 1;
16275 		mmr_t	ni1_pop_overflow        : 1;
16276 		mmr_t	ni1_push_overflow       : 1;
16277 		mmr_t	ni1_credit_overflow     : 1;
16278 		mmr_t	ni1_debit_overflow      : 1;
16279 		mmr_t	ni1_pop_underflow       : 1;
16280 		mmr_t	ni1_push_underflow      : 1;
16281 		mmr_t	ni1_credit_underflow    : 1;
16282 		mmr_t	ni1_llp_error           : 1;
16283 		mmr_t	ni1_pipe_error          : 1;
16284 		mmr_t	xnmd_credit_overflow    : 1;
16285 		mmr_t	xnmd_debit_overflow     : 1;
16286 		mmr_t	xnmd_data_buff_overflow : 1;
16287 		mmr_t	xnmd_credit_underflow   : 1;
16288 		mmr_t	xnmd_sbe_error          : 1;
16289 		mmr_t	xnmd_uce_error          : 1;
16290 		mmr_t	xnmd_lut_error          : 1;
16291 		mmr_t	xnpi_credit_overflow    : 1;
16292 		mmr_t	xnpi_debit_overflow     : 1;
16293 		mmr_t	xnpi_data_buff_overflow : 1;
16294 		mmr_t	xnpi_credit_underflow   : 1;
16295 		mmr_t	xnpi_sbe_error          : 1;
16296 		mmr_t	xnpi_uce_error          : 1;
16297 		mmr_t	xnpi_lut_error          : 1;
16298 		mmr_t	iilb_debit_overflow     : 1;
16299 		mmr_t	iilb_credit_overflow    : 1;
16300 		mmr_t	iilb_fifo_overflow      : 1;
16301 		mmr_t	iilb_credit_underflow   : 1;
16302 		mmr_t	iilb_fifo_underflow     : 1;
16303 		mmr_t	iilb_chiplet_or_lut     : 1;
16304 		mmr_t	reserved_0              : 26;
16309 	mmr_t	sh_xn_error_overflow_regval;
16311 		mmr_t	reserved_0              : 26;
16312 		mmr_t	iilb_chiplet_or_lut     : 1;
16313 		mmr_t	iilb_fifo_underflow     : 1;
16314 		mmr_t	iilb_credit_underflow   : 1;
16315 		mmr_t	iilb_fifo_overflow      : 1;
16316 		mmr_t	iilb_credit_overflow    : 1;
16317 		mmr_t	iilb_debit_overflow     : 1;
16318 		mmr_t	xnpi_lut_error          : 1;
16319 		mmr_t	xnpi_uce_error          : 1;
16320 		mmr_t	xnpi_sbe_error          : 1;
16321 		mmr_t	xnpi_credit_underflow   : 1;
16322 		mmr_t	xnpi_data_buff_overflow : 1;
16323 		mmr_t	xnpi_debit_overflow     : 1;
16324 		mmr_t	xnpi_credit_overflow    : 1;
16325 		mmr_t	xnmd_lut_error          : 1;
16326 		mmr_t	xnmd_uce_error          : 1;
16327 		mmr_t	xnmd_sbe_error          : 1;
16328 		mmr_t	xnmd_credit_underflow   : 1;
16329 		mmr_t	xnmd_data_buff_overflow : 1;
16330 		mmr_t	xnmd_debit_overflow     : 1;
16331 		mmr_t	xnmd_credit_overflow    : 1;
16332 		mmr_t	ni1_pipe_error          : 1;
16333 		mmr_t	ni1_llp_error           : 1;
16334 		mmr_t	ni1_credit_underflow    : 1;
16335 		mmr_t	ni1_push_underflow      : 1;
16336 		mmr_t	ni1_pop_underflow       : 1;
16337 		mmr_t	ni1_debit_overflow      : 1;
16338 		mmr_t	ni1_credit_overflow     : 1;
16339 		mmr_t	ni1_push_overflow       : 1;
16340 		mmr_t	ni1_pop_overflow        : 1;
16341 		mmr_t	ni0_pipe_error          : 1;
16342 		mmr_t	ni0_llp_error           : 1;
16343 		mmr_t	ni0_credit_underflow    : 1;
16344 		mmr_t	ni0_push_underflow      : 1;
16345 		mmr_t	ni0_pop_underflow       : 1;
16346 		mmr_t	ni0_debit_overflow      : 1;
16347 		mmr_t	ni0_credit_overflow     : 1;
16348 		mmr_t	ni0_push_overflow       : 1;
16349 		mmr_t	ni0_pop_overflow        : 1;
16360 	mmr_t	sh_xn_error_mask_regval;
16362 		mmr_t	ni0_pop_overflow        : 1;
16363 		mmr_t	ni0_push_overflow       : 1;
16364 		mmr_t	ni0_credit_overflow     : 1;
16365 		mmr_t	ni0_debit_overflow      : 1;
16366 		mmr_t	ni0_pop_underflow       : 1;
16367 		mmr_t	ni0_push_underflow      : 1;
16368 		mmr_t	ni0_credit_underflow    : 1;
16369 		mmr_t	ni0_llp_error           : 1;
16370 		mmr_t	ni0_pipe_error          : 1;
16371 		mmr_t	ni1_pop_overflow        : 1;
16372 		mmr_t	ni1_push_overflow       : 1;
16373 		mmr_t	ni1_credit_overflow     : 1;
16374 		mmr_t	ni1_debit_overflow      : 1;
16375 		mmr_t	ni1_pop_underflow       : 1;
16376 		mmr_t	ni1_push_underflow      : 1;
16377 		mmr_t	ni1_credit_underflow    : 1;
16378 		mmr_t	ni1_llp_error           : 1;
16379 		mmr_t	ni1_pipe_error          : 1;
16380 		mmr_t	xnmd_credit_overflow    : 1;
16381 		mmr_t	xnmd_debit_overflow     : 1;
16382 		mmr_t	xnmd_data_buff_overflow : 1;
16383 		mmr_t	xnmd_credit_underflow   : 1;
16384 		mmr_t	xnmd_sbe_error          : 1;
16385 		mmr_t	xnmd_uce_error          : 1;
16386 		mmr_t	xnmd_lut_error          : 1;
16387 		mmr_t	xnpi_credit_overflow    : 1;
16388 		mmr_t	xnpi_debit_overflow     : 1;
16389 		mmr_t	xnpi_data_buff_overflow : 1;
16390 		mmr_t	xnpi_credit_underflow   : 1;
16391 		mmr_t	xnpi_sbe_error          : 1;
16392 		mmr_t	xnpi_uce_error          : 1;
16393 		mmr_t	xnpi_lut_error          : 1;
16394 		mmr_t	iilb_debit_overflow     : 1;
16395 		mmr_t	iilb_credit_overflow    : 1;
16396 		mmr_t	iilb_fifo_overflow      : 1;
16397 		mmr_t	iilb_credit_underflow   : 1;
16398 		mmr_t	iilb_fifo_underflow     : 1;
16399 		mmr_t	iilb_chiplet_or_lut     : 1;
16400 		mmr_t	reserved_0              : 26;
16405 	mmr_t	sh_xn_error_mask_regval;
16407 		mmr_t	reserved_0              : 26;
16408 		mmr_t	iilb_chiplet_or_lut     : 1;
16409 		mmr_t	iilb_fifo_underflow     : 1;
16410 		mmr_t	iilb_credit_underflow   : 1;
16411 		mmr_t	iilb_fifo_overflow      : 1;
16412 		mmr_t	iilb_credit_overflow    : 1;
16413 		mmr_t	iilb_debit_overflow     : 1;
16414 		mmr_t	xnpi_lut_error          : 1;
16415 		mmr_t	xnpi_uce_error          : 1;
16416 		mmr_t	xnpi_sbe_error          : 1;
16417 		mmr_t	xnpi_credit_underflow   : 1;
16418 		mmr_t	xnpi_data_buff_overflow : 1;
16419 		mmr_t	xnpi_debit_overflow     : 1;
16420 		mmr_t	xnpi_credit_overflow    : 1;
16421 		mmr_t	xnmd_lut_error          : 1;
16422 		mmr_t	xnmd_uce_error          : 1;
16423 		mmr_t	xnmd_sbe_error          : 1;
16424 		mmr_t	xnmd_credit_underflow   : 1;
16425 		mmr_t	xnmd_data_buff_overflow : 1;
16426 		mmr_t	xnmd_debit_overflow     : 1;
16427 		mmr_t	xnmd_credit_overflow    : 1;
16428 		mmr_t	ni1_pipe_error          : 1;
16429 		mmr_t	ni1_llp_error           : 1;
16430 		mmr_t	ni1_credit_underflow    : 1;
16431 		mmr_t	ni1_push_underflow      : 1;
16432 		mmr_t	ni1_pop_underflow       : 1;
16433 		mmr_t	ni1_debit_overflow      : 1;
16434 		mmr_t	ni1_credit_overflow     : 1;
16435 		mmr_t	ni1_push_overflow       : 1;
16436 		mmr_t	ni1_pop_overflow        : 1;
16437 		mmr_t	ni0_pipe_error          : 1;
16438 		mmr_t	ni0_llp_error           : 1;
16439 		mmr_t	ni0_credit_underflow    : 1;
16440 		mmr_t	ni0_push_underflow      : 1;
16441 		mmr_t	ni0_pop_underflow       : 1;
16442 		mmr_t	ni0_debit_overflow      : 1;
16443 		mmr_t	ni0_credit_overflow     : 1;
16444 		mmr_t	ni0_push_overflow       : 1;
16445 		mmr_t	ni0_pop_overflow        : 1;
16456 	mmr_t	sh_xn_first_error_regval;
16458 		mmr_t	ni0_pop_overflow        : 1;
16459 		mmr_t	ni0_push_overflow       : 1;
16460 		mmr_t	ni0_credit_overflow     : 1;
16461 		mmr_t	ni0_debit_overflow      : 1;
16462 		mmr_t	ni0_pop_underflow       : 1;
16463 		mmr_t	ni0_push_underflow      : 1;
16464 		mmr_t	ni0_credit_underflow    : 1;
16465 		mmr_t	ni0_llp_error           : 1;
16466 		mmr_t	ni0_pipe_error          : 1;
16467 		mmr_t	ni1_pop_overflow        : 1;
16468 		mmr_t	ni1_push_overflow       : 1;
16469 		mmr_t	ni1_credit_overflow     : 1;
16470 		mmr_t	ni1_debit_overflow      : 1;
16471 		mmr_t	ni1_pop_underflow       : 1;
16472 		mmr_t	ni1_push_underflow      : 1;
16473 		mmr_t	ni1_credit_underflow    : 1;
16474 		mmr_t	ni1_llp_error           : 1;
16475 		mmr_t	ni1_pipe_error          : 1;
16476 		mmr_t	xnmd_credit_overflow    : 1;
16477 		mmr_t	xnmd_debit_overflow     : 1;
16478 		mmr_t	xnmd_data_buff_overflow : 1;
16479 		mmr_t	xnmd_credit_underflow   : 1;
16480 		mmr_t	xnmd_sbe_error          : 1;
16481 		mmr_t	xnmd_uce_error          : 1;
16482 		mmr_t	xnmd_lut_error          : 1;
16483 		mmr_t	xnpi_credit_overflow    : 1;
16484 		mmr_t	xnpi_debit_overflow     : 1;
16485 		mmr_t	xnpi_data_buff_overflow : 1;
16486 		mmr_t	xnpi_credit_underflow   : 1;
16487 		mmr_t	xnpi_sbe_error          : 1;
16488 		mmr_t	xnpi_uce_error          : 1;
16489 		mmr_t	xnpi_lut_error          : 1;
16490 		mmr_t	iilb_debit_overflow     : 1;
16491 		mmr_t	iilb_credit_overflow    : 1;
16492 		mmr_t	iilb_fifo_overflow      : 1;
16493 		mmr_t	iilb_credit_underflow   : 1;
16494 		mmr_t	iilb_fifo_underflow     : 1;
16495 		mmr_t	iilb_chiplet_or_lut     : 1;
16496 		mmr_t	reserved_0              : 26;
16501 	mmr_t	sh_xn_first_error_regval;
16503 		mmr_t	reserved_0              : 26;
16504 		mmr_t	iilb_chiplet_or_lut     : 1;
16505 		mmr_t	iilb_fifo_underflow     : 1;
16506 		mmr_t	iilb_credit_underflow   : 1;
16507 		mmr_t	iilb_fifo_overflow      : 1;
16508 		mmr_t	iilb_credit_overflow    : 1;
16509 		mmr_t	iilb_debit_overflow     : 1;
16510 		mmr_t	xnpi_lut_error          : 1;
16511 		mmr_t	xnpi_uce_error          : 1;
16512 		mmr_t	xnpi_sbe_error          : 1;
16513 		mmr_t	xnpi_credit_underflow   : 1;
16514 		mmr_t	xnpi_data_buff_overflow : 1;
16515 		mmr_t	xnpi_debit_overflow     : 1;
16516 		mmr_t	xnpi_credit_overflow    : 1;
16517 		mmr_t	xnmd_lut_error          : 1;
16518 		mmr_t	xnmd_uce_error          : 1;
16519 		mmr_t	xnmd_sbe_error          : 1;
16520 		mmr_t	xnmd_credit_underflow   : 1;
16521 		mmr_t	xnmd_data_buff_overflow : 1;
16522 		mmr_t	xnmd_debit_overflow     : 1;
16523 		mmr_t	xnmd_credit_overflow    : 1;
16524 		mmr_t	ni1_pipe_error          : 1;
16525 		mmr_t	ni1_llp_error           : 1;
16526 		mmr_t	ni1_credit_underflow    : 1;
16527 		mmr_t	ni1_push_underflow      : 1;
16528 		mmr_t	ni1_pop_underflow       : 1;
16529 		mmr_t	ni1_debit_overflow      : 1;
16530 		mmr_t	ni1_credit_overflow     : 1;
16531 		mmr_t	ni1_push_overflow       : 1;
16532 		mmr_t	ni1_pop_overflow        : 1;
16533 		mmr_t	ni0_pipe_error          : 1;
16534 		mmr_t	ni0_llp_error           : 1;
16535 		mmr_t	ni0_credit_underflow    : 1;
16536 		mmr_t	ni0_push_underflow      : 1;
16537 		mmr_t	ni0_pop_underflow       : 1;
16538 		mmr_t	ni0_debit_overflow      : 1;
16539 		mmr_t	ni0_credit_overflow     : 1;
16540 		mmr_t	ni0_push_overflow       : 1;
16541 		mmr_t	ni0_pop_overflow        : 1;
16552 	mmr_t	sh_xniilb_error_summary_regval;
16554 		mmr_t	overflow_ii_debit0            : 1;
16555 		mmr_t	overflow_ii_debit2            : 1;
16556 		mmr_t	overflow_lb_debit0            : 1;
16557 		mmr_t	overflow_lb_debit2            : 1;
16558 		mmr_t	overflow_ii_vc0               : 1;
16559 		mmr_t	overflow_ii_vc2               : 1;
16560 		mmr_t	underflow_ii_vc0              : 1;
16561 		mmr_t	underflow_ii_vc2              : 1;
16562 		mmr_t	overflow_lb_vc0               : 1;
16563 		mmr_t	overflow_lb_vc2               : 1;
16564 		mmr_t	underflow_lb_vc0              : 1;
16565 		mmr_t	underflow_lb_vc2              : 1;
16566 		mmr_t	overflow_pi_vc0_credit_in     : 1;
16567 		mmr_t	overflow_iilb_vc0_credit_in   : 1;
16568 		mmr_t	overflow_md_vc0_credit_in     : 1;
16569 		mmr_t	overflow_ni0_vc0_credit_in    : 1;
16570 		mmr_t	overflow_ni1_vc0_credit_in    : 1;
16571 		mmr_t	overflow_pi_vc2_credit_in     : 1;
16572 		mmr_t	overflow_iilb_vc2_credit_in   : 1;
16573 		mmr_t	overflow_md_vc2_credit_in     : 1;
16574 		mmr_t	overflow_ni0_vc2_credit_in    : 1;
16575 		mmr_t	overflow_ni1_vc2_credit_in    : 1;
16576 		mmr_t	underflow_pi_vc0_credit_in    : 1;
16577 		mmr_t	underflow_iilb_vc0_credit_in  : 1;
16578 		mmr_t	underflow_md_vc0_credit_in    : 1;
16579 		mmr_t	underflow_ni0_vc0_credit_in   : 1;
16580 		mmr_t	underflow_ni1_vc0_credit_in   : 1;
16581 		mmr_t	underflow_pi_vc2_credit_in    : 1;
16582 		mmr_t	underflow_iilb_vc2_credit_in  : 1;
16583 		mmr_t	underflow_md_vc2_credit_in    : 1;
16584 		mmr_t	underflow_ni0_vc2_credit_in   : 1;
16585 		mmr_t	underflow_ni1_vc2_credit_in   : 1;
16586 		mmr_t	overflow_pi_debit0            : 1;
16587 		mmr_t	overflow_pi_debit2            : 1;
16588 		mmr_t	overflow_iilb_debit0          : 1;
16589 		mmr_t	overflow_iilb_debit2          : 1;
16590 		mmr_t	overflow_md_debit0            : 1;
16591 		mmr_t	overflow_md_debit2            : 1;
16592 		mmr_t	overflow_ni0_debit0           : 1;
16593 		mmr_t	overflow_ni0_debit2           : 1;
16594 		mmr_t	overflow_ni1_debit0           : 1;
16595 		mmr_t	overflow_ni1_debit2           : 1;
16596 		mmr_t	overflow_pi_vc0_credit_out    : 1;
16597 		mmr_t	overflow_pi_vc2_credit_out    : 1;
16598 		mmr_t	overflow_md_vc0_credit_out    : 1;
16599 		mmr_t	overflow_md_vc2_credit_out    : 1;
16600 		mmr_t	overflow_iilb_vc0_credit_out  : 1;
16601 		mmr_t	overflow_iilb_vc2_credit_out  : 1;
16602 		mmr_t	overflow_ni0_vc0_credit_out   : 1;
16603 		mmr_t	overflow_ni0_vc2_credit_out   : 1;
16604 		mmr_t	overflow_ni1_vc0_credit_out   : 1;
16605 		mmr_t	overflow_ni1_vc2_credit_out   : 1;
16606 		mmr_t	underflow_pi_vc0_credit_out   : 1;
16607 		mmr_t	underflow_pi_vc2_credit_out   : 1;
16608 		mmr_t	underflow_md_vc0_credit_out   : 1;
16609 		mmr_t	underflow_md_vc2_credit_out   : 1;
16610 		mmr_t	underflow_iilb_vc0_credit_out : 1;
16611 		mmr_t	underflow_iilb_vc2_credit_out : 1;
16612 		mmr_t	underflow_ni0_vc0_credit_out  : 1;
16613 		mmr_t	underflow_ni0_vc2_credit_out  : 1;
16614 		mmr_t	underflow_ni1_vc0_credit_out  : 1;
16615 		mmr_t	underflow_ni1_vc2_credit_out  : 1;
16616 		mmr_t	chiplet_nomatch               : 1;
16617 		mmr_t	lut_read_error                : 1;
16622 	mmr_t	sh_xniilb_error_summary_regval;
16624 		mmr_t	lut_read_error                : 1;
16625 		mmr_t	chiplet_nomatch               : 1;
16626 		mmr_t	underflow_ni1_vc2_credit_out  : 1;
16627 		mmr_t	underflow_ni1_vc0_credit_out  : 1;
16628 		mmr_t	underflow_ni0_vc2_credit_out  : 1;
16629 		mmr_t	underflow_ni0_vc0_credit_out  : 1;
16630 		mmr_t	underflow_iilb_vc2_credit_out : 1;
16631 		mmr_t	underflow_iilb_vc0_credit_out : 1;
16632 		mmr_t	underflow_md_vc2_credit_out   : 1;
16633 		mmr_t	underflow_md_vc0_credit_out   : 1;
16634 		mmr_t	underflow_pi_vc2_credit_out   : 1;
16635 		mmr_t	underflow_pi_vc0_credit_out   : 1;
16636 		mmr_t	overflow_ni1_vc2_credit_out   : 1;
16637 		mmr_t	overflow_ni1_vc0_credit_out   : 1;
16638 		mmr_t	overflow_ni0_vc2_credit_out   : 1;
16639 		mmr_t	overflow_ni0_vc0_credit_out   : 1;
16640 		mmr_t	overflow_iilb_vc2_credit_out  : 1;
16641 		mmr_t	overflow_iilb_vc0_credit_out  : 1;
16642 		mmr_t	overflow_md_vc2_credit_out    : 1;
16643 		mmr_t	overflow_md_vc0_credit_out    : 1;
16644 		mmr_t	overflow_pi_vc2_credit_out    : 1;
16645 		mmr_t	overflow_pi_vc0_credit_out    : 1;
16646 		mmr_t	overflow_ni1_debit2           : 1;
16647 		mmr_t	overflow_ni1_debit0           : 1;
16648 		mmr_t	overflow_ni0_debit2           : 1;
16649 		mmr_t	overflow_ni0_debit0           : 1;
16650 		mmr_t	overflow_md_debit2            : 1;
16651 		mmr_t	overflow_md_debit0            : 1;
16652 		mmr_t	overflow_iilb_debit2          : 1;
16653 		mmr_t	overflow_iilb_debit0          : 1;
16654 		mmr_t	overflow_pi_debit2            : 1;
16655 		mmr_t	overflow_pi_debit0            : 1;
16656 		mmr_t	underflow_ni1_vc2_credit_in   : 1;
16657 		mmr_t	underflow_ni0_vc2_credit_in   : 1;
16658 		mmr_t	underflow_md_vc2_credit_in    : 1;
16659 		mmr_t	underflow_iilb_vc2_credit_in  : 1;
16660 		mmr_t	underflow_pi_vc2_credit_in    : 1;
16661 		mmr_t	underflow_ni1_vc0_credit_in   : 1;
16662 		mmr_t	underflow_ni0_vc0_credit_in   : 1;
16663 		mmr_t	underflow_md_vc0_credit_in    : 1;
16664 		mmr_t	underflow_iilb_vc0_credit_in  : 1;
16665 		mmr_t	underflow_pi_vc0_credit_in    : 1;
16666 		mmr_t	overflow_ni1_vc2_credit_in    : 1;
16667 		mmr_t	overflow_ni0_vc2_credit_in    : 1;
16668 		mmr_t	overflow_md_vc2_credit_in     : 1;
16669 		mmr_t	overflow_iilb_vc2_credit_in   : 1;
16670 		mmr_t	overflow_pi_vc2_credit_in     : 1;
16671 		mmr_t	overflow_ni1_vc0_credit_in    : 1;
16672 		mmr_t	overflow_ni0_vc0_credit_in    : 1;
16673 		mmr_t	overflow_md_vc0_credit_in     : 1;
16674 		mmr_t	overflow_iilb_vc0_credit_in   : 1;
16675 		mmr_t	overflow_pi_vc0_credit_in     : 1;
16676 		mmr_t	underflow_lb_vc2              : 1;
16677 		mmr_t	underflow_lb_vc0              : 1;
16678 		mmr_t	overflow_lb_vc2               : 1;
16679 		mmr_t	overflow_lb_vc0               : 1;
16680 		mmr_t	underflow_ii_vc2              : 1;
16681 		mmr_t	underflow_ii_vc0              : 1;
16682 		mmr_t	overflow_ii_vc2               : 1;
16683 		mmr_t	overflow_ii_vc0               : 1;
16684 		mmr_t	overflow_lb_debit2            : 1;
16685 		mmr_t	overflow_lb_debit0            : 1;
16686 		mmr_t	overflow_ii_debit2            : 1;
16687 		mmr_t	overflow_ii_debit0            : 1;
16698 	mmr_t	sh_xniilb_error_overflow_regval;
16700 		mmr_t	overflow_ii_debit0            : 1;
16701 		mmr_t	overflow_ii_debit2            : 1;
16702 		mmr_t	overflow_lb_debit0            : 1;
16703 		mmr_t	overflow_lb_debit2            : 1;
16704 		mmr_t	overflow_ii_vc0               : 1;
16705 		mmr_t	overflow_ii_vc2               : 1;
16706 		mmr_t	underflow_ii_vc0              : 1;
16707 		mmr_t	underflow_ii_vc2              : 1;
16708 		mmr_t	overflow_lb_vc0               : 1;
16709 		mmr_t	overflow_lb_vc2               : 1;
16710 		mmr_t	underflow_lb_vc0              : 1;
16711 		mmr_t	underflow_lb_vc2              : 1;
16712 		mmr_t	overflow_pi_vc0_credit_in     : 1;
16713 		mmr_t	overflow_iilb_vc0_credit_in   : 1;
16714 		mmr_t	overflow_md_vc0_credit_in     : 1;
16715 		mmr_t	overflow_ni0_vc0_credit_in    : 1;
16716 		mmr_t	overflow_ni1_vc0_credit_in    : 1;
16717 		mmr_t	overflow_pi_vc2_credit_in     : 1;
16718 		mmr_t	overflow_iilb_vc2_credit_in   : 1;
16719 		mmr_t	overflow_md_vc2_credit_in     : 1;
16720 		mmr_t	overflow_ni0_vc2_credit_in    : 1;
16721 		mmr_t	overflow_ni1_vc2_credit_in    : 1;
16722 		mmr_t	underflow_pi_vc0_credit_in    : 1;
16723 		mmr_t	underflow_iilb_vc0_credit_in  : 1;
16724 		mmr_t	underflow_md_vc0_credit_in    : 1;
16725 		mmr_t	underflow_ni0_vc0_credit_in   : 1;
16726 		mmr_t	underflow_ni1_vc0_credit_in   : 1;
16727 		mmr_t	underflow_pi_vc2_credit_in    : 1;
16728 		mmr_t	underflow_iilb_vc2_credit_in  : 1;
16729 		mmr_t	underflow_md_vc2_credit_in    : 1;
16730 		mmr_t	underflow_ni0_vc2_credit_in   : 1;
16731 		mmr_t	underflow_ni1_vc2_credit_in   : 1;
16732 		mmr_t	overflow_pi_debit0            : 1;
16733 		mmr_t	overflow_pi_debit2            : 1;
16734 		mmr_t	overflow_iilb_debit0          : 1;
16735 		mmr_t	overflow_iilb_debit2          : 1;
16736 		mmr_t	overflow_md_debit0            : 1;
16737 		mmr_t	overflow_md_debit2            : 1;
16738 		mmr_t	overflow_ni0_debit0           : 1;
16739 		mmr_t	overflow_ni0_debit2           : 1;
16740 		mmr_t	overflow_ni1_debit0           : 1;
16741 		mmr_t	overflow_ni1_debit2           : 1;
16742 		mmr_t	overflow_pi_vc0_credit_out    : 1;
16743 		mmr_t	overflow_pi_vc2_credit_out    : 1;
16744 		mmr_t	overflow_md_vc0_credit_out    : 1;
16745 		mmr_t	overflow_md_vc2_credit_out    : 1;
16746 		mmr_t	overflow_iilb_vc0_credit_out  : 1;
16747 		mmr_t	overflow_iilb_vc2_credit_out  : 1;
16748 		mmr_t	overflow_ni0_vc0_credit_out   : 1;
16749 		mmr_t	overflow_ni0_vc2_credit_out   : 1;
16750 		mmr_t	overflow_ni1_vc0_credit_out   : 1;
16751 		mmr_t	overflow_ni1_vc2_credit_out   : 1;
16752 		mmr_t	underflow_pi_vc0_credit_out   : 1;
16753 		mmr_t	underflow_pi_vc2_credit_out   : 1;
16754 		mmr_t	underflow_md_vc0_credit_out   : 1;
16755 		mmr_t	underflow_md_vc2_credit_out   : 1;
16756 		mmr_t	underflow_iilb_vc0_credit_out : 1;
16757 		mmr_t	underflow_iilb_vc2_credit_out : 1;
16758 		mmr_t	underflow_ni0_vc0_credit_out  : 1;
16759 		mmr_t	underflow_ni0_vc2_credit_out  : 1;
16760 		mmr_t	underflow_ni1_vc0_credit_out  : 1;
16761 		mmr_t	underflow_ni1_vc2_credit_out  : 1;
16762 		mmr_t	chiplet_nomatch               : 1;
16763 		mmr_t	lut_read_error                : 1;
16768 	mmr_t	sh_xniilb_error_overflow_regval;
16770 		mmr_t	lut_read_error                : 1;
16771 		mmr_t	chiplet_nomatch               : 1;
16772 		mmr_t	underflow_ni1_vc2_credit_out  : 1;
16773 		mmr_t	underflow_ni1_vc0_credit_out  : 1;
16774 		mmr_t	underflow_ni0_vc2_credit_out  : 1;
16775 		mmr_t	underflow_ni0_vc0_credit_out  : 1;
16776 		mmr_t	underflow_iilb_vc2_credit_out : 1;
16777 		mmr_t	underflow_iilb_vc0_credit_out : 1;
16778 		mmr_t	underflow_md_vc2_credit_out   : 1;
16779 		mmr_t	underflow_md_vc0_credit_out   : 1;
16780 		mmr_t	underflow_pi_vc2_credit_out   : 1;
16781 		mmr_t	underflow_pi_vc0_credit_out   : 1;
16782 		mmr_t	overflow_ni1_vc2_credit_out   : 1;
16783 		mmr_t	overflow_ni1_vc0_credit_out   : 1;
16784 		mmr_t	overflow_ni0_vc2_credit_out   : 1;
16785 		mmr_t	overflow_ni0_vc0_credit_out   : 1;
16786 		mmr_t	overflow_iilb_vc2_credit_out  : 1;
16787 		mmr_t	overflow_iilb_vc0_credit_out  : 1;
16788 		mmr_t	overflow_md_vc2_credit_out    : 1;
16789 		mmr_t	overflow_md_vc0_credit_out    : 1;
16790 		mmr_t	overflow_pi_vc2_credit_out    : 1;
16791 		mmr_t	overflow_pi_vc0_credit_out    : 1;
16792 		mmr_t	overflow_ni1_debit2           : 1;
16793 		mmr_t	overflow_ni1_debit0           : 1;
16794 		mmr_t	overflow_ni0_debit2           : 1;
16795 		mmr_t	overflow_ni0_debit0           : 1;
16796 		mmr_t	overflow_md_debit2            : 1;
16797 		mmr_t	overflow_md_debit0            : 1;
16798 		mmr_t	overflow_iilb_debit2          : 1;
16799 		mmr_t	overflow_iilb_debit0          : 1;
16800 		mmr_t	overflow_pi_debit2            : 1;
16801 		mmr_t	overflow_pi_debit0            : 1;
16802 		mmr_t	underflow_ni1_vc2_credit_in   : 1;
16803 		mmr_t	underflow_ni0_vc2_credit_in   : 1;
16804 		mmr_t	underflow_md_vc2_credit_in    : 1;
16805 		mmr_t	underflow_iilb_vc2_credit_in  : 1;
16806 		mmr_t	underflow_pi_vc2_credit_in    : 1;
16807 		mmr_t	underflow_ni1_vc0_credit_in   : 1;
16808 		mmr_t	underflow_ni0_vc0_credit_in   : 1;
16809 		mmr_t	underflow_md_vc0_credit_in    : 1;
16810 		mmr_t	underflow_iilb_vc0_credit_in  : 1;
16811 		mmr_t	underflow_pi_vc0_credit_in    : 1;
16812 		mmr_t	overflow_ni1_vc2_credit_in    : 1;
16813 		mmr_t	overflow_ni0_vc2_credit_in    : 1;
16814 		mmr_t	overflow_md_vc2_credit_in     : 1;
16815 		mmr_t	overflow_iilb_vc2_credit_in   : 1;
16816 		mmr_t	overflow_pi_vc2_credit_in     : 1;
16817 		mmr_t	overflow_ni1_vc0_credit_in    : 1;
16818 		mmr_t	overflow_ni0_vc0_credit_in    : 1;
16819 		mmr_t	overflow_md_vc0_credit_in     : 1;
16820 		mmr_t	overflow_iilb_vc0_credit_in   : 1;
16821 		mmr_t	overflow_pi_vc0_credit_in     : 1;
16822 		mmr_t	underflow_lb_vc2              : 1;
16823 		mmr_t	underflow_lb_vc0              : 1;
16824 		mmr_t	overflow_lb_vc2               : 1;
16825 		mmr_t	overflow_lb_vc0               : 1;
16826 		mmr_t	underflow_ii_vc2              : 1;
16827 		mmr_t	underflow_ii_vc0              : 1;
16828 		mmr_t	overflow_ii_vc2               : 1;
16829 		mmr_t	overflow_ii_vc0               : 1;
16830 		mmr_t	overflow_lb_debit2            : 1;
16831 		mmr_t	overflow_lb_debit0            : 1;
16832 		mmr_t	overflow_ii_debit2            : 1;
16833 		mmr_t	overflow_ii_debit0            : 1;
16844 	mmr_t	sh_xniilb_error_mask_regval;
16846 		mmr_t	overflow_ii_debit0            : 1;
16847 		mmr_t	overflow_ii_debit2            : 1;
16848 		mmr_t	overflow_lb_debit0            : 1;
16849 		mmr_t	overflow_lb_debit2            : 1;
16850 		mmr_t	overflow_ii_vc0               : 1;
16851 		mmr_t	overflow_ii_vc2               : 1;
16852 		mmr_t	underflow_ii_vc0              : 1;
16853 		mmr_t	underflow_ii_vc2              : 1;
16854 		mmr_t	overflow_lb_vc0               : 1;
16855 		mmr_t	overflow_lb_vc2               : 1;
16856 		mmr_t	underflow_lb_vc0              : 1;
16857 		mmr_t	underflow_lb_vc2              : 1;
16858 		mmr_t	overflow_pi_vc0_credit_in     : 1;
16859 		mmr_t	overflow_iilb_vc0_credit_in   : 1;
16860 		mmr_t	overflow_md_vc0_credit_in     : 1;
16861 		mmr_t	overflow_ni0_vc0_credit_in    : 1;
16862 		mmr_t	overflow_ni1_vc0_credit_in    : 1;
16863 		mmr_t	overflow_pi_vc2_credit_in     : 1;
16864 		mmr_t	overflow_iilb_vc2_credit_in   : 1;
16865 		mmr_t	overflow_md_vc2_credit_in     : 1;
16866 		mmr_t	overflow_ni0_vc2_credit_in    : 1;
16867 		mmr_t	overflow_ni1_vc2_credit_in    : 1;
16868 		mmr_t	underflow_pi_vc0_credit_in    : 1;
16869 		mmr_t	underflow_iilb_vc0_credit_in  : 1;
16870 		mmr_t	underflow_md_vc0_credit_in    : 1;
16871 		mmr_t	underflow_ni0_vc0_credit_in   : 1;
16872 		mmr_t	underflow_ni1_vc0_credit_in   : 1;
16873 		mmr_t	underflow_pi_vc2_credit_in    : 1;
16874 		mmr_t	underflow_iilb_vc2_credit_in  : 1;
16875 		mmr_t	underflow_md_vc2_credit_in    : 1;
16876 		mmr_t	underflow_ni0_vc2_credit_in   : 1;
16877 		mmr_t	underflow_ni1_vc2_credit_in   : 1;
16878 		mmr_t	overflow_pi_debit0            : 1;
16879 		mmr_t	overflow_pi_debit2            : 1;
16880 		mmr_t	overflow_iilb_debit0          : 1;
16881 		mmr_t	overflow_iilb_debit2          : 1;
16882 		mmr_t	overflow_md_debit0            : 1;
16883 		mmr_t	overflow_md_debit2            : 1;
16884 		mmr_t	overflow_ni0_debit0           : 1;
16885 		mmr_t	overflow_ni0_debit2           : 1;
16886 		mmr_t	overflow_ni1_debit0           : 1;
16887 		mmr_t	overflow_ni1_debit2           : 1;
16888 		mmr_t	overflow_pi_vc0_credit_out    : 1;
16889 		mmr_t	overflow_pi_vc2_credit_out    : 1;
16890 		mmr_t	overflow_md_vc0_credit_out    : 1;
16891 		mmr_t	overflow_md_vc2_credit_out    : 1;
16892 		mmr_t	overflow_iilb_vc0_credit_out  : 1;
16893 		mmr_t	overflow_iilb_vc2_credit_out  : 1;
16894 		mmr_t	overflow_ni0_vc0_credit_out   : 1;
16895 		mmr_t	overflow_ni0_vc2_credit_out   : 1;
16896 		mmr_t	overflow_ni1_vc0_credit_out   : 1;
16897 		mmr_t	overflow_ni1_vc2_credit_out   : 1;
16898 		mmr_t	underflow_pi_vc0_credit_out   : 1;
16899 		mmr_t	underflow_pi_vc2_credit_out   : 1;
16900 		mmr_t	underflow_md_vc0_credit_out   : 1;
16901 		mmr_t	underflow_md_vc2_credit_out   : 1;
16902 		mmr_t	underflow_iilb_vc0_credit_out : 1;
16903 		mmr_t	underflow_iilb_vc2_credit_out : 1;
16904 		mmr_t	underflow_ni0_vc0_credit_out  : 1;
16905 		mmr_t	underflow_ni0_vc2_credit_out  : 1;
16906 		mmr_t	underflow_ni1_vc0_credit_out  : 1;
16907 		mmr_t	underflow_ni1_vc2_credit_out  : 1;
16908 		mmr_t	chiplet_nomatch               : 1;
16909 		mmr_t	lut_read_error                : 1;
16914 	mmr_t	sh_xniilb_error_mask_regval;
16916 		mmr_t	lut_read_error                : 1;
16917 		mmr_t	chiplet_nomatch               : 1;
16918 		mmr_t	underflow_ni1_vc2_credit_out  : 1;
16919 		mmr_t	underflow_ni1_vc0_credit_out  : 1;
16920 		mmr_t	underflow_ni0_vc2_credit_out  : 1;
16921 		mmr_t	underflow_ni0_vc0_credit_out  : 1;
16922 		mmr_t	underflow_iilb_vc2_credit_out : 1;
16923 		mmr_t	underflow_iilb_vc0_credit_out : 1;
16924 		mmr_t	underflow_md_vc2_credit_out   : 1;
16925 		mmr_t	underflow_md_vc0_credit_out   : 1;
16926 		mmr_t	underflow_pi_vc2_credit_out   : 1;
16927 		mmr_t	underflow_pi_vc0_credit_out   : 1;
16928 		mmr_t	overflow_ni1_vc2_credit_out   : 1;
16929 		mmr_t	overflow_ni1_vc0_credit_out   : 1;
16930 		mmr_t	overflow_ni0_vc2_credit_out   : 1;
16931 		mmr_t	overflow_ni0_vc0_credit_out   : 1;
16932 		mmr_t	overflow_iilb_vc2_credit_out  : 1;
16933 		mmr_t	overflow_iilb_vc0_credit_out  : 1;
16934 		mmr_t	overflow_md_vc2_credit_out    : 1;
16935 		mmr_t	overflow_md_vc0_credit_out    : 1;
16936 		mmr_t	overflow_pi_vc2_credit_out    : 1;
16937 		mmr_t	overflow_pi_vc0_credit_out    : 1;
16938 		mmr_t	overflow_ni1_debit2           : 1;
16939 		mmr_t	overflow_ni1_debit0           : 1;
16940 		mmr_t	overflow_ni0_debit2           : 1;
16941 		mmr_t	overflow_ni0_debit0           : 1;
16942 		mmr_t	overflow_md_debit2            : 1;
16943 		mmr_t	overflow_md_debit0            : 1;
16944 		mmr_t	overflow_iilb_debit2          : 1;
16945 		mmr_t	overflow_iilb_debit0          : 1;
16946 		mmr_t	overflow_pi_debit2            : 1;
16947 		mmr_t	overflow_pi_debit0            : 1;
16948 		mmr_t	underflow_ni1_vc2_credit_in   : 1;
16949 		mmr_t	underflow_ni0_vc2_credit_in   : 1;
16950 		mmr_t	underflow_md_vc2_credit_in    : 1;
16951 		mmr_t	underflow_iilb_vc2_credit_in  : 1;
16952 		mmr_t	underflow_pi_vc2_credit_in    : 1;
16953 		mmr_t	underflow_ni1_vc0_credit_in   : 1;
16954 		mmr_t	underflow_ni0_vc0_credit_in   : 1;
16955 		mmr_t	underflow_md_vc0_credit_in    : 1;
16956 		mmr_t	underflow_iilb_vc0_credit_in  : 1;
16957 		mmr_t	underflow_pi_vc0_credit_in    : 1;
16958 		mmr_t	overflow_ni1_vc2_credit_in    : 1;
16959 		mmr_t	overflow_ni0_vc2_credit_in    : 1;
16960 		mmr_t	overflow_md_vc2_credit_in     : 1;
16961 		mmr_t	overflow_iilb_vc2_credit_in   : 1;
16962 		mmr_t	overflow_pi_vc2_credit_in     : 1;
16963 		mmr_t	overflow_ni1_vc0_credit_in    : 1;
16964 		mmr_t	overflow_ni0_vc0_credit_in    : 1;
16965 		mmr_t	overflow_md_vc0_credit_in     : 1;
16966 		mmr_t	overflow_iilb_vc0_credit_in   : 1;
16967 		mmr_t	overflow_pi_vc0_credit_in     : 1;
16968 		mmr_t	underflow_lb_vc2              : 1;
16969 		mmr_t	underflow_lb_vc0              : 1;
16970 		mmr_t	overflow_lb_vc2               : 1;
16971 		mmr_t	overflow_lb_vc0               : 1;
16972 		mmr_t	underflow_ii_vc2              : 1;
16973 		mmr_t	underflow_ii_vc0              : 1;
16974 		mmr_t	overflow_ii_vc2               : 1;
16975 		mmr_t	overflow_ii_vc0               : 1;
16976 		mmr_t	overflow_lb_debit2            : 1;
16977 		mmr_t	overflow_lb_debit0            : 1;
16978 		mmr_t	overflow_ii_debit2            : 1;
16979 		mmr_t	overflow_ii_debit0            : 1;
16990 	mmr_t	sh_xniilb_first_error_regval;
16992 		mmr_t	overflow_ii_debit0            : 1;
16993 		mmr_t	overflow_ii_debit2            : 1;
16994 		mmr_t	overflow_lb_debit0            : 1;
16995 		mmr_t	overflow_lb_debit2            : 1;
16996 		mmr_t	overflow_ii_vc0               : 1;
16997 		mmr_t	overflow_ii_vc2               : 1;
16998 		mmr_t	underflow_ii_vc0              : 1;
16999 		mmr_t	underflow_ii_vc2              : 1;
17000 		mmr_t	overflow_lb_vc0               : 1;
17001 		mmr_t	overflow_lb_vc2               : 1;
17002 		mmr_t	underflow_lb_vc0              : 1;
17003 		mmr_t	underflow_lb_vc2              : 1;
17004 		mmr_t	overflow_pi_vc0_credit_in     : 1;
17005 		mmr_t	overflow_iilb_vc0_credit_in   : 1;
17006 		mmr_t	overflow_md_vc0_credit_in     : 1;
17007 		mmr_t	overflow_ni0_vc0_credit_in    : 1;
17008 		mmr_t	overflow_ni1_vc0_credit_in    : 1;
17009 		mmr_t	overflow_pi_vc2_credit_in     : 1;
17010 		mmr_t	overflow_iilb_vc2_credit_in   : 1;
17011 		mmr_t	overflow_md_vc2_credit_in     : 1;
17012 		mmr_t	overflow_ni0_vc2_credit_in    : 1;
17013 		mmr_t	overflow_ni1_vc2_credit_in    : 1;
17014 		mmr_t	underflow_pi_vc0_credit_in    : 1;
17015 		mmr_t	underflow_iilb_vc0_credit_in  : 1;
17016 		mmr_t	underflow_md_vc0_credit_in    : 1;
17017 		mmr_t	underflow_ni0_vc0_credit_in   : 1;
17018 		mmr_t	underflow_ni1_vc0_credit_in   : 1;
17019 		mmr_t	underflow_pi_vc2_credit_in    : 1;
17020 		mmr_t	underflow_iilb_vc2_credit_in  : 1;
17021 		mmr_t	underflow_md_vc2_credit_in    : 1;
17022 		mmr_t	underflow_ni0_vc2_credit_in   : 1;
17023 		mmr_t	underflow_ni1_vc2_credit_in   : 1;
17024 		mmr_t	overflow_pi_debit0            : 1;
17025 		mmr_t	overflow_pi_debit2            : 1;
17026 		mmr_t	overflow_iilb_debit0          : 1;
17027 		mmr_t	overflow_iilb_debit2          : 1;
17028 		mmr_t	overflow_md_debit0            : 1;
17029 		mmr_t	overflow_md_debit2            : 1;
17030 		mmr_t	overflow_ni0_debit0           : 1;
17031 		mmr_t	overflow_ni0_debit2           : 1;
17032 		mmr_t	overflow_ni1_debit0           : 1;
17033 		mmr_t	overflow_ni1_debit2           : 1;
17034 		mmr_t	overflow_pi_vc0_credit_out    : 1;
17035 		mmr_t	overflow_pi_vc2_credit_out    : 1;
17036 		mmr_t	overflow_md_vc0_credit_out    : 1;
17037 		mmr_t	overflow_md_vc2_credit_out    : 1;
17038 		mmr_t	overflow_iilb_vc0_credit_out  : 1;
17039 		mmr_t	overflow_iilb_vc2_credit_out  : 1;
17040 		mmr_t	overflow_ni0_vc0_credit_out   : 1;
17041 		mmr_t	overflow_ni0_vc2_credit_out   : 1;
17042 		mmr_t	overflow_ni1_vc0_credit_out   : 1;
17043 		mmr_t	overflow_ni1_vc2_credit_out   : 1;
17044 		mmr_t	underflow_pi_vc0_credit_out   : 1;
17045 		mmr_t	underflow_pi_vc2_credit_out   : 1;
17046 		mmr_t	underflow_md_vc0_credit_out   : 1;
17047 		mmr_t	underflow_md_vc2_credit_out   : 1;
17048 		mmr_t	underflow_iilb_vc0_credit_out : 1;
17049 		mmr_t	underflow_iilb_vc2_credit_out : 1;
17050 		mmr_t	underflow_ni0_vc0_credit_out  : 1;
17051 		mmr_t	underflow_ni0_vc2_credit_out  : 1;
17052 		mmr_t	underflow_ni1_vc0_credit_out  : 1;
17053 		mmr_t	underflow_ni1_vc2_credit_out  : 1;
17054 		mmr_t	chiplet_nomatch               : 1;
17055 		mmr_t	lut_read_error                : 1;
17060 	mmr_t	sh_xniilb_first_error_regval;
17062 		mmr_t	lut_read_error                : 1;
17063 		mmr_t	chiplet_nomatch               : 1;
17064 		mmr_t	underflow_ni1_vc2_credit_out  : 1;
17065 		mmr_t	underflow_ni1_vc0_credit_out  : 1;
17066 		mmr_t	underflow_ni0_vc2_credit_out  : 1;
17067 		mmr_t	underflow_ni0_vc0_credit_out  : 1;
17068 		mmr_t	underflow_iilb_vc2_credit_out : 1;
17069 		mmr_t	underflow_iilb_vc0_credit_out : 1;
17070 		mmr_t	underflow_md_vc2_credit_out   : 1;
17071 		mmr_t	underflow_md_vc0_credit_out   : 1;
17072 		mmr_t	underflow_pi_vc2_credit_out   : 1;
17073 		mmr_t	underflow_pi_vc0_credit_out   : 1;
17074 		mmr_t	overflow_ni1_vc2_credit_out   : 1;
17075 		mmr_t	overflow_ni1_vc0_credit_out   : 1;
17076 		mmr_t	overflow_ni0_vc2_credit_out   : 1;
17077 		mmr_t	overflow_ni0_vc0_credit_out   : 1;
17078 		mmr_t	overflow_iilb_vc2_credit_out  : 1;
17079 		mmr_t	overflow_iilb_vc0_credit_out  : 1;
17080 		mmr_t	overflow_md_vc2_credit_out    : 1;
17081 		mmr_t	overflow_md_vc0_credit_out    : 1;
17082 		mmr_t	overflow_pi_vc2_credit_out    : 1;
17083 		mmr_t	overflow_pi_vc0_credit_out    : 1;
17084 		mmr_t	overflow_ni1_debit2           : 1;
17085 		mmr_t	overflow_ni1_debit0           : 1;
17086 		mmr_t	overflow_ni0_debit2           : 1;
17087 		mmr_t	overflow_ni0_debit0           : 1;
17088 		mmr_t	overflow_md_debit2            : 1;
17089 		mmr_t	overflow_md_debit0            : 1;
17090 		mmr_t	overflow_iilb_debit2          : 1;
17091 		mmr_t	overflow_iilb_debit0          : 1;
17092 		mmr_t	overflow_pi_debit2            : 1;
17093 		mmr_t	overflow_pi_debit0            : 1;
17094 		mmr_t	underflow_ni1_vc2_credit_in   : 1;
17095 		mmr_t	underflow_ni0_vc2_credit_in   : 1;
17096 		mmr_t	underflow_md_vc2_credit_in    : 1;
17097 		mmr_t	underflow_iilb_vc2_credit_in  : 1;
17098 		mmr_t	underflow_pi_vc2_credit_in    : 1;
17099 		mmr_t	underflow_ni1_vc0_credit_in   : 1;
17100 		mmr_t	underflow_ni0_vc0_credit_in   : 1;
17101 		mmr_t	underflow_md_vc0_credit_in    : 1;
17102 		mmr_t	underflow_iilb_vc0_credit_in  : 1;
17103 		mmr_t	underflow_pi_vc0_credit_in    : 1;
17104 		mmr_t	overflow_ni1_vc2_credit_in    : 1;
17105 		mmr_t	overflow_ni0_vc2_credit_in    : 1;
17106 		mmr_t	overflow_md_vc2_credit_in     : 1;
17107 		mmr_t	overflow_iilb_vc2_credit_in   : 1;
17108 		mmr_t	overflow_pi_vc2_credit_in     : 1;
17109 		mmr_t	overflow_ni1_vc0_credit_in    : 1;
17110 		mmr_t	overflow_ni0_vc0_credit_in    : 1;
17111 		mmr_t	overflow_md_vc0_credit_in     : 1;
17112 		mmr_t	overflow_iilb_vc0_credit_in   : 1;
17113 		mmr_t	overflow_pi_vc0_credit_in     : 1;
17114 		mmr_t	underflow_lb_vc2              : 1;
17115 		mmr_t	underflow_lb_vc0              : 1;
17116 		mmr_t	overflow_lb_vc2               : 1;
17117 		mmr_t	overflow_lb_vc0               : 1;
17118 		mmr_t	underflow_ii_vc2              : 1;
17119 		mmr_t	underflow_ii_vc0              : 1;
17120 		mmr_t	overflow_ii_vc2               : 1;
17121 		mmr_t	overflow_ii_vc0               : 1;
17122 		mmr_t	overflow_lb_debit2            : 1;
17123 		mmr_t	overflow_lb_debit0            : 1;
17124 		mmr_t	overflow_ii_debit2            : 1;
17125 		mmr_t	overflow_ii_debit0            : 1;
17136 	mmr_t	sh_xnpi_error_summary_regval;
17138 		mmr_t	underflow_ni0_vc0           : 1;
17139 		mmr_t	overflow_ni0_vc0            : 1;
17140 		mmr_t	underflow_ni0_vc2           : 1;
17141 		mmr_t	overflow_ni0_vc2            : 1;
17142 		mmr_t	underflow_ni1_vc0           : 1;
17143 		mmr_t	overflow_ni1_vc0            : 1;
17144 		mmr_t	underflow_ni1_vc2           : 1;
17145 		mmr_t	overflow_ni1_vc2            : 1;
17146 		mmr_t	underflow_iilb_vc0          : 1;
17147 		mmr_t	overflow_iilb_vc0           : 1;
17148 		mmr_t	underflow_iilb_vc2          : 1;
17149 		mmr_t	overflow_iilb_vc2           : 1;
17150 		mmr_t	underflow_vc0_credit        : 1;
17151 		mmr_t	overflow_vc0_credit         : 1;
17152 		mmr_t	underflow_vc2_credit        : 1;
17153 		mmr_t	overflow_vc2_credit         : 1;
17154 		mmr_t	overflow_databuff_vc0       : 1;
17155 		mmr_t	overflow_databuff_vc2       : 1;
17156 		mmr_t	lut_read_error              : 1;
17157 		mmr_t	single_bit_error0           : 1;
17158 		mmr_t	single_bit_error1           : 1;
17159 		mmr_t	single_bit_error2           : 1;
17160 		mmr_t	single_bit_error3           : 1;
17161 		mmr_t	uncor_error0                : 1;
17162 		mmr_t	uncor_error1                : 1;
17163 		mmr_t	uncor_error2                : 1;
17164 		mmr_t	uncor_error3                : 1;
17165 		mmr_t	underflow_sic_cntr0         : 1;
17166 		mmr_t	overflow_sic_cntr0          : 1;
17167 		mmr_t	underflow_sic_cntr2         : 1;
17168 		mmr_t	overflow_sic_cntr2          : 1;
17169 		mmr_t	overflow_ni0_debit0         : 1;
17170 		mmr_t	overflow_ni0_debit2         : 1;
17171 		mmr_t	overflow_ni1_debit0         : 1;
17172 		mmr_t	overflow_ni1_debit2         : 1;
17173 		mmr_t	overflow_iilb_debit0        : 1;
17174 		mmr_t	overflow_iilb_debit2        : 1;
17175 		mmr_t	underflow_ni0_vc0_credit    : 1;
17176 		mmr_t	overflow_ni0_vc0_credit     : 1;
17177 		mmr_t	underflow_ni0_vc2_credit    : 1;
17178 		mmr_t	overflow_ni0_vc2_credit     : 1;
17179 		mmr_t	underflow_ni1_vc0_credit    : 1;
17180 		mmr_t	overflow_ni1_vc0_credit     : 1;
17181 		mmr_t	underflow_ni1_vc2_credit    : 1;
17182 		mmr_t	overflow_ni1_vc2_credit     : 1;
17183 		mmr_t	underflow_iilb_vc0_credit   : 1;
17184 		mmr_t	overflow_iilb_vc0_credit    : 1;
17185 		mmr_t	underflow_iilb_vc2_credit   : 1;
17186 		mmr_t	overflow_iilb_vc2_credit    : 1;
17187 		mmr_t	overflow_header_cancel_fifo : 1;
17188 		mmr_t	reserved_0                  : 14;
17193 	mmr_t	sh_xnpi_error_summary_regval;
17195 		mmr_t	reserved_0                  : 14;
17196 		mmr_t	overflow_header_cancel_fifo : 1;
17197 		mmr_t	overflow_iilb_vc2_credit    : 1;
17198 		mmr_t	underflow_iilb_vc2_credit   : 1;
17199 		mmr_t	overflow_iilb_vc0_credit    : 1;
17200 		mmr_t	underflow_iilb_vc0_credit   : 1;
17201 		mmr_t	overflow_ni1_vc2_credit     : 1;
17202 		mmr_t	underflow_ni1_vc2_credit    : 1;
17203 		mmr_t	overflow_ni1_vc0_credit     : 1;
17204 		mmr_t	underflow_ni1_vc0_credit    : 1;
17205 		mmr_t	overflow_ni0_vc2_credit     : 1;
17206 		mmr_t	underflow_ni0_vc2_credit    : 1;
17207 		mmr_t	overflow_ni0_vc0_credit     : 1;
17208 		mmr_t	underflow_ni0_vc0_credit    : 1;
17209 		mmr_t	overflow_iilb_debit2        : 1;
17210 		mmr_t	overflow_iilb_debit0        : 1;
17211 		mmr_t	overflow_ni1_debit2         : 1;
17212 		mmr_t	overflow_ni1_debit0         : 1;
17213 		mmr_t	overflow_ni0_debit2         : 1;
17214 		mmr_t	overflow_ni0_debit0         : 1;
17215 		mmr_t	overflow_sic_cntr2          : 1;
17216 		mmr_t	underflow_sic_cntr2         : 1;
17217 		mmr_t	overflow_sic_cntr0          : 1;
17218 		mmr_t	underflow_sic_cntr0         : 1;
17219 		mmr_t	uncor_error3                : 1;
17220 		mmr_t	uncor_error2                : 1;
17221 		mmr_t	uncor_error1                : 1;
17222 		mmr_t	uncor_error0                : 1;
17223 		mmr_t	single_bit_error3           : 1;
17224 		mmr_t	single_bit_error2           : 1;
17225 		mmr_t	single_bit_error1           : 1;
17226 		mmr_t	single_bit_error0           : 1;
17227 		mmr_t	lut_read_error              : 1;
17228 		mmr_t	overflow_databuff_vc2       : 1;
17229 		mmr_t	overflow_databuff_vc0       : 1;
17230 		mmr_t	overflow_vc2_credit         : 1;
17231 		mmr_t	underflow_vc2_credit        : 1;
17232 		mmr_t	overflow_vc0_credit         : 1;
17233 		mmr_t	underflow_vc0_credit        : 1;
17234 		mmr_t	overflow_iilb_vc2           : 1;
17235 		mmr_t	underflow_iilb_vc2          : 1;
17236 		mmr_t	overflow_iilb_vc0           : 1;
17237 		mmr_t	underflow_iilb_vc0          : 1;
17238 		mmr_t	overflow_ni1_vc2            : 1;
17239 		mmr_t	underflow_ni1_vc2           : 1;
17240 		mmr_t	overflow_ni1_vc0            : 1;
17241 		mmr_t	underflow_ni1_vc0           : 1;
17242 		mmr_t	overflow_ni0_vc2            : 1;
17243 		mmr_t	underflow_ni0_vc2           : 1;
17244 		mmr_t	overflow_ni0_vc0            : 1;
17245 		mmr_t	underflow_ni0_vc0           : 1;
17256 	mmr_t	sh_xnpi_error_overflow_regval;
17258 		mmr_t	underflow_ni0_vc0           : 1;
17259 		mmr_t	overflow_ni0_vc0            : 1;
17260 		mmr_t	underflow_ni0_vc2           : 1;
17261 		mmr_t	overflow_ni0_vc2            : 1;
17262 		mmr_t	underflow_ni1_vc0           : 1;
17263 		mmr_t	overflow_ni1_vc0            : 1;
17264 		mmr_t	underflow_ni1_vc2           : 1;
17265 		mmr_t	overflow_ni1_vc2            : 1;
17266 		mmr_t	underflow_iilb_vc0          : 1;
17267 		mmr_t	overflow_iilb_vc0           : 1;
17268 		mmr_t	underflow_iilb_vc2          : 1;
17269 		mmr_t	overflow_iilb_vc2           : 1;
17270 		mmr_t	underflow_vc0_credit        : 1;
17271 		mmr_t	overflow_vc0_credit         : 1;
17272 		mmr_t	underflow_vc2_credit        : 1;
17273 		mmr_t	overflow_vc2_credit         : 1;
17274 		mmr_t	overflow_databuff_vc0       : 1;
17275 		mmr_t	overflow_databuff_vc2       : 1;
17276 		mmr_t	lut_read_error              : 1;
17277 		mmr_t	single_bit_error0           : 1;
17278 		mmr_t	single_bit_error1           : 1;
17279 		mmr_t	single_bit_error2           : 1;
17280 		mmr_t	single_bit_error3           : 1;
17281 		mmr_t	uncor_error0                : 1;
17282 		mmr_t	uncor_error1                : 1;
17283 		mmr_t	uncor_error2                : 1;
17284 		mmr_t	uncor_error3                : 1;
17285 		mmr_t	underflow_sic_cntr0         : 1;
17286 		mmr_t	overflow_sic_cntr0          : 1;
17287 		mmr_t	underflow_sic_cntr2         : 1;
17288 		mmr_t	overflow_sic_cntr2          : 1;
17289 		mmr_t	overflow_ni0_debit0         : 1;
17290 		mmr_t	overflow_ni0_debit2         : 1;
17291 		mmr_t	overflow_ni1_debit0         : 1;
17292 		mmr_t	overflow_ni1_debit2         : 1;
17293 		mmr_t	overflow_iilb_debit0        : 1;
17294 		mmr_t	overflow_iilb_debit2        : 1;
17295 		mmr_t	underflow_ni0_vc0_credit    : 1;
17296 		mmr_t	overflow_ni0_vc0_credit     : 1;
17297 		mmr_t	underflow_ni0_vc2_credit    : 1;
17298 		mmr_t	overflow_ni0_vc2_credit     : 1;
17299 		mmr_t	underflow_ni1_vc0_credit    : 1;
17300 		mmr_t	overflow_ni1_vc0_credit     : 1;
17301 		mmr_t	underflow_ni1_vc2_credit    : 1;
17302 		mmr_t	overflow_ni1_vc2_credit     : 1;
17303 		mmr_t	underflow_iilb_vc0_credit   : 1;
17304 		mmr_t	overflow_iilb_vc0_credit    : 1;
17305 		mmr_t	underflow_iilb_vc2_credit   : 1;
17306 		mmr_t	overflow_iilb_vc2_credit    : 1;
17307 		mmr_t	overflow_header_cancel_fifo : 1;
17308 		mmr_t	reserved_0                  : 14;
17313 	mmr_t	sh_xnpi_error_overflow_regval;
17315 		mmr_t	reserved_0                  : 14;
17316 		mmr_t	overflow_header_cancel_fifo : 1;
17317 		mmr_t	overflow_iilb_vc2_credit    : 1;
17318 		mmr_t	underflow_iilb_vc2_credit   : 1;
17319 		mmr_t	overflow_iilb_vc0_credit    : 1;
17320 		mmr_t	underflow_iilb_vc0_credit   : 1;
17321 		mmr_t	overflow_ni1_vc2_credit     : 1;
17322 		mmr_t	underflow_ni1_vc2_credit    : 1;
17323 		mmr_t	overflow_ni1_vc0_credit     : 1;
17324 		mmr_t	underflow_ni1_vc0_credit    : 1;
17325 		mmr_t	overflow_ni0_vc2_credit     : 1;
17326 		mmr_t	underflow_ni0_vc2_credit    : 1;
17327 		mmr_t	overflow_ni0_vc0_credit     : 1;
17328 		mmr_t	underflow_ni0_vc0_credit    : 1;
17329 		mmr_t	overflow_iilb_debit2        : 1;
17330 		mmr_t	overflow_iilb_debit0        : 1;
17331 		mmr_t	overflow_ni1_debit2         : 1;
17332 		mmr_t	overflow_ni1_debit0         : 1;
17333 		mmr_t	overflow_ni0_debit2         : 1;
17334 		mmr_t	overflow_ni0_debit0         : 1;
17335 		mmr_t	overflow_sic_cntr2          : 1;
17336 		mmr_t	underflow_sic_cntr2         : 1;
17337 		mmr_t	overflow_sic_cntr0          : 1;
17338 		mmr_t	underflow_sic_cntr0         : 1;
17339 		mmr_t	uncor_error3                : 1;
17340 		mmr_t	uncor_error2                : 1;
17341 		mmr_t	uncor_error1                : 1;
17342 		mmr_t	uncor_error0                : 1;
17343 		mmr_t	single_bit_error3           : 1;
17344 		mmr_t	single_bit_error2           : 1;
17345 		mmr_t	single_bit_error1           : 1;
17346 		mmr_t	single_bit_error0           : 1;
17347 		mmr_t	lut_read_error              : 1;
17348 		mmr_t	overflow_databuff_vc2       : 1;
17349 		mmr_t	overflow_databuff_vc0       : 1;
17350 		mmr_t	overflow_vc2_credit         : 1;
17351 		mmr_t	underflow_vc2_credit        : 1;
17352 		mmr_t	overflow_vc0_credit         : 1;
17353 		mmr_t	underflow_vc0_credit        : 1;
17354 		mmr_t	overflow_iilb_vc2           : 1;
17355 		mmr_t	underflow_iilb_vc2          : 1;
17356 		mmr_t	overflow_iilb_vc0           : 1;
17357 		mmr_t	underflow_iilb_vc0          : 1;
17358 		mmr_t	overflow_ni1_vc2            : 1;
17359 		mmr_t	underflow_ni1_vc2           : 1;
17360 		mmr_t	overflow_ni1_vc0            : 1;
17361 		mmr_t	underflow_ni1_vc0           : 1;
17362 		mmr_t	overflow_ni0_vc2            : 1;
17363 		mmr_t	underflow_ni0_vc2           : 1;
17364 		mmr_t	overflow_ni0_vc0            : 1;
17365 		mmr_t	underflow_ni0_vc0           : 1;
17376 	mmr_t	sh_xnpi_error_mask_regval;
17378 		mmr_t	underflow_ni0_vc0           : 1;
17379 		mmr_t	overflow_ni0_vc0            : 1;
17380 		mmr_t	underflow_ni0_vc2           : 1;
17381 		mmr_t	overflow_ni0_vc2            : 1;
17382 		mmr_t	underflow_ni1_vc0           : 1;
17383 		mmr_t	overflow_ni1_vc0            : 1;
17384 		mmr_t	underflow_ni1_vc2           : 1;
17385 		mmr_t	overflow_ni1_vc2            : 1;
17386 		mmr_t	underflow_iilb_vc0          : 1;
17387 		mmr_t	overflow_iilb_vc0           : 1;
17388 		mmr_t	underflow_iilb_vc2          : 1;
17389 		mmr_t	overflow_iilb_vc2           : 1;
17390 		mmr_t	underflow_vc0_credit        : 1;
17391 		mmr_t	overflow_vc0_credit         : 1;
17392 		mmr_t	underflow_vc2_credit        : 1;
17393 		mmr_t	overflow_vc2_credit         : 1;
17394 		mmr_t	overflow_databuff_vc0       : 1;
17395 		mmr_t	overflow_databuff_vc2       : 1;
17396 		mmr_t	lut_read_error              : 1;
17397 		mmr_t	single_bit_error0           : 1;
17398 		mmr_t	single_bit_error1           : 1;
17399 		mmr_t	single_bit_error2           : 1;
17400 		mmr_t	single_bit_error3           : 1;
17401 		mmr_t	uncor_error0                : 1;
17402 		mmr_t	uncor_error1                : 1;
17403 		mmr_t	uncor_error2                : 1;
17404 		mmr_t	uncor_error3                : 1;
17405 		mmr_t	underflow_sic_cntr0         : 1;
17406 		mmr_t	overflow_sic_cntr0          : 1;
17407 		mmr_t	underflow_sic_cntr2         : 1;
17408 		mmr_t	overflow_sic_cntr2          : 1;
17409 		mmr_t	overflow_ni0_debit0         : 1;
17410 		mmr_t	overflow_ni0_debit2         : 1;
17411 		mmr_t	overflow_ni1_debit0         : 1;
17412 		mmr_t	overflow_ni1_debit2         : 1;
17413 		mmr_t	overflow_iilb_debit0        : 1;
17414 		mmr_t	overflow_iilb_debit2        : 1;
17415 		mmr_t	underflow_ni0_vc0_credit    : 1;
17416 		mmr_t	overflow_ni0_vc0_credit     : 1;
17417 		mmr_t	underflow_ni0_vc2_credit    : 1;
17418 		mmr_t	overflow_ni0_vc2_credit     : 1;
17419 		mmr_t	underflow_ni1_vc0_credit    : 1;
17420 		mmr_t	overflow_ni1_vc0_credit     : 1;
17421 		mmr_t	underflow_ni1_vc2_credit    : 1;
17422 		mmr_t	overflow_ni1_vc2_credit     : 1;
17423 		mmr_t	underflow_iilb_vc0_credit   : 1;
17424 		mmr_t	overflow_iilb_vc0_credit    : 1;
17425 		mmr_t	underflow_iilb_vc2_credit   : 1;
17426 		mmr_t	overflow_iilb_vc2_credit    : 1;
17427 		mmr_t	overflow_header_cancel_fifo : 1;
17428 		mmr_t	reserved_0                  : 14;
17433 	mmr_t	sh_xnpi_error_mask_regval;
17435 		mmr_t	reserved_0                  : 14;
17436 		mmr_t	overflow_header_cancel_fifo : 1;
17437 		mmr_t	overflow_iilb_vc2_credit    : 1;
17438 		mmr_t	underflow_iilb_vc2_credit   : 1;
17439 		mmr_t	overflow_iilb_vc0_credit    : 1;
17440 		mmr_t	underflow_iilb_vc0_credit   : 1;
17441 		mmr_t	overflow_ni1_vc2_credit     : 1;
17442 		mmr_t	underflow_ni1_vc2_credit    : 1;
17443 		mmr_t	overflow_ni1_vc0_credit     : 1;
17444 		mmr_t	underflow_ni1_vc0_credit    : 1;
17445 		mmr_t	overflow_ni0_vc2_credit     : 1;
17446 		mmr_t	underflow_ni0_vc2_credit    : 1;
17447 		mmr_t	overflow_ni0_vc0_credit     : 1;
17448 		mmr_t	underflow_ni0_vc0_credit    : 1;
17449 		mmr_t	overflow_iilb_debit2        : 1;
17450 		mmr_t	overflow_iilb_debit0        : 1;
17451 		mmr_t	overflow_ni1_debit2         : 1;
17452 		mmr_t	overflow_ni1_debit0         : 1;
17453 		mmr_t	overflow_ni0_debit2         : 1;
17454 		mmr_t	overflow_ni0_debit0         : 1;
17455 		mmr_t	overflow_sic_cntr2          : 1;
17456 		mmr_t	underflow_sic_cntr2         : 1;
17457 		mmr_t	overflow_sic_cntr0          : 1;
17458 		mmr_t	underflow_sic_cntr0         : 1;
17459 		mmr_t	uncor_error3                : 1;
17460 		mmr_t	uncor_error2                : 1;
17461 		mmr_t	uncor_error1                : 1;
17462 		mmr_t	uncor_error0                : 1;
17463 		mmr_t	single_bit_error3           : 1;
17464 		mmr_t	single_bit_error2           : 1;
17465 		mmr_t	single_bit_error1           : 1;
17466 		mmr_t	single_bit_error0           : 1;
17467 		mmr_t	lut_read_error              : 1;
17468 		mmr_t	overflow_databuff_vc2       : 1;
17469 		mmr_t	overflow_databuff_vc0       : 1;
17470 		mmr_t	overflow_vc2_credit         : 1;
17471 		mmr_t	underflow_vc2_credit        : 1;
17472 		mmr_t	overflow_vc0_credit         : 1;
17473 		mmr_t	underflow_vc0_credit        : 1;
17474 		mmr_t	overflow_iilb_vc2           : 1;
17475 		mmr_t	underflow_iilb_vc2          : 1;
17476 		mmr_t	overflow_iilb_vc0           : 1;
17477 		mmr_t	underflow_iilb_vc0          : 1;
17478 		mmr_t	overflow_ni1_vc2            : 1;
17479 		mmr_t	underflow_ni1_vc2           : 1;
17480 		mmr_t	overflow_ni1_vc0            : 1;
17481 		mmr_t	underflow_ni1_vc0           : 1;
17482 		mmr_t	overflow_ni0_vc2            : 1;
17483 		mmr_t	underflow_ni0_vc2           : 1;
17484 		mmr_t	overflow_ni0_vc0            : 1;
17485 		mmr_t	underflow_ni0_vc0           : 1;
17496 	mmr_t	sh_xnpi_first_error_regval;
17498 		mmr_t	underflow_ni0_vc0           : 1;
17499 		mmr_t	overflow_ni0_vc0            : 1;
17500 		mmr_t	underflow_ni0_vc2           : 1;
17501 		mmr_t	overflow_ni0_vc2            : 1;
17502 		mmr_t	underflow_ni1_vc0           : 1;
17503 		mmr_t	overflow_ni1_vc0            : 1;
17504 		mmr_t	underflow_ni1_vc2           : 1;
17505 		mmr_t	overflow_ni1_vc2            : 1;
17506 		mmr_t	underflow_iilb_vc0          : 1;
17507 		mmr_t	overflow_iilb_vc0           : 1;
17508 		mmr_t	underflow_iilb_vc2          : 1;
17509 		mmr_t	overflow_iilb_vc2           : 1;
17510 		mmr_t	underflow_vc0_credit        : 1;
17511 		mmr_t	overflow_vc0_credit         : 1;
17512 		mmr_t	underflow_vc2_credit        : 1;
17513 		mmr_t	overflow_vc2_credit         : 1;
17514 		mmr_t	overflow_databuff_vc0       : 1;
17515 		mmr_t	overflow_databuff_vc2       : 1;
17516 		mmr_t	lut_read_error              : 1;
17517 		mmr_t	single_bit_error0           : 1;
17518 		mmr_t	single_bit_error1           : 1;
17519 		mmr_t	single_bit_error2           : 1;
17520 		mmr_t	single_bit_error3           : 1;
17521 		mmr_t	uncor_error0                : 1;
17522 		mmr_t	uncor_error1                : 1;
17523 		mmr_t	uncor_error2                : 1;
17524 		mmr_t	uncor_error3                : 1;
17525 		mmr_t	underflow_sic_cntr0         : 1;
17526 		mmr_t	overflow_sic_cntr0          : 1;
17527 		mmr_t	underflow_sic_cntr2         : 1;
17528 		mmr_t	overflow_sic_cntr2          : 1;
17529 		mmr_t	overflow_ni0_debit0         : 1;
17530 		mmr_t	overflow_ni0_debit2         : 1;
17531 		mmr_t	overflow_ni1_debit0         : 1;
17532 		mmr_t	overflow_ni1_debit2         : 1;
17533 		mmr_t	overflow_iilb_debit0        : 1;
17534 		mmr_t	overflow_iilb_debit2        : 1;
17535 		mmr_t	underflow_ni0_vc0_credit    : 1;
17536 		mmr_t	overflow_ni0_vc0_credit     : 1;
17537 		mmr_t	underflow_ni0_vc2_credit    : 1;
17538 		mmr_t	overflow_ni0_vc2_credit     : 1;
17539 		mmr_t	underflow_ni1_vc0_credit    : 1;
17540 		mmr_t	overflow_ni1_vc0_credit     : 1;
17541 		mmr_t	underflow_ni1_vc2_credit    : 1;
17542 		mmr_t	overflow_ni1_vc2_credit     : 1;
17543 		mmr_t	underflow_iilb_vc0_credit   : 1;
17544 		mmr_t	overflow_iilb_vc0_credit    : 1;
17545 		mmr_t	underflow_iilb_vc2_credit   : 1;
17546 		mmr_t	overflow_iilb_vc2_credit    : 1;
17547 		mmr_t	overflow_header_cancel_fifo : 1;
17548 		mmr_t	reserved_0                  : 14;
17553 	mmr_t	sh_xnpi_first_error_regval;
17555 		mmr_t	reserved_0                  : 14;
17556 		mmr_t	overflow_header_cancel_fifo : 1;
17557 		mmr_t	overflow_iilb_vc2_credit    : 1;
17558 		mmr_t	underflow_iilb_vc2_credit   : 1;
17559 		mmr_t	overflow_iilb_vc0_credit    : 1;
17560 		mmr_t	underflow_iilb_vc0_credit   : 1;
17561 		mmr_t	overflow_ni1_vc2_credit     : 1;
17562 		mmr_t	underflow_ni1_vc2_credit    : 1;
17563 		mmr_t	overflow_ni1_vc0_credit     : 1;
17564 		mmr_t	underflow_ni1_vc0_credit    : 1;
17565 		mmr_t	overflow_ni0_vc2_credit     : 1;
17566 		mmr_t	underflow_ni0_vc2_credit    : 1;
17567 		mmr_t	overflow_ni0_vc0_credit     : 1;
17568 		mmr_t	underflow_ni0_vc0_credit    : 1;
17569 		mmr_t	overflow_iilb_debit2        : 1;
17570 		mmr_t	overflow_iilb_debit0        : 1;
17571 		mmr_t	overflow_ni1_debit2         : 1;
17572 		mmr_t	overflow_ni1_debit0         : 1;
17573 		mmr_t	overflow_ni0_debit2         : 1;
17574 		mmr_t	overflow_ni0_debit0         : 1;
17575 		mmr_t	overflow_sic_cntr2          : 1;
17576 		mmr_t	underflow_sic_cntr2         : 1;
17577 		mmr_t	overflow_sic_cntr0          : 1;
17578 		mmr_t	underflow_sic_cntr0         : 1;
17579 		mmr_t	uncor_error3                : 1;
17580 		mmr_t	uncor_error2                : 1;
17581 		mmr_t	uncor_error1                : 1;
17582 		mmr_t	uncor_error0                : 1;
17583 		mmr_t	single_bit_error3           : 1;
17584 		mmr_t	single_bit_error2           : 1;
17585 		mmr_t	single_bit_error1           : 1;
17586 		mmr_t	single_bit_error0           : 1;
17587 		mmr_t	lut_read_error              : 1;
17588 		mmr_t	overflow_databuff_vc2       : 1;
17589 		mmr_t	overflow_databuff_vc0       : 1;
17590 		mmr_t	overflow_vc2_credit         : 1;
17591 		mmr_t	underflow_vc2_credit        : 1;
17592 		mmr_t	overflow_vc0_credit         : 1;
17593 		mmr_t	underflow_vc0_credit        : 1;
17594 		mmr_t	overflow_iilb_vc2           : 1;
17595 		mmr_t	underflow_iilb_vc2          : 1;
17596 		mmr_t	overflow_iilb_vc0           : 1;
17597 		mmr_t	underflow_iilb_vc0          : 1;
17598 		mmr_t	overflow_ni1_vc2            : 1;
17599 		mmr_t	underflow_ni1_vc2           : 1;
17600 		mmr_t	overflow_ni1_vc0            : 1;
17601 		mmr_t	underflow_ni1_vc0           : 1;
17602 		mmr_t	overflow_ni0_vc2            : 1;
17603 		mmr_t	underflow_ni0_vc2           : 1;
17604 		mmr_t	overflow_ni0_vc0            : 1;
17605 		mmr_t	underflow_ni0_vc0           : 1;
17616 	mmr_t	sh_xnmd_error_summary_regval;
17618 		mmr_t	underflow_ni0_vc0           : 1;
17619 		mmr_t	overflow_ni0_vc0            : 1;
17620 		mmr_t	underflow_ni0_vc2           : 1;
17621 		mmr_t	overflow_ni0_vc2            : 1;
17622 		mmr_t	underflow_ni1_vc0           : 1;
17623 		mmr_t	overflow_ni1_vc0            : 1;
17624 		mmr_t	underflow_ni1_vc2           : 1;
17625 		mmr_t	overflow_ni1_vc2            : 1;
17626 		mmr_t	underflow_iilb_vc0          : 1;
17627 		mmr_t	overflow_iilb_vc0           : 1;
17628 		mmr_t	underflow_iilb_vc2          : 1;
17629 		mmr_t	overflow_iilb_vc2           : 1;
17630 		mmr_t	underflow_vc0_credit        : 1;
17631 		mmr_t	overflow_vc0_credit         : 1;
17632 		mmr_t	underflow_vc2_credit        : 1;
17633 		mmr_t	overflow_vc2_credit         : 1;
17634 		mmr_t	overflow_databuff_vc0       : 1;
17635 		mmr_t	overflow_databuff_vc2       : 1;
17636 		mmr_t	lut_read_error              : 1;
17637 		mmr_t	single_bit_error0           : 1;
17638 		mmr_t	single_bit_error1           : 1;
17639 		mmr_t	single_bit_error2           : 1;
17640 		mmr_t	single_bit_error3           : 1;
17641 		mmr_t	uncor_error0                : 1;
17642 		mmr_t	uncor_error1                : 1;
17643 		mmr_t	uncor_error2                : 1;
17644 		mmr_t	uncor_error3                : 1;
17645 		mmr_t	underflow_sic_cntr0         : 1;
17646 		mmr_t	overflow_sic_cntr0          : 1;
17647 		mmr_t	underflow_sic_cntr2         : 1;
17648 		mmr_t	overflow_sic_cntr2          : 1;
17649 		mmr_t	overflow_ni0_debit0         : 1;
17650 		mmr_t	overflow_ni0_debit2         : 1;
17651 		mmr_t	overflow_ni1_debit0         : 1;
17652 		mmr_t	overflow_ni1_debit2         : 1;
17653 		mmr_t	overflow_iilb_debit0        : 1;
17654 		mmr_t	overflow_iilb_debit2        : 1;
17655 		mmr_t	underflow_ni0_vc0_credit    : 1;
17656 		mmr_t	overflow_ni0_vc0_credit     : 1;
17657 		mmr_t	underflow_ni0_vc2_credit    : 1;
17658 		mmr_t	overflow_ni0_vc2_credit     : 1;
17659 		mmr_t	underflow_ni1_vc0_credit    : 1;
17660 		mmr_t	overflow_ni1_vc0_credit     : 1;
17661 		mmr_t	underflow_ni1_vc2_credit    : 1;
17662 		mmr_t	overflow_ni1_vc2_credit     : 1;
17663 		mmr_t	underflow_iilb_vc0_credit   : 1;
17664 		mmr_t	overflow_iilb_vc0_credit    : 1;
17665 		mmr_t	underflow_iilb_vc2_credit   : 1;
17666 		mmr_t	overflow_iilb_vc2_credit    : 1;
17667 		mmr_t	overflow_header_cancel_fifo : 1;
17668 		mmr_t	reserved_0                  : 14;
17673 	mmr_t	sh_xnmd_error_summary_regval;
17675 		mmr_t	reserved_0                  : 14;
17676 		mmr_t	overflow_header_cancel_fifo : 1;
17677 		mmr_t	overflow_iilb_vc2_credit    : 1;
17678 		mmr_t	underflow_iilb_vc2_credit   : 1;
17679 		mmr_t	overflow_iilb_vc0_credit    : 1;
17680 		mmr_t	underflow_iilb_vc0_credit   : 1;
17681 		mmr_t	overflow_ni1_vc2_credit     : 1;
17682 		mmr_t	underflow_ni1_vc2_credit    : 1;
17683 		mmr_t	overflow_ni1_vc0_credit     : 1;
17684 		mmr_t	underflow_ni1_vc0_credit    : 1;
17685 		mmr_t	overflow_ni0_vc2_credit     : 1;
17686 		mmr_t	underflow_ni0_vc2_credit    : 1;
17687 		mmr_t	overflow_ni0_vc0_credit     : 1;
17688 		mmr_t	underflow_ni0_vc0_credit    : 1;
17689 		mmr_t	overflow_iilb_debit2        : 1;
17690 		mmr_t	overflow_iilb_debit0        : 1;
17691 		mmr_t	overflow_ni1_debit2         : 1;
17692 		mmr_t	overflow_ni1_debit0         : 1;
17693 		mmr_t	overflow_ni0_debit2         : 1;
17694 		mmr_t	overflow_ni0_debit0         : 1;
17695 		mmr_t	overflow_sic_cntr2          : 1;
17696 		mmr_t	underflow_sic_cntr2         : 1;
17697 		mmr_t	overflow_sic_cntr0          : 1;
17698 		mmr_t	underflow_sic_cntr0         : 1;
17699 		mmr_t	uncor_error3                : 1;
17700 		mmr_t	uncor_error2                : 1;
17701 		mmr_t	uncor_error1                : 1;
17702 		mmr_t	uncor_error0                : 1;
17703 		mmr_t	single_bit_error3           : 1;
17704 		mmr_t	single_bit_error2           : 1;
17705 		mmr_t	single_bit_error1           : 1;
17706 		mmr_t	single_bit_error0           : 1;
17707 		mmr_t	lut_read_error              : 1;
17708 		mmr_t	overflow_databuff_vc2       : 1;
17709 		mmr_t	overflow_databuff_vc0       : 1;
17710 		mmr_t	overflow_vc2_credit         : 1;
17711 		mmr_t	underflow_vc2_credit        : 1;
17712 		mmr_t	overflow_vc0_credit         : 1;
17713 		mmr_t	underflow_vc0_credit        : 1;
17714 		mmr_t	overflow_iilb_vc2           : 1;
17715 		mmr_t	underflow_iilb_vc2          : 1;
17716 		mmr_t	overflow_iilb_vc0           : 1;
17717 		mmr_t	underflow_iilb_vc0          : 1;
17718 		mmr_t	overflow_ni1_vc2            : 1;
17719 		mmr_t	underflow_ni1_vc2           : 1;
17720 		mmr_t	overflow_ni1_vc0            : 1;
17721 		mmr_t	underflow_ni1_vc0           : 1;
17722 		mmr_t	overflow_ni0_vc2            : 1;
17723 		mmr_t	underflow_ni0_vc2           : 1;
17724 		mmr_t	overflow_ni0_vc0            : 1;
17725 		mmr_t	underflow_ni0_vc0           : 1;
17736 	mmr_t	sh_xnmd_error_overflow_regval;
17738 		mmr_t	underflow_ni0_vc0           : 1;
17739 		mmr_t	overflow_ni0_vc0            : 1;
17740 		mmr_t	underflow_ni0_vc2           : 1;
17741 		mmr_t	overflow_ni0_vc2            : 1;
17742 		mmr_t	underflow_ni1_vc0           : 1;
17743 		mmr_t	overflow_ni1_vc0            : 1;
17744 		mmr_t	underflow_ni1_vc2           : 1;
17745 		mmr_t	overflow_ni1_vc2            : 1;
17746 		mmr_t	underflow_iilb_vc0          : 1;
17747 		mmr_t	overflow_iilb_vc0           : 1;
17748 		mmr_t	underflow_iilb_vc2          : 1;
17749 		mmr_t	overflow_iilb_vc2           : 1;
17750 		mmr_t	underflow_vc0_credit        : 1;
17751 		mmr_t	overflow_vc0_credit         : 1;
17752 		mmr_t	underflow_vc2_credit        : 1;
17753 		mmr_t	overflow_vc2_credit         : 1;
17754 		mmr_t	overflow_databuff_vc0       : 1;
17755 		mmr_t	overflow_databuff_vc2       : 1;
17756 		mmr_t	lut_read_error              : 1;
17757 		mmr_t	single_bit_error0           : 1;
17758 		mmr_t	single_bit_error1           : 1;
17759 		mmr_t	single_bit_error2           : 1;
17760 		mmr_t	single_bit_error3           : 1;
17761 		mmr_t	uncor_error0                : 1;
17762 		mmr_t	uncor_error1                : 1;
17763 		mmr_t	uncor_error2                : 1;
17764 		mmr_t	uncor_error3                : 1;
17765 		mmr_t	underflow_sic_cntr0         : 1;
17766 		mmr_t	overflow_sic_cntr0          : 1;
17767 		mmr_t	underflow_sic_cntr2         : 1;
17768 		mmr_t	overflow_sic_cntr2          : 1;
17769 		mmr_t	overflow_ni0_debit0         : 1;
17770 		mmr_t	overflow_ni0_debit2         : 1;
17771 		mmr_t	overflow_ni1_debit0         : 1;
17772 		mmr_t	overflow_ni1_debit2         : 1;
17773 		mmr_t	overflow_iilb_debit0        : 1;
17774 		mmr_t	overflow_iilb_debit2        : 1;
17775 		mmr_t	underflow_ni0_vc0_credit    : 1;
17776 		mmr_t	overflow_ni0_vc0_credit     : 1;
17777 		mmr_t	underflow_ni0_vc2_credit    : 1;
17778 		mmr_t	overflow_ni0_vc2_credit     : 1;
17779 		mmr_t	underflow_ni1_vc0_credit    : 1;
17780 		mmr_t	overflow_ni1_vc0_credit     : 1;
17781 		mmr_t	underflow_ni1_vc2_credit    : 1;
17782 		mmr_t	overflow_ni1_vc2_credit     : 1;
17783 		mmr_t	underflow_iilb_vc0_credit   : 1;
17784 		mmr_t	overflow_iilb_vc0_credit    : 1;
17785 		mmr_t	underflow_iilb_vc2_credit   : 1;
17786 		mmr_t	overflow_iilb_vc2_credit    : 1;
17787 		mmr_t	overflow_header_cancel_fifo : 1;
17788 		mmr_t	reserved_0                  : 14;
17793 	mmr_t	sh_xnmd_error_overflow_regval;
17795 		mmr_t	reserved_0                  : 14;
17796 		mmr_t	overflow_header_cancel_fifo : 1;
17797 		mmr_t	overflow_iilb_vc2_credit    : 1;
17798 		mmr_t	underflow_iilb_vc2_credit   : 1;
17799 		mmr_t	overflow_iilb_vc0_credit    : 1;
17800 		mmr_t	underflow_iilb_vc0_credit   : 1;
17801 		mmr_t	overflow_ni1_vc2_credit     : 1;
17802 		mmr_t	underflow_ni1_vc2_credit    : 1;
17803 		mmr_t	overflow_ni1_vc0_credit     : 1;
17804 		mmr_t	underflow_ni1_vc0_credit    : 1;
17805 		mmr_t	overflow_ni0_vc2_credit     : 1;
17806 		mmr_t	underflow_ni0_vc2_credit    : 1;
17807 		mmr_t	overflow_ni0_vc0_credit     : 1;
17808 		mmr_t	underflow_ni0_vc0_credit    : 1;
17809 		mmr_t	overflow_iilb_debit2        : 1;
17810 		mmr_t	overflow_iilb_debit0        : 1;
17811 		mmr_t	overflow_ni1_debit2         : 1;
17812 		mmr_t	overflow_ni1_debit0         : 1;
17813 		mmr_t	overflow_ni0_debit2         : 1;
17814 		mmr_t	overflow_ni0_debit0         : 1;
17815 		mmr_t	overflow_sic_cntr2          : 1;
17816 		mmr_t	underflow_sic_cntr2         : 1;
17817 		mmr_t	overflow_sic_cntr0          : 1;
17818 		mmr_t	underflow_sic_cntr0         : 1;
17819 		mmr_t	uncor_error3                : 1;
17820 		mmr_t	uncor_error2                : 1;
17821 		mmr_t	uncor_error1                : 1;
17822 		mmr_t	uncor_error0                : 1;
17823 		mmr_t	single_bit_error3           : 1;
17824 		mmr_t	single_bit_error2           : 1;
17825 		mmr_t	single_bit_error1           : 1;
17826 		mmr_t	single_bit_error0           : 1;
17827 		mmr_t	lut_read_error              : 1;
17828 		mmr_t	overflow_databuff_vc2       : 1;
17829 		mmr_t	overflow_databuff_vc0       : 1;
17830 		mmr_t	overflow_vc2_credit         : 1;
17831 		mmr_t	underflow_vc2_credit        : 1;
17832 		mmr_t	overflow_vc0_credit         : 1;
17833 		mmr_t	underflow_vc0_credit        : 1;
17834 		mmr_t	overflow_iilb_vc2           : 1;
17835 		mmr_t	underflow_iilb_vc2          : 1;
17836 		mmr_t	overflow_iilb_vc0           : 1;
17837 		mmr_t	underflow_iilb_vc0          : 1;
17838 		mmr_t	overflow_ni1_vc2            : 1;
17839 		mmr_t	underflow_ni1_vc2           : 1;
17840 		mmr_t	overflow_ni1_vc0            : 1;
17841 		mmr_t	underflow_ni1_vc0           : 1;
17842 		mmr_t	overflow_ni0_vc2            : 1;
17843 		mmr_t	underflow_ni0_vc2           : 1;
17844 		mmr_t	overflow_ni0_vc0            : 1;
17845 		mmr_t	underflow_ni0_vc0           : 1;
17856 	mmr_t	sh_xnmd_error_mask_regval;
17858 		mmr_t	underflow_ni0_vc0           : 1;
17859 		mmr_t	overflow_ni0_vc0            : 1;
17860 		mmr_t	underflow_ni0_vc2           : 1;
17861 		mmr_t	overflow_ni0_vc2            : 1;
17862 		mmr_t	underflow_ni1_vc0           : 1;
17863 		mmr_t	overflow_ni1_vc0            : 1;
17864 		mmr_t	underflow_ni1_vc2           : 1;
17865 		mmr_t	overflow_ni1_vc2            : 1;
17866 		mmr_t	underflow_iilb_vc0          : 1;
17867 		mmr_t	overflow_iilb_vc0           : 1;
17868 		mmr_t	underflow_iilb_vc2          : 1;
17869 		mmr_t	overflow_iilb_vc2           : 1;
17870 		mmr_t	underflow_vc0_credit        : 1;
17871 		mmr_t	overflow_vc0_credit         : 1;
17872 		mmr_t	underflow_vc2_credit        : 1;
17873 		mmr_t	overflow_vc2_credit         : 1;
17874 		mmr_t	overflow_databuff_vc0       : 1;
17875 		mmr_t	overflow_databuff_vc2       : 1;
17876 		mmr_t	lut_read_error              : 1;
17877 		mmr_t	single_bit_error0           : 1;
17878 		mmr_t	single_bit_error1           : 1;
17879 		mmr_t	single_bit_error2           : 1;
17880 		mmr_t	single_bit_error3           : 1;
17881 		mmr_t	uncor_error0                : 1;
17882 		mmr_t	uncor_error1                : 1;
17883 		mmr_t	uncor_error2                : 1;
17884 		mmr_t	uncor_error3                : 1;
17885 		mmr_t	underflow_sic_cntr0         : 1;
17886 		mmr_t	overflow_sic_cntr0          : 1;
17887 		mmr_t	underflow_sic_cntr2         : 1;
17888 		mmr_t	overflow_sic_cntr2          : 1;
17889 		mmr_t	overflow_ni0_debit0         : 1;
17890 		mmr_t	overflow_ni0_debit2         : 1;
17891 		mmr_t	overflow_ni1_debit0         : 1;
17892 		mmr_t	overflow_ni1_debit2         : 1;
17893 		mmr_t	overflow_iilb_debit0        : 1;
17894 		mmr_t	overflow_iilb_debit2        : 1;
17895 		mmr_t	underflow_ni0_vc0_credit    : 1;
17896 		mmr_t	overflow_ni0_vc0_credit     : 1;
17897 		mmr_t	underflow_ni0_vc2_credit    : 1;
17898 		mmr_t	overflow_ni0_vc2_credit     : 1;
17899 		mmr_t	underflow_ni1_vc0_credit    : 1;
17900 		mmr_t	overflow_ni1_vc0_credit     : 1;
17901 		mmr_t	underflow_ni1_vc2_credit    : 1;
17902 		mmr_t	overflow_ni1_vc2_credit     : 1;
17903 		mmr_t	underflow_iilb_vc0_credit   : 1;
17904 		mmr_t	overflow_iilb_vc0_credit    : 1;
17905 		mmr_t	underflow_iilb_vc2_credit   : 1;
17906 		mmr_t	overflow_iilb_vc2_credit    : 1;
17907 		mmr_t	overflow_header_cancel_fifo : 1;
17908 		mmr_t	reserved_0                  : 14;
17913 	mmr_t	sh_xnmd_error_mask_regval;
17915 		mmr_t	reserved_0                  : 14;
17916 		mmr_t	overflow_header_cancel_fifo : 1;
17917 		mmr_t	overflow_iilb_vc2_credit    : 1;
17918 		mmr_t	underflow_iilb_vc2_credit   : 1;
17919 		mmr_t	overflow_iilb_vc0_credit    : 1;
17920 		mmr_t	underflow_iilb_vc0_credit   : 1;
17921 		mmr_t	overflow_ni1_vc2_credit     : 1;
17922 		mmr_t	underflow_ni1_vc2_credit    : 1;
17923 		mmr_t	overflow_ni1_vc0_credit     : 1;
17924 		mmr_t	underflow_ni1_vc0_credit    : 1;
17925 		mmr_t	overflow_ni0_vc2_credit     : 1;
17926 		mmr_t	underflow_ni0_vc2_credit    : 1;
17927 		mmr_t	overflow_ni0_vc0_credit     : 1;
17928 		mmr_t	underflow_ni0_vc0_credit    : 1;
17929 		mmr_t	overflow_iilb_debit2        : 1;
17930 		mmr_t	overflow_iilb_debit0        : 1;
17931 		mmr_t	overflow_ni1_debit2         : 1;
17932 		mmr_t	overflow_ni1_debit0         : 1;
17933 		mmr_t	overflow_ni0_debit2         : 1;
17934 		mmr_t	overflow_ni0_debit0         : 1;
17935 		mmr_t	overflow_sic_cntr2          : 1;
17936 		mmr_t	underflow_sic_cntr2         : 1;
17937 		mmr_t	overflow_sic_cntr0          : 1;
17938 		mmr_t	underflow_sic_cntr0         : 1;
17939 		mmr_t	uncor_error3                : 1;
17940 		mmr_t	uncor_error2                : 1;
17941 		mmr_t	uncor_error1                : 1;
17942 		mmr_t	uncor_error0                : 1;
17943 		mmr_t	single_bit_error3           : 1;
17944 		mmr_t	single_bit_error2           : 1;
17945 		mmr_t	single_bit_error1           : 1;
17946 		mmr_t	single_bit_error0           : 1;
17947 		mmr_t	lut_read_error              : 1;
17948 		mmr_t	overflow_databuff_vc2       : 1;
17949 		mmr_t	overflow_databuff_vc0       : 1;
17950 		mmr_t	overflow_vc2_credit         : 1;
17951 		mmr_t	underflow_vc2_credit        : 1;
17952 		mmr_t	overflow_vc0_credit         : 1;
17953 		mmr_t	underflow_vc0_credit        : 1;
17954 		mmr_t	overflow_iilb_vc2           : 1;
17955 		mmr_t	underflow_iilb_vc2          : 1;
17956 		mmr_t	overflow_iilb_vc0           : 1;
17957 		mmr_t	underflow_iilb_vc0          : 1;
17958 		mmr_t	overflow_ni1_vc2            : 1;
17959 		mmr_t	underflow_ni1_vc2           : 1;
17960 		mmr_t	overflow_ni1_vc0            : 1;
17961 		mmr_t	underflow_ni1_vc0           : 1;
17962 		mmr_t	overflow_ni0_vc2            : 1;
17963 		mmr_t	underflow_ni0_vc2           : 1;
17964 		mmr_t	overflow_ni0_vc0            : 1;
17965 		mmr_t	underflow_ni0_vc0           : 1;
17976 	mmr_t	sh_xnmd_first_error_regval;
17978 		mmr_t	underflow_ni0_vc0           : 1;
17979 		mmr_t	overflow_ni0_vc0            : 1;
17980 		mmr_t	underflow_ni0_vc2           : 1;
17981 		mmr_t	overflow_ni0_vc2            : 1;
17982 		mmr_t	underflow_ni1_vc0           : 1;
17983 		mmr_t	overflow_ni1_vc0            : 1;
17984 		mmr_t	underflow_ni1_vc2           : 1;
17985 		mmr_t	overflow_ni1_vc2            : 1;
17986 		mmr_t	underflow_iilb_vc0          : 1;
17987 		mmr_t	overflow_iilb_vc0           : 1;
17988 		mmr_t	underflow_iilb_vc2          : 1;
17989 		mmr_t	overflow_iilb_vc2           : 1;
17990 		mmr_t	underflow_vc0_credit        : 1;
17991 		mmr_t	overflow_vc0_credit         : 1;
17992 		mmr_t	underflow_vc2_credit        : 1;
17993 		mmr_t	overflow_vc2_credit         : 1;
17994 		mmr_t	overflow_databuff_vc0       : 1;
17995 		mmr_t	overflow_databuff_vc2       : 1;
17996 		mmr_t	lut_read_error              : 1;
17997 		mmr_t	single_bit_error0           : 1;
17998 		mmr_t	single_bit_error1           : 1;
17999 		mmr_t	single_bit_error2           : 1;
18000 		mmr_t	single_bit_error3           : 1;
18001 		mmr_t	uncor_error0                : 1;
18002 		mmr_t	uncor_error1                : 1;
18003 		mmr_t	uncor_error2                : 1;
18004 		mmr_t	uncor_error3                : 1;
18005 		mmr_t	underflow_sic_cntr0         : 1;
18006 		mmr_t	overflow_sic_cntr0          : 1;
18007 		mmr_t	underflow_sic_cntr2         : 1;
18008 		mmr_t	overflow_sic_cntr2          : 1;
18009 		mmr_t	overflow_ni0_debit0         : 1;
18010 		mmr_t	overflow_ni0_debit2         : 1;
18011 		mmr_t	overflow_ni1_debit0         : 1;
18012 		mmr_t	overflow_ni1_debit2         : 1;
18013 		mmr_t	overflow_iilb_debit0        : 1;
18014 		mmr_t	overflow_iilb_debit2        : 1;
18015 		mmr_t	underflow_ni0_vc0_credit    : 1;
18016 		mmr_t	overflow_ni0_vc0_credit     : 1;
18017 		mmr_t	underflow_ni0_vc2_credit    : 1;
18018 		mmr_t	overflow_ni0_vc2_credit     : 1;
18019 		mmr_t	underflow_ni1_vc0_credit    : 1;
18020 		mmr_t	overflow_ni1_vc0_credit     : 1;
18021 		mmr_t	underflow_ni1_vc2_credit    : 1;
18022 		mmr_t	overflow_ni1_vc2_credit     : 1;
18023 		mmr_t	underflow_iilb_vc0_credit   : 1;
18024 		mmr_t	overflow_iilb_vc0_credit    : 1;
18025 		mmr_t	underflow_iilb_vc2_credit   : 1;
18026 		mmr_t	overflow_iilb_vc2_credit    : 1;
18027 		mmr_t	overflow_header_cancel_fifo : 1;
18028 		mmr_t	reserved_0                  : 14;
18033 	mmr_t	sh_xnmd_first_error_regval;
18035 		mmr_t	reserved_0                  : 14;
18036 		mmr_t	overflow_header_cancel_fifo : 1;
18037 		mmr_t	overflow_iilb_vc2_credit    : 1;
18038 		mmr_t	underflow_iilb_vc2_credit   : 1;
18039 		mmr_t	overflow_iilb_vc0_credit    : 1;
18040 		mmr_t	underflow_iilb_vc0_credit   : 1;
18041 		mmr_t	overflow_ni1_vc2_credit     : 1;
18042 		mmr_t	underflow_ni1_vc2_credit    : 1;
18043 		mmr_t	overflow_ni1_vc0_credit     : 1;
18044 		mmr_t	underflow_ni1_vc0_credit    : 1;
18045 		mmr_t	overflow_ni0_vc2_credit     : 1;
18046 		mmr_t	underflow_ni0_vc2_credit    : 1;
18047 		mmr_t	overflow_ni0_vc0_credit     : 1;
18048 		mmr_t	underflow_ni0_vc0_credit    : 1;
18049 		mmr_t	overflow_iilb_debit2        : 1;
18050 		mmr_t	overflow_iilb_debit0        : 1;
18051 		mmr_t	overflow_ni1_debit2         : 1;
18052 		mmr_t	overflow_ni1_debit0         : 1;
18053 		mmr_t	overflow_ni0_debit2         : 1;
18054 		mmr_t	overflow_ni0_debit0         : 1;
18055 		mmr_t	overflow_sic_cntr2          : 1;
18056 		mmr_t	underflow_sic_cntr2         : 1;
18057 		mmr_t	overflow_sic_cntr0          : 1;
18058 		mmr_t	underflow_sic_cntr0         : 1;
18059 		mmr_t	uncor_error3                : 1;
18060 		mmr_t	uncor_error2                : 1;
18061 		mmr_t	uncor_error1                : 1;
18062 		mmr_t	uncor_error0                : 1;
18063 		mmr_t	single_bit_error3           : 1;
18064 		mmr_t	single_bit_error2           : 1;
18065 		mmr_t	single_bit_error1           : 1;
18066 		mmr_t	single_bit_error0           : 1;
18067 		mmr_t	lut_read_error              : 1;
18068 		mmr_t	overflow_databuff_vc2       : 1;
18069 		mmr_t	overflow_databuff_vc0       : 1;
18070 		mmr_t	overflow_vc2_credit         : 1;
18071 		mmr_t	underflow_vc2_credit        : 1;
18072 		mmr_t	overflow_vc0_credit         : 1;
18073 		mmr_t	underflow_vc0_credit        : 1;
18074 		mmr_t	overflow_iilb_vc2           : 1;
18075 		mmr_t	underflow_iilb_vc2          : 1;
18076 		mmr_t	overflow_iilb_vc0           : 1;
18077 		mmr_t	underflow_iilb_vc0          : 1;
18078 		mmr_t	overflow_ni1_vc2            : 1;
18079 		mmr_t	underflow_ni1_vc2           : 1;
18080 		mmr_t	overflow_ni1_vc0            : 1;
18081 		mmr_t	underflow_ni1_vc0           : 1;
18082 		mmr_t	overflow_ni0_vc2            : 1;
18083 		mmr_t	underflow_ni0_vc2           : 1;
18084 		mmr_t	overflow_ni0_vc0            : 1;
18085 		mmr_t	underflow_ni0_vc0           : 1;
18097 	mmr_t	sh_auto_reply_enable0_regval;
18099 		mmr_t	enable0     : 64;
18104 	mmr_t	sh_auto_reply_enable0_regval;
18106 		mmr_t	enable0     : 64;
18118 	mmr_t	sh_auto_reply_enable1_regval;
18120 		mmr_t	enable1     : 64;
18125 	mmr_t	sh_auto_reply_enable1_regval;
18127 		mmr_t	enable1     : 64;
18139 	mmr_t	sh_auto_reply_header0_regval;
18141 		mmr_t	header0     : 64;
18146 	mmr_t	sh_auto_reply_header0_regval;
18148 		mmr_t	header0     : 64;
18160 	mmr_t	sh_auto_reply_header1_regval;
18162 		mmr_t	header1     : 64;
18167 	mmr_t	sh_auto_reply_header1_regval;
18169 		mmr_t	header1     : 64;
18181 	mmr_t	sh_enable_rp_auto_reply_regval;
18183 		mmr_t	enable      : 1;
18184 		mmr_t	reserved_0  : 63;
18189 	mmr_t	sh_enable_rp_auto_reply_regval;
18191 		mmr_t	reserved_0  : 63;
18192 		mmr_t	enable      : 1;
18204 	mmr_t	sh_enable_rq_auto_reply_regval;
18206 		mmr_t	enable      : 1;
18207 		mmr_t	reserved_0  : 63;
18212 	mmr_t	sh_enable_rq_auto_reply_regval;
18214 		mmr_t	reserved_0  : 63;
18215 		mmr_t	enable      : 1;
18227 	mmr_t	sh_redirect_inval_regval;
18229 		mmr_t	redirect    : 1;
18230 		mmr_t	reserved_0  : 63;
18235 	mmr_t	sh_redirect_inval_regval;
18237 		mmr_t	reserved_0  : 63;
18238 		mmr_t	redirect    : 1;
18250 	mmr_t	sh_diag_msg_cntrl_regval;
18252 		mmr_t	msg_length          : 6;
18253 		mmr_t	error_inject_point  : 6;
18254 		mmr_t	error_inject_enable : 1;
18255 		mmr_t	port                : 1;
18256 		mmr_t	reserved_0          : 48;
18257 		mmr_t	start               : 1;
18258 		mmr_t	busy                : 1;
18263 	mmr_t	sh_diag_msg_cntrl_regval;
18265 		mmr_t	busy                : 1;
18266 		mmr_t	start               : 1;
18267 		mmr_t	reserved_0          : 48;
18268 		mmr_t	port                : 1;
18269 		mmr_t	error_inject_enable : 1;
18270 		mmr_t	error_inject_point  : 6;
18271 		mmr_t	msg_length          : 6;
18283 	mmr_t	sh_diag_msg_data0l_regval;
18285 		mmr_t	data_lower  : 64;
18290 	mmr_t	sh_diag_msg_data0l_regval;
18292 		mmr_t	data_lower  : 64;
18304 	mmr_t	sh_diag_msg_data0u_regval;
18306 		mmr_t	data_upper  : 64;
18311 	mmr_t	sh_diag_msg_data0u_regval;
18313 		mmr_t	data_upper  : 64;
18325 	mmr_t	sh_diag_msg_data1l_regval;
18327 		mmr_t	data_lower  : 64;
18332 	mmr_t	sh_diag_msg_data1l_regval;
18334 		mmr_t	data_lower  : 64;
18346 	mmr_t	sh_diag_msg_data1u_regval;
18348 		mmr_t	data_upper  : 64;
18353 	mmr_t	sh_diag_msg_data1u_regval;
18355 		mmr_t	data_upper  : 64;
18367 	mmr_t	sh_diag_msg_data2l_regval;
18369 		mmr_t	data_lower  : 64;
18374 	mmr_t	sh_diag_msg_data2l_regval;
18376 		mmr_t	data_lower  : 64;
18388 	mmr_t	sh_diag_msg_data2u_regval;
18390 		mmr_t	data_upper  : 64;
18395 	mmr_t	sh_diag_msg_data2u_regval;
18397 		mmr_t	data_upper  : 64;
18409 	mmr_t	sh_diag_msg_data3l_regval;
18411 		mmr_t	data_lower  : 64;
18416 	mmr_t	sh_diag_msg_data3l_regval;
18418 		mmr_t	data_lower  : 64;
18430 	mmr_t	sh_diag_msg_data3u_regval;
18432 		mmr_t	data_upper  : 64;
18437 	mmr_t	sh_diag_msg_data3u_regval;
18439 		mmr_t	data_upper  : 64;
18451 	mmr_t	sh_diag_msg_data4l_regval;
18453 		mmr_t	data_lower  : 64;
18458 	mmr_t	sh_diag_msg_data4l_regval;
18460 		mmr_t	data_lower  : 64;
18472 	mmr_t	sh_diag_msg_data4u_regval;
18474 		mmr_t	data_upper  : 64;
18479 	mmr_t	sh_diag_msg_data4u_regval;
18481 		mmr_t	data_upper  : 64;
18493 	mmr_t	sh_diag_msg_data5l_regval;
18495 		mmr_t	data_lower  : 64;
18500 	mmr_t	sh_diag_msg_data5l_regval;
18502 		mmr_t	data_lower  : 64;
18514 	mmr_t	sh_diag_msg_data5u_regval;
18516 		mmr_t	data_upper  : 64;
18521 	mmr_t	sh_diag_msg_data5u_regval;
18523 		mmr_t	data_upper  : 64;
18535 	mmr_t	sh_diag_msg_data6l_regval;
18537 		mmr_t	data_lower  : 64;
18542 	mmr_t	sh_diag_msg_data6l_regval;
18544 		mmr_t	data_lower  : 64;
18556 	mmr_t	sh_diag_msg_data6u_regval;
18558 		mmr_t	data_upper  : 64;
18563 	mmr_t	sh_diag_msg_data6u_regval;
18565 		mmr_t	data_upper  : 64;
18577 	mmr_t	sh_diag_msg_data7l_regval;
18579 		mmr_t	data_lower  : 64;
18584 	mmr_t	sh_diag_msg_data7l_regval;
18586 		mmr_t	data_lower  : 64;
18598 	mmr_t	sh_diag_msg_data7u_regval;
18600 		mmr_t	data_upper  : 64;
18605 	mmr_t	sh_diag_msg_data7u_regval;
18607 		mmr_t	data_upper  : 64;
18619 	mmr_t	sh_diag_msg_data8l_regval;
18621 		mmr_t	data_lower  : 64;
18626 	mmr_t	sh_diag_msg_data8l_regval;
18628 		mmr_t	data_lower  : 64;
18640 	mmr_t	sh_diag_msg_data8u_regval;
18642 		mmr_t	data_upper  : 64;
18647 	mmr_t	sh_diag_msg_data8u_regval;
18649 		mmr_t	data_upper  : 64;
18661 	mmr_t	sh_diag_msg_hdr0_regval;
18663 		mmr_t	header0     : 64;
18668 	mmr_t	sh_diag_msg_hdr0_regval;
18670 		mmr_t	header0     : 64;
18682 	mmr_t	sh_diag_msg_hdr1_regval;
18684 		mmr_t	header1     : 64;
18689 	mmr_t	sh_diag_msg_hdr1_regval;
18691 		mmr_t	header1     : 64;
18703 	mmr_t	sh_debug_select_regval;
18705 		mmr_t	nibble0_nibble_sel  : 3;
18706 		mmr_t	nibble0_chiplet_sel : 3;
18707 		mmr_t	nibble1_nibble_sel  : 3;
18708 		mmr_t	nibble1_chiplet_sel : 3;
18709 		mmr_t	nibble2_nibble_sel  : 3;
18710 		mmr_t	nibble2_chiplet_sel : 3;
18711 		mmr_t	nibble3_nibble_sel  : 3;
18712 		mmr_t	nibble3_chiplet_sel : 3;
18713 		mmr_t	nibble4_nibble_sel  : 3;
18714 		mmr_t	nibble4_chiplet_sel : 3;
18715 		mmr_t	nibble5_nibble_sel  : 3;
18716 		mmr_t	nibble5_chiplet_sel : 3;
18717 		mmr_t	nibble6_nibble_sel  : 3;
18718 		mmr_t	nibble6_chiplet_sel : 3;
18719 		mmr_t	nibble7_nibble_sel  : 3;
18720 		mmr_t	nibble7_chiplet_sel : 3;
18721 		mmr_t	debug_ii_sel        : 3;
18722 		mmr_t	sel_ii              : 9;
18723 		mmr_t	reserved_0          : 3;
18724 		mmr_t	trigger_enable      : 1;
18729 	mmr_t	sh_debug_select_regval;
18731 		mmr_t	trigger_enable      : 1;
18732 		mmr_t	reserved_0          : 3;
18733 		mmr_t	sel_ii              : 9;
18734 		mmr_t	debug_ii_sel        : 3;
18735 		mmr_t	nibble7_chiplet_sel : 3;
18736 		mmr_t	nibble7_nibble_sel  : 3;
18737 		mmr_t	nibble6_chiplet_sel : 3;
18738 		mmr_t	nibble6_nibble_sel  : 3;
18739 		mmr_t	nibble5_chiplet_sel : 3;
18740 		mmr_t	nibble5_nibble_sel  : 3;
18741 		mmr_t	nibble4_chiplet_sel : 3;
18742 		mmr_t	nibble4_nibble_sel  : 3;
18743 		mmr_t	nibble3_chiplet_sel : 3;
18744 		mmr_t	nibble3_nibble_sel  : 3;
18745 		mmr_t	nibble2_chiplet_sel : 3;
18746 		mmr_t	nibble2_nibble_sel  : 3;
18747 		mmr_t	nibble1_chiplet_sel : 3;
18748 		mmr_t	nibble1_nibble_sel  : 3;
18749 		mmr_t	nibble0_chiplet_sel : 3;
18750 		mmr_t	nibble0_nibble_sel  : 3;
18762 	mmr_t	sh_trigger_compare_mask_regval;
18764 		mmr_t	mask        : 32;
18765 		mmr_t	reserved_0  : 32;
18770 	mmr_t	sh_trigger_compare_mask_regval;
18772 		mmr_t	reserved_0  : 32;
18773 		mmr_t	mask        : 32;
18785 	mmr_t	sh_trigger_compare_pattern_regval;
18787 		mmr_t	data        : 32;
18788 		mmr_t	reserved_0  : 32;
18793 	mmr_t	sh_trigger_compare_pattern_regval;
18795 		mmr_t	reserved_0  : 32;
18796 		mmr_t	data        : 32;
18808 	mmr_t	sh_trigger_sel_regval;
18810 		mmr_t	nibble0_input_sel  : 3;
18811 		mmr_t	reserved_0         : 1;
18812 		mmr_t	nibble0_nibble_sel : 3;
18813 		mmr_t	reserved_1         : 1;
18814 		mmr_t	nibble1_input_sel  : 3;
18815 		mmr_t	reserved_2         : 1;
18816 		mmr_t	nibble1_nibble_sel : 3;
18817 		mmr_t	reserved_3         : 1;
18818 		mmr_t	nibble2_input_sel  : 3;
18819 		mmr_t	reserved_4         : 1;
18820 		mmr_t	nibble2_nibble_sel : 3;
18821 		mmr_t	reserved_5         : 1;
18822 		mmr_t	nibble3_input_sel  : 3;
18823 		mmr_t	reserved_6         : 1;
18824 		mmr_t	nibble3_nibble_sel : 3;
18825 		mmr_t	reserved_7         : 1;
18826 		mmr_t	nibble4_input_sel  : 3;
18827 		mmr_t	reserved_8         : 1;
18828 		mmr_t	nibble4_nibble_sel : 3;
18829 		mmr_t	reserved_9         : 1;
18830 		mmr_t	nibble5_input_sel  : 3;
18831 		mmr_t	reserved_10        : 1;
18832 		mmr_t	nibble5_nibble_sel : 3;
18833 		mmr_t	reserved_11        : 1;
18834 		mmr_t	nibble6_input_sel  : 3;
18835 		mmr_t	reserved_12        : 1;
18836 		mmr_t	nibble6_nibble_sel : 3;
18837 		mmr_t	reserved_13        : 1;
18838 		mmr_t	nibble7_input_sel  : 3;
18839 		mmr_t	reserved_14        : 1;
18840 		mmr_t	nibble7_nibble_sel : 3;
18841 		mmr_t	reserved_15        : 1;
18846 	mmr_t	sh_trigger_sel_regval;
18848 		mmr_t	reserved_15        : 1;
18849 		mmr_t	nibble7_nibble_sel : 3;
18850 		mmr_t	reserved_14        : 1;
18851 		mmr_t	nibble7_input_sel  : 3;
18852 		mmr_t	reserved_13        : 1;
18853 		mmr_t	nibble6_nibble_sel : 3;
18854 		mmr_t	reserved_12        : 1;
18855 		mmr_t	nibble6_input_sel  : 3;
18856 		mmr_t	reserved_11        : 1;
18857 		mmr_t	nibble5_nibble_sel : 3;
18858 		mmr_t	reserved_10        : 1;
18859 		mmr_t	nibble5_input_sel  : 3;
18860 		mmr_t	reserved_9         : 1;
18861 		mmr_t	nibble4_nibble_sel : 3;
18862 		mmr_t	reserved_8         : 1;
18863 		mmr_t	nibble4_input_sel  : 3;
18864 		mmr_t	reserved_7         : 1;
18865 		mmr_t	nibble3_nibble_sel : 3;
18866 		mmr_t	reserved_6         : 1;
18867 		mmr_t	nibble3_input_sel  : 3;
18868 		mmr_t	reserved_5         : 1;
18869 		mmr_t	nibble2_nibble_sel : 3;
18870 		mmr_t	reserved_4         : 1;
18871 		mmr_t	nibble2_input_sel  : 3;
18872 		mmr_t	reserved_3         : 1;
18873 		mmr_t	nibble1_nibble_sel : 3;
18874 		mmr_t	reserved_2         : 1;
18875 		mmr_t	nibble1_input_sel  : 3;
18876 		mmr_t	reserved_1         : 1;
18877 		mmr_t	nibble0_nibble_sel : 3;
18878 		mmr_t	reserved_0         : 1;
18879 		mmr_t	nibble0_input_sel  : 3;
18891 	mmr_t	sh_stop_clk_control_regval;
18893 		mmr_t	stimulus    : 5;
18894 		mmr_t	event       : 1;
18895 		mmr_t	polarity    : 1;
18896 		mmr_t	mode        : 1;
18897 		mmr_t	reserved_0  : 56;
18902 	mmr_t	sh_stop_clk_control_regval;
18904 		mmr_t	reserved_0  : 56;
18905 		mmr_t	mode        : 1;
18906 		mmr_t	polarity    : 1;
18907 		mmr_t	event       : 1;
18908 		mmr_t	stimulus    : 5;
18920 	mmr_t	sh_stop_clk_delay_phase_regval;
18922 		mmr_t	delay       : 8;
18923 		mmr_t	reserved_0  : 56;
18928 	mmr_t	sh_stop_clk_delay_phase_regval;
18930 		mmr_t	reserved_0  : 56;
18931 		mmr_t	delay       : 8;
18943 	mmr_t	sh_tsf_arm_mask_regval;
18945 		mmr_t	mask        : 64;
18950 	mmr_t	sh_tsf_arm_mask_regval;
18952 		mmr_t	mask        : 64;
18964 	mmr_t	sh_tsf_counter_presets_regval;
18966 		mmr_t	count_32    : 32;
18967 		mmr_t	count_16    : 16;
18968 		mmr_t	count_8b    : 8;
18969 		mmr_t	count_8a    : 8;
18974 	mmr_t	sh_tsf_counter_presets_regval;
18976 		mmr_t	count_8a    : 8;
18977 		mmr_t	count_8b    : 8;
18978 		mmr_t	count_16    : 16;
18979 		mmr_t	count_32    : 32;
18991 	mmr_t	sh_tsf_decrement_ctl_regval;
18993 		mmr_t	ctl         : 16;
18994 		mmr_t	reserved_0  : 48;
18999 	mmr_t	sh_tsf_decrement_ctl_regval;
19001 		mmr_t	reserved_0  : 48;
19002 		mmr_t	ctl         : 16;
19014 	mmr_t	sh_tsf_diag_msg_ctl_regval;
19016 		mmr_t	enable      : 8;
19017 		mmr_t	reserved_0  : 56;
19022 	mmr_t	sh_tsf_diag_msg_ctl_regval;
19024 		mmr_t	reserved_0  : 56;
19025 		mmr_t	enable      : 8;
19037 	mmr_t	sh_tsf_disarm_mask_regval;
19039 		mmr_t	mask        : 64;
19044 	mmr_t	sh_tsf_disarm_mask_regval;
19046 		mmr_t	mask        : 64;
19058 	mmr_t	sh_tsf_enable_ctl_regval;
19060 		mmr_t	ctl         : 16;
19061 		mmr_t	reserved_0  : 48;
19066 	mmr_t	sh_tsf_enable_ctl_regval;
19068 		mmr_t	reserved_0  : 48;
19069 		mmr_t	ctl         : 16;
19081 	mmr_t	sh_tsf_software_arm_regval;
19083 		mmr_t	bit0        : 1;
19084 		mmr_t	bit1        : 1;
19085 		mmr_t	bit2        : 1;
19086 		mmr_t	bit3        : 1;
19087 		mmr_t	bit4        : 1;
19088 		mmr_t	bit5        : 1;
19089 		mmr_t	bit6        : 1;
19090 		mmr_t	bit7        : 1;
19091 		mmr_t	reserved_0  : 56;
19096 	mmr_t	sh_tsf_software_arm_regval;
19098 		mmr_t	reserved_0  : 56;
19099 		mmr_t	bit7        : 1;
19100 		mmr_t	bit6        : 1;
19101 		mmr_t	bit5        : 1;
19102 		mmr_t	bit4        : 1;
19103 		mmr_t	bit3        : 1;
19104 		mmr_t	bit2        : 1;
19105 		mmr_t	bit1        : 1;
19106 		mmr_t	bit0        : 1;
19118 	mmr_t	sh_tsf_software_disarm_regval;
19120 		mmr_t	bit0        : 1;
19121 		mmr_t	bit1        : 1;
19122 		mmr_t	bit2        : 1;
19123 		mmr_t	bit3        : 1;
19124 		mmr_t	bit4        : 1;
19125 		mmr_t	bit5        : 1;
19126 		mmr_t	bit6        : 1;
19127 		mmr_t	bit7        : 1;
19128 		mmr_t	reserved_0  : 56;
19133 	mmr_t	sh_tsf_software_disarm_regval;
19135 		mmr_t	reserved_0  : 56;
19136 		mmr_t	bit7        : 1;
19137 		mmr_t	bit6        : 1;
19138 		mmr_t	bit5        : 1;
19139 		mmr_t	bit4        : 1;
19140 		mmr_t	bit3        : 1;
19141 		mmr_t	bit2        : 1;
19142 		mmr_t	bit1        : 1;
19143 		mmr_t	bit0        : 1;
19155 	mmr_t	sh_tsf_software_triggered_regval;
19157 		mmr_t	bit0        : 1;
19158 		mmr_t	bit1        : 1;
19159 		mmr_t	bit2        : 1;
19160 		mmr_t	bit3        : 1;
19161 		mmr_t	bit4        : 1;
19162 		mmr_t	bit5        : 1;
19163 		mmr_t	bit6        : 1;
19164 		mmr_t	bit7        : 1;
19165 		mmr_t	reserved_0  : 56;
19170 	mmr_t	sh_tsf_software_triggered_regval;
19172 		mmr_t	reserved_0  : 56;
19173 		mmr_t	bit7        : 1;
19174 		mmr_t	bit6        : 1;
19175 		mmr_t	bit5        : 1;
19176 		mmr_t	bit4        : 1;
19177 		mmr_t	bit3        : 1;
19178 		mmr_t	bit2        : 1;
19179 		mmr_t	bit1        : 1;
19180 		mmr_t	bit0        : 1;
19192 	mmr_t	sh_tsf_trigger_mask_regval;
19194 		mmr_t	mask        : 64;
19199 	mmr_t	sh_tsf_trigger_mask_regval;
19201 		mmr_t	mask        : 64;
19213 	mmr_t	sh_vec_data_regval;
19215 		mmr_t	data        : 64;
19220 	mmr_t	sh_vec_data_regval;
19222 		mmr_t	data        : 64;
19234 	mmr_t	sh_vec_parms_regval;
19236 		mmr_t	type        : 1;
19237 		mmr_t	ni_port     : 1;
19238 		mmr_t	reserved_0  : 1;
19239 		mmr_t	address     : 32;
19240 		mmr_t	pio_id      : 11;
19241 		mmr_t	reserved_1  : 16;
19242 		mmr_t	start       : 1;
19243 		mmr_t	busy        : 1;
19248 	mmr_t	sh_vec_parms_regval;
19250 		mmr_t	busy        : 1;
19251 		mmr_t	start       : 1;
19252 		mmr_t	reserved_1  : 16;
19253 		mmr_t	pio_id      : 11;
19254 		mmr_t	address     : 32;
19255 		mmr_t	reserved_0  : 1;
19256 		mmr_t	ni_port     : 1;
19257 		mmr_t	type        : 1;
19269 	mmr_t	sh_vec_route_regval;
19271 		mmr_t	route       : 64;
19276 	mmr_t	sh_vec_route_regval;
19278 		mmr_t	route       : 64;
19290 	mmr_t	sh_cpu_perm_regval;
19292 		mmr_t	access_bits : 64;
19297 	mmr_t	sh_cpu_perm_regval;
19299 		mmr_t	access_bits : 64;
19311 	mmr_t	sh_cpu_perm_ovr_regval;
19313 		mmr_t	override    : 64;
19318 	mmr_t	sh_cpu_perm_ovr_regval;
19320 		mmr_t	override    : 64;
19332 	mmr_t	sh_ext_io_perm_regval;
19334 		mmr_t	access_bits : 64;
19339 	mmr_t	sh_ext_io_perm_regval;
19341 		mmr_t	access_bits : 64;
19353 	mmr_t	sh_ext_ioi_access_regval;
19355 		mmr_t	access_bits : 64;
19360 	mmr_t	sh_ext_ioi_access_regval;
19362 		mmr_t	access_bits : 64;
19374 	mmr_t	sh_gc_fil_ctrl_regval;
19376 		mmr_t	offset          : 5;
19377 		mmr_t	reserved_0      : 3;
19378 		mmr_t	mask_counter    : 12;
19379 		mmr_t	mask_enable     : 1;
19380 		mmr_t	reserved_1      : 3;
19381 		mmr_t	dropout_counter : 10;
19382 		mmr_t	reserved_2      : 2;
19383 		mmr_t	dropout_thresh  : 10;
19384 		mmr_t	reserved_3      : 2;
19385 		mmr_t	error_counter   : 10;
19386 		mmr_t	reserved_4      : 6;
19391 	mmr_t	sh_gc_fil_ctrl_regval;
19393 		mmr_t	reserved_4      : 6;
19394 		mmr_t	error_counter   : 10;
19395 		mmr_t	reserved_3      : 2;
19396 		mmr_t	dropout_thresh  : 10;
19397 		mmr_t	reserved_2      : 2;
19398 		mmr_t	dropout_counter : 10;
19399 		mmr_t	reserved_1      : 3;
19400 		mmr_t	mask_enable     : 1;
19401 		mmr_t	mask_counter    : 12;
19402 		mmr_t	reserved_0      : 3;
19403 		mmr_t	offset          : 5;
19415 	mmr_t	sh_gc_src_ctrl_regval;
19417 		mmr_t	enable_counter : 1;
19418 		mmr_t	reserved_0     : 3;
19419 		mmr_t	max_count      : 10;
19420 		mmr_t	reserved_1     : 2;
19421 		mmr_t	counter        : 10;
19422 		mmr_t	reserved_2     : 2;
19423 		mmr_t	toggle_bit     : 1;
19424 		mmr_t	reserved_3     : 3;
19425 		mmr_t	source_sel     : 2;
19426 		mmr_t	reserved_4     : 30;
19431 	mmr_t	sh_gc_src_ctrl_regval;
19433 		mmr_t	reserved_4     : 30;
19434 		mmr_t	source_sel     : 2;
19435 		mmr_t	reserved_3     : 3;
19436 		mmr_t	toggle_bit     : 1;
19437 		mmr_t	reserved_2     : 2;
19438 		mmr_t	counter        : 10;
19439 		mmr_t	reserved_1     : 2;
19440 		mmr_t	max_count      : 10;
19441 		mmr_t	reserved_0     : 3;
19442 		mmr_t	enable_counter : 1;
19454 	mmr_t	sh_hard_reset_regval;
19456 		mmr_t	hard_reset  : 1;
19457 		mmr_t	reserved_0  : 63;
19462 	mmr_t	sh_hard_reset_regval;
19464 		mmr_t	reserved_0  : 63;
19465 		mmr_t	hard_reset  : 1;
19477 	mmr_t	sh_io_perm_regval;
19479 		mmr_t	access_bits : 64;
19484 	mmr_t	sh_io_perm_regval;
19486 		mmr_t	access_bits : 64;
19498 	mmr_t	sh_ioi_access_regval;
19500 		mmr_t	access_bits : 64;
19505 	mmr_t	sh_ioi_access_regval;
19507 		mmr_t	access_bits : 64;
19519 	mmr_t	sh_ipi_access_regval;
19521 		mmr_t	access_bits : 64;
19526 	mmr_t	sh_ipi_access_regval;
19528 		mmr_t	access_bits : 64;
19540 	mmr_t	sh_jtag_config_regval;
19542 		mmr_t	md_clk_sel                    : 2;
19543 		mmr_t	ni_clk_sel                    : 1;
19544 		mmr_t	ii_clk_sel                    : 2;
19545 		mmr_t	wrt90_target                  : 14;
19546 		mmr_t	wrt90_overrider               : 1;
19547 		mmr_t	wrt90_override                : 1;
19548 		mmr_t	jtag_mci_reset_delay          : 4;
19549 		mmr_t	jtag_mci_target               : 14;
19550 		mmr_t	jtag_mci_override             : 1;
19551 		mmr_t	fsb_config_ioq_depth          : 1;
19552 		mmr_t	fsb_config_sample_binit       : 1;
19553 		mmr_t	fsb_config_enable_bus_parking : 1;
19554 		mmr_t	fsb_config_clock_ratio        : 5;
19555 		mmr_t	fsb_config_output_tristate    : 4;
19556 		mmr_t	fsb_config_enable_bist        : 1;
19557 		mmr_t	fsb_config_aux                : 2;
19558 		mmr_t	gtl_config_re                 : 1;
19559 		mmr_t	reserved_0                    : 8;
19564 	mmr_t	sh_jtag_config_regval;
19566 		mmr_t	reserved_0                    : 8;
19567 		mmr_t	gtl_config_re                 : 1;
19568 		mmr_t	fsb_config_aux                : 2;
19569 		mmr_t	fsb_config_enable_bist        : 1;
19570 		mmr_t	fsb_config_output_tristate    : 4;
19571 		mmr_t	fsb_config_clock_ratio        : 5;
19572 		mmr_t	fsb_config_enable_bus_parking : 1;
19573 		mmr_t	fsb_config_sample_binit       : 1;
19574 		mmr_t	fsb_config_ioq_depth          : 1;
19575 		mmr_t	jtag_mci_override             : 1;
19576 		mmr_t	jtag_mci_target               : 14;
19577 		mmr_t	jtag_mci_reset_delay          : 4;
19578 		mmr_t	wrt90_override                : 1;
19579 		mmr_t	wrt90_overrider               : 1;
19580 		mmr_t	wrt90_target                  : 14;
19581 		mmr_t	ii_clk_sel                    : 2;
19582 		mmr_t	ni_clk_sel                    : 1;
19583 		mmr_t	md_clk_sel                    : 2;
19595 	mmr_t	sh_shub_id_regval;
19597 		mmr_t	force1        : 1;
19598 		mmr_t	manufacturer  : 11;
19599 		mmr_t	part_number   : 16;
19600 		mmr_t	revision      : 4;
19601 		mmr_t	node_id       : 11;
19602 		mmr_t	reserved_0    : 1;
19603 		mmr_t	sharing_mode  : 2;
19604 		mmr_t	reserved_1    : 2;
19605 		mmr_t	nodes_per_bit : 5;
19606 		mmr_t	reserved_2    : 3;
19607 		mmr_t	ni_port       : 1;
19608 		mmr_t	reserved_3    : 7;
19613 	mmr_t	sh_shub_id_regval;
19615 		mmr_t	reserved_3    : 7;
19616 		mmr_t	ni_port       : 1;
19617 		mmr_t	reserved_2    : 3;
19618 		mmr_t	nodes_per_bit : 5;
19619 		mmr_t	reserved_1    : 2;
19620 		mmr_t	sharing_mode  : 2;
19621 		mmr_t	reserved_0    : 1;
19622 		mmr_t	node_id       : 11;
19623 		mmr_t	revision      : 4;
19624 		mmr_t	part_number   : 16;
19625 		mmr_t	manufacturer  : 11;
19626 		mmr_t	force1        : 1;
19638 	mmr_t	sh_shubs_present0_regval;
19640 		mmr_t	shubs_present0 : 64;
19645 	mmr_t	sh_shubs_present0_regval;
19647 		mmr_t	shubs_present0 : 64;
19659 	mmr_t	sh_shubs_present1_regval;
19661 		mmr_t	shubs_present1 : 64;
19666 	mmr_t	sh_shubs_present1_regval;
19668 		mmr_t	shubs_present1 : 64;
19680 	mmr_t	sh_shubs_present2_regval;
19682 		mmr_t	shubs_present2 : 64;
19687 	mmr_t	sh_shubs_present2_regval;
19689 		mmr_t	shubs_present2 : 64;
19701 	mmr_t	sh_shubs_present3_regval;
19703 		mmr_t	shubs_present3 : 64;
19708 	mmr_t	sh_shubs_present3_regval;
19710 		mmr_t	shubs_present3 : 64;
19722 	mmr_t	sh_soft_reset_regval;
19724 		mmr_t	soft_reset  : 1;
19725 		mmr_t	reserved_0  : 63;
19730 	mmr_t	sh_soft_reset_regval;
19732 		mmr_t	reserved_0  : 63;
19733 		mmr_t	soft_reset  : 1;
19745 	mmr_t	sh_first_error_regval;
19747 		mmr_t	first_error : 19;
19748 		mmr_t	reserved_0  : 45;
19753 	mmr_t	sh_first_error_regval;
19755 		mmr_t	reserved_0  : 45;
19756 		mmr_t	first_error : 19;
19768 	mmr_t	sh_ii_hw_time_stamp_regval;
19770 		mmr_t	time        : 63;
19771 		mmr_t	valid       : 1;
19776 	mmr_t	sh_ii_hw_time_stamp_regval;
19778 		mmr_t	valid       : 1;
19779 		mmr_t	time        : 63;
19791 	mmr_t	sh_lb_hw_time_stamp_regval;
19793 		mmr_t	time        : 63;
19794 		mmr_t	valid       : 1;
19799 	mmr_t	sh_lb_hw_time_stamp_regval;
19801 		mmr_t	valid       : 1;
19802 		mmr_t	time        : 63;
19814 	mmr_t	sh_md_cor_time_stamp_regval;
19816 		mmr_t	time        : 63;
19817 		mmr_t	valid       : 1;
19822 	mmr_t	sh_md_cor_time_stamp_regval;
19824 		mmr_t	valid       : 1;
19825 		mmr_t	time        : 63;
19837 	mmr_t	sh_md_hw_time_stamp_regval;
19839 		mmr_t	time        : 63;
19840 		mmr_t	valid       : 1;
19845 	mmr_t	sh_md_hw_time_stamp_regval;
19847 		mmr_t	valid       : 1;
19848 		mmr_t	time        : 63;
19860 	mmr_t	sh_md_uncor_time_stamp_regval;
19862 		mmr_t	time        : 63;
19863 		mmr_t	valid       : 1;
19868 	mmr_t	sh_md_uncor_time_stamp_regval;
19870 		mmr_t	valid       : 1;
19871 		mmr_t	time        : 63;
19883 	mmr_t	sh_pi_cor_time_stamp_regval;
19885 		mmr_t	time        : 63;
19886 		mmr_t	valid       : 1;
19891 	mmr_t	sh_pi_cor_time_stamp_regval;
19893 		mmr_t	valid       : 1;
19894 		mmr_t	time        : 63;
19906 	mmr_t	sh_pi_hw_time_stamp_regval;
19908 		mmr_t	time        : 63;
19909 		mmr_t	valid       : 1;
19914 	mmr_t	sh_pi_hw_time_stamp_regval;
19916 		mmr_t	valid       : 1;
19917 		mmr_t	time        : 63;
19929 	mmr_t	sh_pi_uncor_time_stamp_regval;
19931 		mmr_t	time        : 63;
19932 		mmr_t	valid       : 1;
19937 	mmr_t	sh_pi_uncor_time_stamp_regval;
19939 		mmr_t	valid       : 1;
19940 		mmr_t	time        : 63;
19952 	mmr_t	sh_proc0_adv_time_stamp_regval;
19954 		mmr_t	time        : 63;
19955 		mmr_t	valid       : 1;
19960 	mmr_t	sh_proc0_adv_time_stamp_regval;
19962 		mmr_t	valid       : 1;
19963 		mmr_t	time        : 63;
19975 	mmr_t	sh_proc0_err_time_stamp_regval;
19977 		mmr_t	time        : 63;
19978 		mmr_t	valid       : 1;
19983 	mmr_t	sh_proc0_err_time_stamp_regval;
19985 		mmr_t	valid       : 1;
19986 		mmr_t	time        : 63;
19998 	mmr_t	sh_proc1_adv_time_stamp_regval;
20000 		mmr_t	time        : 63;
20001 		mmr_t	valid       : 1;
20006 	mmr_t	sh_proc1_adv_time_stamp_regval;
20008 		mmr_t	valid       : 1;
20009 		mmr_t	time        : 63;
20021 	mmr_t	sh_proc1_err_time_stamp_regval;
20023 		mmr_t	time        : 63;
20024 		mmr_t	valid       : 1;
20029 	mmr_t	sh_proc1_err_time_stamp_regval;
20031 		mmr_t	valid       : 1;
20032 		mmr_t	time        : 63;
20044 	mmr_t	sh_proc2_adv_time_stamp_regval;
20046 		mmr_t	time        : 63;
20047 		mmr_t	valid       : 1;
20052 	mmr_t	sh_proc2_adv_time_stamp_regval;
20054 		mmr_t	valid       : 1;
20055 		mmr_t	time        : 63;
20067 	mmr_t	sh_proc2_err_time_stamp_regval;
20069 		mmr_t	time        : 63;
20070 		mmr_t	valid       : 1;
20075 	mmr_t	sh_proc2_err_time_stamp_regval;
20077 		mmr_t	valid       : 1;
20078 		mmr_t	time        : 63;
20090 	mmr_t	sh_proc3_adv_time_stamp_regval;
20092 		mmr_t	time        : 63;
20093 		mmr_t	valid       : 1;
20098 	mmr_t	sh_proc3_adv_time_stamp_regval;
20100 		mmr_t	valid       : 1;
20101 		mmr_t	time        : 63;
20113 	mmr_t	sh_proc3_err_time_stamp_regval;
20115 		mmr_t	time        : 63;
20116 		mmr_t	valid       : 1;
20121 	mmr_t	sh_proc3_err_time_stamp_regval;
20123 		mmr_t	valid       : 1;
20124 		mmr_t	time        : 63;
20136 	mmr_t	sh_xn_cor_time_stamp_regval;
20138 		mmr_t	time        : 63;
20139 		mmr_t	valid       : 1;
20144 	mmr_t	sh_xn_cor_time_stamp_regval;
20146 		mmr_t	valid       : 1;
20147 		mmr_t	time        : 63;
20159 	mmr_t	sh_xn_hw_time_stamp_regval;
20161 		mmr_t	time        : 63;
20162 		mmr_t	valid       : 1;
20167 	mmr_t	sh_xn_hw_time_stamp_regval;
20169 		mmr_t	valid       : 1;
20170 		mmr_t	time        : 63;
20182 	mmr_t	sh_xn_uncor_time_stamp_regval;
20184 		mmr_t	time        : 63;
20185 		mmr_t	valid       : 1;
20190 	mmr_t	sh_xn_uncor_time_stamp_regval;
20192 		mmr_t	valid       : 1;
20193 		mmr_t	time        : 63;
20205 	mmr_t	sh_debug_port_regval;
20207 		mmr_t	debug_nibble0 : 4;
20208 		mmr_t	debug_nibble1 : 4;
20209 		mmr_t	debug_nibble2 : 4;
20210 		mmr_t	debug_nibble3 : 4;
20211 		mmr_t	debug_nibble4 : 4;
20212 		mmr_t	debug_nibble5 : 4;
20213 		mmr_t	debug_nibble6 : 4;
20214 		mmr_t	debug_nibble7 : 4;
20215 		mmr_t	reserved_0    : 32;
20220 	mmr_t	sh_debug_port_regval;
20222 		mmr_t	reserved_0    : 32;
20223 		mmr_t	debug_nibble7 : 4;
20224 		mmr_t	debug_nibble6 : 4;
20225 		mmr_t	debug_nibble5 : 4;
20226 		mmr_t	debug_nibble4 : 4;
20227 		mmr_t	debug_nibble3 : 4;
20228 		mmr_t	debug_nibble2 : 4;
20229 		mmr_t	debug_nibble1 : 4;
20230 		mmr_t	debug_nibble0 : 4;
20242 	mmr_t	sh_ii_debug_data_regval;
20244 		mmr_t	ii_data     : 32;
20245 		mmr_t	reserved_0  : 32;
20250 	mmr_t	sh_ii_debug_data_regval;
20252 		mmr_t	reserved_0  : 32;
20253 		mmr_t	ii_data     : 32;
20265 	mmr_t	sh_ii_wrap_debug_data_regval;
20267 		mmr_t	ii_wrap_data : 32;
20268 		mmr_t	reserved_0   : 32;
20273 	mmr_t	sh_ii_wrap_debug_data_regval;
20275 		mmr_t	reserved_0   : 32;
20276 		mmr_t	ii_wrap_data : 32;
20288 	mmr_t	sh_lb_debug_data_regval;
20290 		mmr_t	lb_data     : 32;
20291 		mmr_t	reserved_0  : 32;
20296 	mmr_t	sh_lb_debug_data_regval;
20298 		mmr_t	reserved_0  : 32;
20299 		mmr_t	lb_data     : 32;
20311 	mmr_t	sh_md_debug_data_regval;
20313 		mmr_t	md_data     : 32;
20314 		mmr_t	reserved_0  : 32;
20319 	mmr_t	sh_md_debug_data_regval;
20321 		mmr_t	reserved_0  : 32;
20322 		mmr_t	md_data     : 32;
20334 	mmr_t	sh_pi_debug_data_regval;
20336 		mmr_t	pi_data     : 32;
20337 		mmr_t	reserved_0  : 32;
20342 	mmr_t	sh_pi_debug_data_regval;
20344 		mmr_t	reserved_0  : 32;
20345 		mmr_t	pi_data     : 32;
20357 	mmr_t	sh_xn_debug_data_regval;
20359 		mmr_t	xn_data     : 32;
20360 		mmr_t	reserved_0  : 32;
20365 	mmr_t	sh_xn_debug_data_regval;
20367 		mmr_t	reserved_0  : 32;
20368 		mmr_t	xn_data     : 32;
20380 	mmr_t	sh_tsf_armed_state_regval;
20382 		mmr_t	state       : 8;
20383 		mmr_t	reserved_0  : 56;
20388 	mmr_t	sh_tsf_armed_state_regval;
20390 		mmr_t	reserved_0  : 56;
20391 		mmr_t	state       : 8;
20403 	mmr_t	sh_tsf_counter_value_regval;
20405 		mmr_t	count_32    : 32;
20406 		mmr_t	count_16    : 16;
20407 		mmr_t	count_8b    : 8;
20408 		mmr_t	count_8a    : 8;
20413 	mmr_t	sh_tsf_counter_value_regval;
20415 		mmr_t	count_8a    : 8;
20416 		mmr_t	count_8b    : 8;
20417 		mmr_t	count_16    : 16;
20418 		mmr_t	count_32    : 32;
20430 	mmr_t	sh_tsf_triggered_state_regval;
20432 		mmr_t	state       : 8;
20433 		mmr_t	reserved_0  : 56;
20438 	mmr_t	sh_tsf_triggered_state_regval;
20440 		mmr_t	reserved_0  : 56;
20441 		mmr_t	state       : 8;
20453 	mmr_t	sh_vec_rddata_regval;
20455 		mmr_t	data        : 64;
20460 	mmr_t	sh_vec_rddata_regval;
20462 		mmr_t	data        : 64;
20474 	mmr_t	sh_vec_return_regval;
20476 		mmr_t	route       : 64;
20481 	mmr_t	sh_vec_return_regval;
20483 		mmr_t	route       : 64;
20495 	mmr_t	sh_vec_status_regval;
20497 		mmr_t	type         : 3;
20498 		mmr_t	address      : 32;
20499 		mmr_t	pio_id       : 11;
20500 		mmr_t	source       : 14;
20501 		mmr_t	reserved_0   : 2;
20502 		mmr_t	overrun      : 1;
20503 		mmr_t	status_valid : 1;
20508 	mmr_t	sh_vec_status_regval;
20510 		mmr_t	status_valid : 1;
20511 		mmr_t	overrun      : 1;
20512 		mmr_t	reserved_0   : 2;
20513 		mmr_t	source       : 14;
20514 		mmr_t	pio_id       : 11;
20515 		mmr_t	address      : 32;
20516 		mmr_t	type         : 3;
20528 	mmr_t	sh_performance_count0_control_regval;
20530 		mmr_t	up_stimulus     : 5;
20531 		mmr_t	up_event        : 1;
20532 		mmr_t	up_polarity     : 1;
20533 		mmr_t	up_mode         : 1;
20534 		mmr_t	dn_stimulus     : 5;
20535 		mmr_t	dn_event        : 1;
20536 		mmr_t	dn_polarity     : 1;
20537 		mmr_t	dn_mode         : 1;
20538 		mmr_t	inc_enable      : 1;
20539 		mmr_t	dec_enable      : 1;
20540 		mmr_t	peak_det_enable : 1;
20541 		mmr_t	reserved_0      : 45;
20546 	mmr_t	sh_performance_count0_control_regval;
20548 		mmr_t	reserved_0      : 45;
20549 		mmr_t	peak_det_enable : 1;
20550 		mmr_t	dec_enable      : 1;
20551 		mmr_t	inc_enable      : 1;
20552 		mmr_t	dn_mode         : 1;
20553 		mmr_t	dn_polarity     : 1;
20554 		mmr_t	dn_event        : 1;
20555 		mmr_t	dn_stimulus     : 5;
20556 		mmr_t	up_mode         : 1;
20557 		mmr_t	up_polarity     : 1;
20558 		mmr_t	up_event        : 1;
20559 		mmr_t	up_stimulus     : 5;
20571 	mmr_t	sh_performance_count1_control_regval;
20573 		mmr_t	up_stimulus     : 5;
20574 		mmr_t	up_event        : 1;
20575 		mmr_t	up_polarity     : 1;
20576 		mmr_t	up_mode         : 1;
20577 		mmr_t	dn_stimulus     : 5;
20578 		mmr_t	dn_event        : 1;
20579 		mmr_t	dn_polarity     : 1;
20580 		mmr_t	dn_mode         : 1;
20581 		mmr_t	inc_enable      : 1;
20582 		mmr_t	dec_enable      : 1;
20583 		mmr_t	peak_det_enable : 1;
20584 		mmr_t	reserved_0      : 45;
20589 	mmr_t	sh_performance_count1_control_regval;
20591 		mmr_t	reserved_0      : 45;
20592 		mmr_t	peak_det_enable : 1;
20593 		mmr_t	dec_enable      : 1;
20594 		mmr_t	inc_enable      : 1;
20595 		mmr_t	dn_mode         : 1;
20596 		mmr_t	dn_polarity     : 1;
20597 		mmr_t	dn_event        : 1;
20598 		mmr_t	dn_stimulus     : 5;
20599 		mmr_t	up_mode         : 1;
20600 		mmr_t	up_polarity     : 1;
20601 		mmr_t	up_event        : 1;
20602 		mmr_t	up_stimulus     : 5;
20614 	mmr_t	sh_performance_count2_control_regval;
20616 		mmr_t	up_stimulus     : 5;
20617 		mmr_t	up_event        : 1;
20618 		mmr_t	up_polarity     : 1;
20619 		mmr_t	up_mode         : 1;
20620 		mmr_t	dn_stimulus     : 5;
20621 		mmr_t	dn_event        : 1;
20622 		mmr_t	dn_polarity     : 1;
20623 		mmr_t	dn_mode         : 1;
20624 		mmr_t	inc_enable      : 1;
20625 		mmr_t	dec_enable      : 1;
20626 		mmr_t	peak_det_enable : 1;
20627 		mmr_t	reserved_0      : 45;
20632 	mmr_t	sh_performance_count2_control_regval;
20634 		mmr_t	reserved_0      : 45;
20635 		mmr_t	peak_det_enable : 1;
20636 		mmr_t	dec_enable      : 1;
20637 		mmr_t	inc_enable      : 1;
20638 		mmr_t	dn_mode         : 1;
20639 		mmr_t	dn_polarity     : 1;
20640 		mmr_t	dn_event        : 1;
20641 		mmr_t	dn_stimulus     : 5;
20642 		mmr_t	up_mode         : 1;
20643 		mmr_t	up_polarity     : 1;
20644 		mmr_t	up_event        : 1;
20645 		mmr_t	up_stimulus     : 5;
20657 	mmr_t	sh_performance_count3_control_regval;
20659 		mmr_t	up_stimulus     : 5;
20660 		mmr_t	up_event        : 1;
20661 		mmr_t	up_polarity     : 1;
20662 		mmr_t	up_mode         : 1;
20663 		mmr_t	dn_stimulus     : 5;
20664 		mmr_t	dn_event        : 1;
20665 		mmr_t	dn_polarity     : 1;
20666 		mmr_t	dn_mode         : 1;
20667 		mmr_t	inc_enable      : 1;
20668 		mmr_t	dec_enable      : 1;
20669 		mmr_t	peak_det_enable : 1;
20670 		mmr_t	reserved_0      : 45;
20675 	mmr_t	sh_performance_count3_control_regval;
20677 		mmr_t	reserved_0      : 45;
20678 		mmr_t	peak_det_enable : 1;
20679 		mmr_t	dec_enable      : 1;
20680 		mmr_t	inc_enable      : 1;
20681 		mmr_t	dn_mode         : 1;
20682 		mmr_t	dn_polarity     : 1;
20683 		mmr_t	dn_event        : 1;
20684 		mmr_t	dn_stimulus     : 5;
20685 		mmr_t	up_mode         : 1;
20686 		mmr_t	up_polarity     : 1;
20687 		mmr_t	up_event        : 1;
20688 		mmr_t	up_stimulus     : 5;
20700 	mmr_t	sh_performance_count4_control_regval;
20702 		mmr_t	up_stimulus     : 5;
20703 		mmr_t	up_event        : 1;
20704 		mmr_t	up_polarity     : 1;
20705 		mmr_t	up_mode         : 1;
20706 		mmr_t	dn_stimulus     : 5;
20707 		mmr_t	dn_event        : 1;
20708 		mmr_t	dn_polarity     : 1;
20709 		mmr_t	dn_mode         : 1;
20710 		mmr_t	inc_enable      : 1;
20711 		mmr_t	dec_enable      : 1;
20712 		mmr_t	peak_det_enable : 1;
20713 		mmr_t	reserved_0      : 45;
20718 	mmr_t	sh_performance_count4_control_regval;
20720 		mmr_t	reserved_0      : 45;
20721 		mmr_t	peak_det_enable : 1;
20722 		mmr_t	dec_enable      : 1;
20723 		mmr_t	inc_enable      : 1;
20724 		mmr_t	dn_mode         : 1;
20725 		mmr_t	dn_polarity     : 1;
20726 		mmr_t	dn_event        : 1;
20727 		mmr_t	dn_stimulus     : 5;
20728 		mmr_t	up_mode         : 1;
20729 		mmr_t	up_polarity     : 1;
20730 		mmr_t	up_event        : 1;
20731 		mmr_t	up_stimulus     : 5;
20743 	mmr_t	sh_performance_count5_control_regval;
20745 		mmr_t	up_stimulus     : 5;
20746 		mmr_t	up_event        : 1;
20747 		mmr_t	up_polarity     : 1;
20748 		mmr_t	up_mode         : 1;
20749 		mmr_t	dn_stimulus     : 5;
20750 		mmr_t	dn_event        : 1;
20751 		mmr_t	dn_polarity     : 1;
20752 		mmr_t	dn_mode         : 1;
20753 		mmr_t	inc_enable      : 1;
20754 		mmr_t	dec_enable      : 1;
20755 		mmr_t	peak_det_enable : 1;
20756 		mmr_t	reserved_0      : 45;
20761 	mmr_t	sh_performance_count5_control_regval;
20763 		mmr_t	reserved_0      : 45;
20764 		mmr_t	peak_det_enable : 1;
20765 		mmr_t	dec_enable      : 1;
20766 		mmr_t	inc_enable      : 1;
20767 		mmr_t	dn_mode         : 1;
20768 		mmr_t	dn_polarity     : 1;
20769 		mmr_t	dn_event        : 1;
20770 		mmr_t	dn_stimulus     : 5;
20771 		mmr_t	up_mode         : 1;
20772 		mmr_t	up_polarity     : 1;
20773 		mmr_t	up_event        : 1;
20774 		mmr_t	up_stimulus     : 5;
20786 	mmr_t	sh_performance_count6_control_regval;
20788 		mmr_t	up_stimulus     : 5;
20789 		mmr_t	up_event        : 1;
20790 		mmr_t	up_polarity     : 1;
20791 		mmr_t	up_mode         : 1;
20792 		mmr_t	dn_stimulus     : 5;
20793 		mmr_t	dn_event        : 1;
20794 		mmr_t	dn_polarity     : 1;
20795 		mmr_t	dn_mode         : 1;
20796 		mmr_t	inc_enable      : 1;
20797 		mmr_t	dec_enable      : 1;
20798 		mmr_t	peak_det_enable : 1;
20799 		mmr_t	reserved_0      : 45;
20804 	mmr_t	sh_performance_count6_control_regval;
20806 		mmr_t	reserved_0      : 45;
20807 		mmr_t	peak_det_enable : 1;
20808 		mmr_t	dec_enable      : 1;
20809 		mmr_t	inc_enable      : 1;
20810 		mmr_t	dn_mode         : 1;
20811 		mmr_t	dn_polarity     : 1;
20812 		mmr_t	dn_event        : 1;
20813 		mmr_t	dn_stimulus     : 5;
20814 		mmr_t	up_mode         : 1;
20815 		mmr_t	up_polarity     : 1;
20816 		mmr_t	up_event        : 1;
20817 		mmr_t	up_stimulus     : 5;
20829 	mmr_t	sh_performance_count7_control_regval;
20831 		mmr_t	up_stimulus     : 5;
20832 		mmr_t	up_event        : 1;
20833 		mmr_t	up_polarity     : 1;
20834 		mmr_t	up_mode         : 1;
20835 		mmr_t	dn_stimulus     : 5;
20836 		mmr_t	dn_event        : 1;
20837 		mmr_t	dn_polarity     : 1;
20838 		mmr_t	dn_mode         : 1;
20839 		mmr_t	inc_enable      : 1;
20840 		mmr_t	dec_enable      : 1;
20841 		mmr_t	peak_det_enable : 1;
20842 		mmr_t	reserved_0      : 45;
20847 	mmr_t	sh_performance_count7_control_regval;
20849 		mmr_t	reserved_0      : 45;
20850 		mmr_t	peak_det_enable : 1;
20851 		mmr_t	dec_enable      : 1;
20852 		mmr_t	inc_enable      : 1;
20853 		mmr_t	dn_mode         : 1;
20854 		mmr_t	dn_polarity     : 1;
20855 		mmr_t	dn_event        : 1;
20856 		mmr_t	dn_stimulus     : 5;
20857 		mmr_t	up_mode         : 1;
20858 		mmr_t	up_polarity     : 1;
20859 		mmr_t	up_event        : 1;
20860 		mmr_t	up_stimulus     : 5;
20872 	mmr_t	sh_profile_dn_control_regval;
20874 		mmr_t	stimulus    : 5;
20875 		mmr_t	event       : 1;
20876 		mmr_t	polarity    : 1;
20877 		mmr_t	mode        : 1;
20878 		mmr_t	reserved_0  : 56;
20883 	mmr_t	sh_profile_dn_control_regval;
20885 		mmr_t	reserved_0  : 56;
20886 		mmr_t	mode        : 1;
20887 		mmr_t	polarity    : 1;
20888 		mmr_t	event       : 1;
20889 		mmr_t	stimulus    : 5;
20901 	mmr_t	sh_profile_peak_control_regval;
20903 		mmr_t	reserved_0  : 3;
20904 		mmr_t	stimulus    : 1;
20905 		mmr_t	reserved_1  : 1;
20906 		mmr_t	event       : 1;
20907 		mmr_t	polarity    : 1;
20908 		mmr_t	reserved_2  : 57;
20913 	mmr_t	sh_profile_peak_control_regval;
20915 		mmr_t	reserved_2  : 57;
20916 		mmr_t	polarity    : 1;
20917 		mmr_t	event       : 1;
20918 		mmr_t	reserved_1  : 1;
20919 		mmr_t	stimulus    : 1;
20920 		mmr_t	reserved_0  : 3;
20932 	mmr_t	sh_profile_range_regval;
20934 		mmr_t	range0      : 8;
20935 		mmr_t	range1      : 8;
20936 		mmr_t	range2      : 8;
20937 		mmr_t	range3      : 8;
20938 		mmr_t	range4      : 8;
20939 		mmr_t	range5      : 8;
20940 		mmr_t	range6      : 8;
20941 		mmr_t	range7      : 8;
20946 	mmr_t	sh_profile_range_regval;
20948 		mmr_t	range7      : 8;
20949 		mmr_t	range6      : 8;
20950 		mmr_t	range5      : 8;
20951 		mmr_t	range4      : 8;
20952 		mmr_t	range3      : 8;
20953 		mmr_t	range2      : 8;
20954 		mmr_t	range1      : 8;
20955 		mmr_t	range0      : 8;
20967 	mmr_t	sh_profile_up_control_regval;
20969 		mmr_t	stimulus    : 5;
20970 		mmr_t	event       : 1;
20971 		mmr_t	polarity    : 1;
20972 		mmr_t	mode        : 1;
20973 		mmr_t	reserved_0  : 56;
20978 	mmr_t	sh_profile_up_control_regval;
20980 		mmr_t	reserved_0  : 56;
20981 		mmr_t	mode        : 1;
20982 		mmr_t	polarity    : 1;
20983 		mmr_t	event       : 1;
20984 		mmr_t	stimulus    : 5;
20996 	mmr_t	sh_performance_counter0_regval;
20998 		mmr_t	count       : 32;
20999 		mmr_t	reserved_0  : 32;
21004 	mmr_t	sh_performance_counter0_regval;
21006 		mmr_t	reserved_0  : 32;
21007 		mmr_t	count       : 32;
21019 	mmr_t	sh_performance_counter1_regval;
21021 		mmr_t	count       : 32;
21022 		mmr_t	reserved_0  : 32;
21027 	mmr_t	sh_performance_counter1_regval;
21029 		mmr_t	reserved_0  : 32;
21030 		mmr_t	count       : 32;
21042 	mmr_t	sh_performance_counter2_regval;
21044 		mmr_t	count       : 32;
21045 		mmr_t	reserved_0  : 32;
21050 	mmr_t	sh_performance_counter2_regval;
21052 		mmr_t	reserved_0  : 32;
21053 		mmr_t	count       : 32;
21065 	mmr_t	sh_performance_counter3_regval;
21067 		mmr_t	count       : 32;
21068 		mmr_t	reserved_0  : 32;
21073 	mmr_t	sh_performance_counter3_regval;
21075 		mmr_t	reserved_0  : 32;
21076 		mmr_t	count       : 32;
21088 	mmr_t	sh_performance_counter4_regval;
21090 		mmr_t	count       : 32;
21091 		mmr_t	reserved_0  : 32;
21096 	mmr_t	sh_performance_counter4_regval;
21098 		mmr_t	reserved_0  : 32;
21099 		mmr_t	count       : 32;
21111 	mmr_t	sh_performance_counter5_regval;
21113 		mmr_t	count       : 32;
21114 		mmr_t	reserved_0  : 32;
21119 	mmr_t	sh_performance_counter5_regval;
21121 		mmr_t	reserved_0  : 32;
21122 		mmr_t	count       : 32;
21134 	mmr_t	sh_performance_counter6_regval;
21136 		mmr_t	count       : 32;
21137 		mmr_t	reserved_0  : 32;
21142 	mmr_t	sh_performance_counter6_regval;
21144 		mmr_t	reserved_0  : 32;
21145 		mmr_t	count       : 32;
21157 	mmr_t	sh_performance_counter7_regval;
21159 		mmr_t	count       : 32;
21160 		mmr_t	reserved_0  : 32;
21165 	mmr_t	sh_performance_counter7_regval;
21167 		mmr_t	reserved_0  : 32;
21168 		mmr_t	count       : 32;
21180 	mmr_t	sh_profile_counter_regval;
21182 		mmr_t	counter     : 8;
21183 		mmr_t	reserved_0  : 56;
21188 	mmr_t	sh_profile_counter_regval;
21190 		mmr_t	reserved_0  : 56;
21191 		mmr_t	counter     : 8;
21203 	mmr_t	sh_profile_peak_regval;
21205 		mmr_t	counter     : 8;
21206 		mmr_t	reserved_0  : 56;
21211 	mmr_t	sh_profile_peak_regval;
21213 		mmr_t	reserved_0  : 56;
21214 		mmr_t	counter     : 8;
21226 	mmr_t	sh_ptc_0_regval;
21228 		mmr_t	a           : 1;
21229 		mmr_t	reserved_0  : 1;
21230 		mmr_t	ps          : 6;
21231 		mmr_t	rid         : 24;
21232 		mmr_t	reserved_1  : 31;
21233 		mmr_t	start       : 1;
21238 	mmr_t	sh_ptc_0_regval;
21240 		mmr_t	start       : 1;
21241 		mmr_t	reserved_1  : 31;
21242 		mmr_t	rid         : 24;
21243 		mmr_t	ps          : 6;
21244 		mmr_t	reserved_0  : 1;
21245 		mmr_t	a           : 1;
21257 	mmr_t	sh_ptc_1_regval;
21259 		mmr_t	reserved_0  : 12;
21260 		mmr_t	vpn         : 49;
21261 		mmr_t	reserved_1  : 2;
21262 		mmr_t	start       : 1;
21267 	mmr_t	sh_ptc_1_regval;
21269 		mmr_t	start       : 1;
21270 		mmr_t	reserved_1  : 2;
21271 		mmr_t	vpn         : 49;
21272 		mmr_t	reserved_0  : 12;
21284 	mmr_t	sh_ptc_parms_regval;
21286 		mmr_t	ptc_to_wrap : 24;
21287 		mmr_t	ptc_to_val  : 12;
21288 		mmr_t	reserved_0  : 28;
21293 	mmr_t	sh_ptc_parms_regval;
21295 		mmr_t	reserved_0  : 28;
21296 		mmr_t	ptc_to_val  : 12;
21297 		mmr_t	ptc_to_wrap : 24;
21309 	mmr_t	sh_int_cmpa_regval;
21311 		mmr_t	real_time_cmpa : 55;
21312 		mmr_t	reserved_0     : 9;
21317 	mmr_t	sh_int_cmpa_regval;
21319 		mmr_t	reserved_0     : 9;
21320 		mmr_t	real_time_cmpa : 55;
21332 	mmr_t	sh_int_cmpb_regval;
21334 		mmr_t	real_time_cmpb : 55;
21335 		mmr_t	reserved_0     : 9;
21340 	mmr_t	sh_int_cmpb_regval;
21342 		mmr_t	reserved_0     : 9;
21343 		mmr_t	real_time_cmpb : 55;
21355 	mmr_t	sh_int_cmpc_regval;
21357 		mmr_t	real_time_cmpc : 55;
21358 		mmr_t	reserved_0     : 9;
21363 	mmr_t	sh_int_cmpc_regval;
21365 		mmr_t	reserved_0     : 9;
21366 		mmr_t	real_time_cmpc : 55;
21378 	mmr_t	sh_int_cmpd_regval;
21380 		mmr_t	real_time_cmpd : 55;
21381 		mmr_t	reserved_0     : 9;
21386 	mmr_t	sh_int_cmpd_regval;
21388 		mmr_t	reserved_0     : 9;
21389 		mmr_t	real_time_cmpd : 55;
21401 	mmr_t	sh_int_prof_regval;
21403 		mmr_t	profile_compare : 32;
21404 		mmr_t	reserved_0      : 32;
21409 	mmr_t	sh_int_prof_regval;
21411 		mmr_t	reserved_0      : 32;
21412 		mmr_t	profile_compare : 32;
21424 	mmr_t	sh_rtc_regval;
21426 		mmr_t	real_time_clock : 55;
21427 		mmr_t	reserved_0      : 9;
21432 	mmr_t	sh_rtc_regval;
21434 		mmr_t	reserved_0      : 9;
21435 		mmr_t	real_time_clock : 55;
21447 	mmr_t	sh_scratch0_regval;
21449 		mmr_t	scratch0    : 64;
21454 	mmr_t	sh_scratch0_regval;
21456 		mmr_t	scratch0    : 64;
21468 	mmr_t	sh_scratch1_regval;
21470 		mmr_t	scratch1    : 64;
21475 	mmr_t	sh_scratch1_regval;
21477 		mmr_t	scratch1    : 64;
21489 	mmr_t	sh_scratch2_regval;
21491 		mmr_t	scratch2    : 64;
21496 	mmr_t	sh_scratch2_regval;
21498 		mmr_t	scratch2    : 64;
21510 	mmr_t	sh_scratch3_regval;
21512 		mmr_t	scratch3    : 1;
21513 		mmr_t	reserved_0  : 63;
21518 	mmr_t	sh_scratch3_regval;
21520 		mmr_t	reserved_0  : 63;
21521 		mmr_t	scratch3    : 1;
21533 	mmr_t	sh_scratch4_regval;
21535 		mmr_t	scratch4    : 1;
21536 		mmr_t	reserved_0  : 63;
21541 	mmr_t	sh_scratch4_regval;
21543 		mmr_t	reserved_0  : 63;
21544 		mmr_t	scratch4    : 1;
21556 	mmr_t	sh_crb_message_control_regval;
21558 		mmr_t	system_coherence_enable           : 1;
21559 		mmr_t	local_speculative_message_enable  : 1;
21560 		mmr_t	remote_speculative_message_enable : 1;
21561 		mmr_t	message_color                     : 1;
21562 		mmr_t	message_color_enable              : 1;
21563 		mmr_t	rrb_attribute_mismatch_fsb_enable : 1;
21564 		mmr_t	wrb_attribute_mismatch_fsb_enable : 1;
21565 		mmr_t	irb_attribute_mismatch_fsb_enable : 1;
21566 		mmr_t	rrb_attribute_mismatch_xb_enable  : 1;
21567 		mmr_t	wrb_attribute_mismatch_xb_enable  : 1;
21568 		mmr_t	suppress_bogus_writes             : 1;
21569 		mmr_t	enable_ivack_consolidation        : 1;
21570 		mmr_t	reserved_0                        : 20;
21571 		mmr_t	ivack_stall_count                 : 16;
21572 		mmr_t	ivack_throttle_control            : 16;
21577 	mmr_t	sh_crb_message_control_regval;
21579 		mmr_t	ivack_throttle_control            : 16;
21580 		mmr_t	ivack_stall_count                 : 16;
21581 		mmr_t	reserved_0                        : 20;
21582 		mmr_t	enable_ivack_consolidation        : 1;
21583 		mmr_t	suppress_bogus_writes             : 1;
21584 		mmr_t	wrb_attribute_mismatch_xb_enable  : 1;
21585 		mmr_t	rrb_attribute_mismatch_xb_enable  : 1;
21586 		mmr_t	irb_attribute_mismatch_fsb_enable : 1;
21587 		mmr_t	wrb_attribute_mismatch_fsb_enable : 1;
21588 		mmr_t	rrb_attribute_mismatch_fsb_enable : 1;
21589 		mmr_t	message_color_enable              : 1;
21590 		mmr_t	message_color                     : 1;
21591 		mmr_t	remote_speculative_message_enable : 1;
21592 		mmr_t	local_speculative_message_enable  : 1;
21593 		mmr_t	system_coherence_enable           : 1;
21605 	mmr_t	sh_crb_nack_limit_regval;
21607 		mmr_t	limit       : 12;
21608 		mmr_t	pri_freq    : 4;
21609 		mmr_t	reserved_0  : 47;
21610 		mmr_t	enable      : 1;
21615 	mmr_t	sh_crb_nack_limit_regval;
21617 		mmr_t	enable      : 1;
21618 		mmr_t	reserved_0  : 47;
21619 		mmr_t	pri_freq    : 4;
21620 		mmr_t	limit       : 12;
21632 	mmr_t	sh_crb_timeout_prescale_regval;
21634 		mmr_t	scaling_factor : 32;
21635 		mmr_t	reserved_0     : 32;
21640 	mmr_t	sh_crb_timeout_prescale_regval;
21642 		mmr_t	reserved_0     : 32;
21643 		mmr_t	scaling_factor : 32;
21655 	mmr_t	sh_crb_timeout_skid_regval;
21657 		mmr_t	skid             : 6;
21658 		mmr_t	reserved_0       : 57;
21659 		mmr_t	reset_skid_count : 1;
21664 	mmr_t	sh_crb_timeout_skid_regval;
21666 		mmr_t	reset_skid_count : 1;
21667 		mmr_t	reserved_0       : 57;
21668 		mmr_t	skid             : 6;
21680 	mmr_t	sh_memory_write_status_0_regval;
21682 		mmr_t	pending_write_count : 6;
21683 		mmr_t	reserved_0          : 58;
21688 	mmr_t	sh_memory_write_status_0_regval;
21690 		mmr_t	reserved_0          : 58;
21691 		mmr_t	pending_write_count : 6;
21703 	mmr_t	sh_memory_write_status_1_regval;
21705 		mmr_t	pending_write_count : 6;
21706 		mmr_t	reserved_0          : 58;
21711 	mmr_t	sh_memory_write_status_1_regval;
21713 		mmr_t	reserved_0          : 58;
21714 		mmr_t	pending_write_count : 6;
21726 	mmr_t	sh_pio_write_status_0_regval;
21728 		mmr_t	multi_write_error   : 1;
21729 		mmr_t	write_deadlock      : 1;
21730 		mmr_t	write_error         : 1;
21731 		mmr_t	write_error_address : 47;
21732 		mmr_t	reserved_0          : 6;
21733 		mmr_t	pending_write_count : 6;
21734 		mmr_t	reserved_1          : 1;
21735 		mmr_t	writes_ok           : 1;
21740 	mmr_t	sh_pio_write_status_0_regval;
21742 		mmr_t	writes_ok           : 1;
21743 		mmr_t	reserved_1          : 1;
21744 		mmr_t	pending_write_count : 6;
21745 		mmr_t	reserved_0          : 6;
21746 		mmr_t	write_error_address : 47;
21747 		mmr_t	write_error         : 1;
21748 		mmr_t	write_deadlock      : 1;
21749 		mmr_t	multi_write_error   : 1;
21761 	mmr_t	sh_pio_write_status_1_regval;
21763 		mmr_t	multi_write_error   : 1;
21764 		mmr_t	write_deadlock      : 1;
21765 		mmr_t	write_error         : 1;
21766 		mmr_t	write_error_address : 47;
21767 		mmr_t	reserved_0          : 6;
21768 		mmr_t	pending_write_count : 6;
21769 		mmr_t	reserved_1          : 1;
21770 		mmr_t	writes_ok           : 1;
21775 	mmr_t	sh_pio_write_status_1_regval;
21777 		mmr_t	writes_ok           : 1;
21778 		mmr_t	reserved_1          : 1;
21779 		mmr_t	pending_write_count : 6;
21780 		mmr_t	reserved_0          : 6;
21781 		mmr_t	write_error_address : 47;
21782 		mmr_t	write_error         : 1;
21783 		mmr_t	write_deadlock      : 1;
21784 		mmr_t	multi_write_error   : 1;
21796 	mmr_t	sh_memory_write_status_non_user_0_regval;
21798 		mmr_t	pending_write_count : 6;
21799 		mmr_t	reserved_0          : 57;
21800 		mmr_t	clear               : 1;
21805 	mmr_t	sh_memory_write_status_non_user_0_regval;
21807 		mmr_t	clear               : 1;
21808 		mmr_t	reserved_0          : 57;
21809 		mmr_t	pending_write_count : 6;
21821 	mmr_t	sh_memory_write_status_non_user_1_regval;
21823 		mmr_t	pending_write_count : 6;
21824 		mmr_t	reserved_0          : 57;
21825 		mmr_t	clear               : 1;
21830 	mmr_t	sh_memory_write_status_non_user_1_regval;
21832 		mmr_t	clear               : 1;
21833 		mmr_t	reserved_0          : 57;
21834 		mmr_t	pending_write_count : 6;
21846 	mmr_t	sh_mmrbist_err_regval;
21848 		mmr_t	addr              : 33;
21849 		mmr_t	reserved_0        : 3;
21850 		mmr_t	detected          : 1;
21851 		mmr_t	multiple_detected : 1;
21852 		mmr_t	cancelled         : 1;
21853 		mmr_t	reserved_1        : 25;
21858 	mmr_t	sh_mmrbist_err_regval;
21860 		mmr_t	reserved_1        : 25;
21861 		mmr_t	cancelled         : 1;
21862 		mmr_t	multiple_detected : 1;
21863 		mmr_t	detected          : 1;
21864 		mmr_t	reserved_0        : 3;
21865 		mmr_t	addr              : 33;
21877 	mmr_t	sh_misc_err_hdr_lower_regval;
21879 		mmr_t	reserved_0  : 3;
21880 		mmr_t	addr        : 33;
21881 		mmr_t	cmd         : 8;
21882 		mmr_t	src         : 14;
21883 		mmr_t	reserved_1  : 2;
21884 		mmr_t	write       : 1;
21885 		mmr_t	reserved_2  : 2;
21886 		mmr_t	valid       : 1;
21891 	mmr_t	sh_misc_err_hdr_lower_regval;
21893 		mmr_t	valid       : 1;
21894 		mmr_t	reserved_2  : 2;
21895 		mmr_t	write       : 1;
21896 		mmr_t	reserved_1  : 2;
21897 		mmr_t	src         : 14;
21898 		mmr_t	cmd         : 8;
21899 		mmr_t	addr        : 33;
21900 		mmr_t	reserved_0  : 3;
21912 	mmr_t	sh_misc_err_hdr_upper_regval;
21914 		mmr_t	dir_protocol  : 1;
21915 		mmr_t	illegal_cmd   : 1;
21916 		mmr_t	nonexist_addr : 1;
21917 		mmr_t	rmw_uc        : 1;
21918 		mmr_t	rmw_cor       : 1;
21919 		mmr_t	dir_acc       : 1;
21920 		mmr_t	pi_pkt_size   : 1;
21921 		mmr_t	xn_pkt_size   : 1;
21922 		mmr_t	reserved_0    : 12;
21923 		mmr_t	echo          : 9;
21924 		mmr_t	reserved_1    : 35;
21929 	mmr_t	sh_misc_err_hdr_upper_regval;
21931 		mmr_t	reserved_1    : 35;
21932 		mmr_t	echo          : 9;
21933 		mmr_t	reserved_0    : 12;
21934 		mmr_t	xn_pkt_size   : 1;
21935 		mmr_t	pi_pkt_size   : 1;
21936 		mmr_t	dir_acc       : 1;
21937 		mmr_t	rmw_cor       : 1;
21938 		mmr_t	rmw_uc        : 1;
21939 		mmr_t	nonexist_addr : 1;
21940 		mmr_t	illegal_cmd   : 1;
21941 		mmr_t	dir_protocol  : 1;
21953 	mmr_t	sh_dir_uc_err_hdr_lower_regval;
21955 		mmr_t	reserved_0  : 3;
21956 		mmr_t	addr        : 33;
21957 		mmr_t	cmd         : 8;
21958 		mmr_t	src         : 14;
21959 		mmr_t	reserved_1  : 2;
21960 		mmr_t	write       : 1;
21961 		mmr_t	reserved_2  : 2;
21962 		mmr_t	valid       : 1;
21967 	mmr_t	sh_dir_uc_err_hdr_lower_regval;
21969 		mmr_t	valid       : 1;
21970 		mmr_t	reserved_2  : 2;
21971 		mmr_t	write       : 1;
21972 		mmr_t	reserved_1  : 2;
21973 		mmr_t	src         : 14;
21974 		mmr_t	cmd         : 8;
21975 		mmr_t	addr        : 33;
21976 		mmr_t	reserved_0  : 3;
21988 	mmr_t	sh_dir_uc_err_hdr_upper_regval;
21990 		mmr_t	reserved_0  : 3;
21991 		mmr_t	dir_uc      : 1;
21992 		mmr_t	reserved_1  : 16;
21993 		mmr_t	echo        : 9;
21994 		mmr_t	reserved_2  : 35;
21999 	mmr_t	sh_dir_uc_err_hdr_upper_regval;
22001 		mmr_t	reserved_2  : 35;
22002 		mmr_t	echo        : 9;
22003 		mmr_t	reserved_1  : 16;
22004 		mmr_t	dir_uc      : 1;
22005 		mmr_t	reserved_0  : 3;
22017 	mmr_t	sh_dir_cor_err_hdr_lower_regval;
22019 		mmr_t	reserved_0  : 3;
22020 		mmr_t	addr        : 33;
22021 		mmr_t	cmd         : 8;
22022 		mmr_t	src         : 14;
22023 		mmr_t	reserved_1  : 2;
22024 		mmr_t	write       : 1;
22025 		mmr_t	reserved_2  : 2;
22026 		mmr_t	valid       : 1;
22031 	mmr_t	sh_dir_cor_err_hdr_lower_regval;
22033 		mmr_t	valid       : 1;
22034 		mmr_t	reserved_2  : 2;
22035 		mmr_t	write       : 1;
22036 		mmr_t	reserved_1  : 2;
22037 		mmr_t	src         : 14;
22038 		mmr_t	cmd         : 8;
22039 		mmr_t	addr        : 33;
22040 		mmr_t	reserved_0  : 3;
22052 	mmr_t	sh_dir_cor_err_hdr_upper_regval;
22054 		mmr_t	reserved_0  : 8;
22055 		mmr_t	dir_cor     : 1;
22056 		mmr_t	reserved_1  : 11;
22057 		mmr_t	echo        : 9;
22058 		mmr_t	reserved_2  : 35;
22063 	mmr_t	sh_dir_cor_err_hdr_upper_regval;
22065 		mmr_t	reserved_2  : 35;
22066 		mmr_t	echo        : 9;
22067 		mmr_t	reserved_1  : 11;
22068 		mmr_t	dir_cor     : 1;
22069 		mmr_t	reserved_0  : 8;
22081 	mmr_t	sh_mem_error_summary_regval;
22083 		mmr_t	illegal_cmd           : 1;
22084 		mmr_t	nonexist_addr         : 1;
22085 		mmr_t	dqlp_dir_perr         : 1;
22086 		mmr_t	dqrp_dir_perr         : 1;
22087 		mmr_t	dqlp_dir_uc           : 1;
22088 		mmr_t	dqlp_dir_cor          : 1;
22089 		mmr_t	dqrp_dir_uc           : 1;
22090 		mmr_t	dqrp_dir_cor          : 1;
22091 		mmr_t	acx_int_hw            : 1;
22092 		mmr_t	acy_int_hw            : 1;
22093 		mmr_t	dir_acc               : 1;
22094 		mmr_t	reserved_0            : 1;
22095 		mmr_t	dqlp_int_uc           : 1;
22096 		mmr_t	dqlp_int_cor          : 1;
22097 		mmr_t	dqlp_int_hw           : 1;
22098 		mmr_t	reserved_1            : 1;
22099 		mmr_t	dqls_int_uc           : 1;
22100 		mmr_t	dqls_int_cor          : 1;
22101 		mmr_t	dqls_int_hw           : 1;
22102 		mmr_t	reserved_2            : 1;
22103 		mmr_t	dqrp_int_uc           : 1;
22104 		mmr_t	dqrp_int_cor          : 1;
22105 		mmr_t	dqrp_int_hw           : 1;
22106 		mmr_t	reserved_3            : 1;
22107 		mmr_t	dqrs_int_uc           : 1;
22108 		mmr_t	dqrs_int_cor          : 1;
22109 		mmr_t	dqrs_int_hw           : 1;
22110 		mmr_t	reserved_4            : 1;
22111 		mmr_t	pi_reply_overflow     : 1;
22112 		mmr_t	xn_reply_overflow     : 1;
22113 		mmr_t	pi_request_overflow   : 1;
22114 		mmr_t	xn_request_overflow   : 1;
22115 		mmr_t	red_black_err_timeout : 1;
22116 		mmr_t	pi_pkt_size           : 1;
22117 		mmr_t	xn_pkt_size           : 1;
22118 		mmr_t	reserved_5            : 29;
22123 	mmr_t	sh_mem_error_summary_regval;
22125 		mmr_t	reserved_5            : 29;
22126 		mmr_t	xn_pkt_size           : 1;
22127 		mmr_t	pi_pkt_size           : 1;
22128 		mmr_t	red_black_err_timeout : 1;
22129 		mmr_t	xn_request_overflow   : 1;
22130 		mmr_t	pi_request_overflow   : 1;
22131 		mmr_t	xn_reply_overflow     : 1;
22132 		mmr_t	pi_reply_overflow     : 1;
22133 		mmr_t	reserved_4            : 1;
22134 		mmr_t	dqrs_int_hw           : 1;
22135 		mmr_t	dqrs_int_cor          : 1;
22136 		mmr_t	dqrs_int_uc           : 1;
22137 		mmr_t	reserved_3            : 1;
22138 		mmr_t	dqrp_int_hw           : 1;
22139 		mmr_t	dqrp_int_cor          : 1;
22140 		mmr_t	dqrp_int_uc           : 1;
22141 		mmr_t	reserved_2            : 1;
22142 		mmr_t	dqls_int_hw           : 1;
22143 		mmr_t	dqls_int_cor          : 1;
22144 		mmr_t	dqls_int_uc           : 1;
22145 		mmr_t	reserved_1            : 1;
22146 		mmr_t	dqlp_int_hw           : 1;
22147 		mmr_t	dqlp_int_cor          : 1;
22148 		mmr_t	dqlp_int_uc           : 1;
22149 		mmr_t	reserved_0            : 1;
22150 		mmr_t	dir_acc               : 1;
22151 		mmr_t	acy_int_hw            : 1;
22152 		mmr_t	acx_int_hw            : 1;
22153 		mmr_t	dqrp_dir_cor          : 1;
22154 		mmr_t	dqrp_dir_uc           : 1;
22155 		mmr_t	dqlp_dir_cor          : 1;
22156 		mmr_t	dqlp_dir_uc           : 1;
22157 		mmr_t	dqrp_dir_perr         : 1;
22158 		mmr_t	dqlp_dir_perr         : 1;
22159 		mmr_t	nonexist_addr         : 1;
22160 		mmr_t	illegal_cmd           : 1;
22172 	mmr_t	sh_mem_error_overflow_regval;
22174 		mmr_t	illegal_cmd           : 1;
22175 		mmr_t	nonexist_addr         : 1;
22176 		mmr_t	dqlp_dir_perr         : 1;
22177 		mmr_t	dqrp_dir_perr         : 1;
22178 		mmr_t	dqlp_dir_uc           : 1;
22179 		mmr_t	dqlp_dir_cor          : 1;
22180 		mmr_t	dqrp_dir_uc           : 1;
22181 		mmr_t	dqrp_dir_cor          : 1;
22182 		mmr_t	acx_int_hw            : 1;
22183 		mmr_t	acy_int_hw            : 1;
22184 		mmr_t	dir_acc               : 1;
22185 		mmr_t	reserved_0            : 1;
22186 		mmr_t	dqlp_int_uc           : 1;
22187 		mmr_t	dqlp_int_cor          : 1;
22188 		mmr_t	dqlp_int_hw           : 1;
22189 		mmr_t	reserved_1            : 1;
22190 		mmr_t	dqls_int_uc           : 1;
22191 		mmr_t	dqls_int_cor          : 1;
22192 		mmr_t	dqls_int_hw           : 1;
22193 		mmr_t	reserved_2            : 1;
22194 		mmr_t	dqrp_int_uc           : 1;
22195 		mmr_t	dqrp_int_cor          : 1;
22196 		mmr_t	dqrp_int_hw           : 1;
22197 		mmr_t	reserved_3            : 1;
22198 		mmr_t	dqrs_int_uc           : 1;
22199 		mmr_t	dqrs_int_cor          : 1;
22200 		mmr_t	dqrs_int_hw           : 1;
22201 		mmr_t	reserved_4            : 1;
22202 		mmr_t	pi_reply_overflow     : 1;
22203 		mmr_t	xn_reply_overflow     : 1;
22204 		mmr_t	pi_request_overflow   : 1;
22205 		mmr_t	xn_request_overflow   : 1;
22206 		mmr_t	red_black_err_timeout : 1;
22207 		mmr_t	pi_pkt_size           : 1;
22208 		mmr_t	xn_pkt_size           : 1;
22209 		mmr_t	reserved_5            : 29;
22214 	mmr_t	sh_mem_error_overflow_regval;
22216 		mmr_t	reserved_5            : 29;
22217 		mmr_t	xn_pkt_size           : 1;
22218 		mmr_t	pi_pkt_size           : 1;
22219 		mmr_t	red_black_err_timeout : 1;
22220 		mmr_t	xn_request_overflow   : 1;
22221 		mmr_t	pi_request_overflow   : 1;
22222 		mmr_t	xn_reply_overflow     : 1;
22223 		mmr_t	pi_reply_overflow     : 1;
22224 		mmr_t	reserved_4            : 1;
22225 		mmr_t	dqrs_int_hw           : 1;
22226 		mmr_t	dqrs_int_cor          : 1;
22227 		mmr_t	dqrs_int_uc           : 1;
22228 		mmr_t	reserved_3            : 1;
22229 		mmr_t	dqrp_int_hw           : 1;
22230 		mmr_t	dqrp_int_cor          : 1;
22231 		mmr_t	dqrp_int_uc           : 1;
22232 		mmr_t	reserved_2            : 1;
22233 		mmr_t	dqls_int_hw           : 1;
22234 		mmr_t	dqls_int_cor          : 1;
22235 		mmr_t	dqls_int_uc           : 1;
22236 		mmr_t	reserved_1            : 1;
22237 		mmr_t	dqlp_int_hw           : 1;
22238 		mmr_t	dqlp_int_cor          : 1;
22239 		mmr_t	dqlp_int_uc           : 1;
22240 		mmr_t	reserved_0            : 1;
22241 		mmr_t	dir_acc               : 1;
22242 		mmr_t	acy_int_hw            : 1;
22243 		mmr_t	acx_int_hw            : 1;
22244 		mmr_t	dqrp_dir_cor          : 1;
22245 		mmr_t	dqrp_dir_uc           : 1;
22246 		mmr_t	dqlp_dir_cor          : 1;
22247 		mmr_t	dqlp_dir_uc           : 1;
22248 		mmr_t	dqrp_dir_perr         : 1;
22249 		mmr_t	dqlp_dir_perr         : 1;
22250 		mmr_t	nonexist_addr         : 1;
22251 		mmr_t	illegal_cmd           : 1;
22263 	mmr_t	sh_mem_error_mask_regval;
22265 		mmr_t	illegal_cmd           : 1;
22266 		mmr_t	nonexist_addr         : 1;
22267 		mmr_t	dqlp_dir_perr         : 1;
22268 		mmr_t	dqrp_dir_perr         : 1;
22269 		mmr_t	dqlp_dir_uc           : 1;
22270 		mmr_t	dqlp_dir_cor          : 1;
22271 		mmr_t	dqrp_dir_uc           : 1;
22272 		mmr_t	dqrp_dir_cor          : 1;
22273 		mmr_t	acx_int_hw            : 1;
22274 		mmr_t	acy_int_hw            : 1;
22275 		mmr_t	dir_acc               : 1;
22276 		mmr_t	reserved_0            : 1;
22277 		mmr_t	dqlp_int_uc           : 1;
22278 		mmr_t	dqlp_int_cor          : 1;
22279 		mmr_t	dqlp_int_hw           : 1;
22280 		mmr_t	reserved_1            : 1;
22281 		mmr_t	dqls_int_uc           : 1;
22282 		mmr_t	dqls_int_cor          : 1;
22283 		mmr_t	dqls_int_hw           : 1;
22284 		mmr_t	reserved_2            : 1;
22285 		mmr_t	dqrp_int_uc           : 1;
22286 		mmr_t	dqrp_int_cor          : 1;
22287 		mmr_t	dqrp_int_hw           : 1;
22288 		mmr_t	reserved_3            : 1;
22289 		mmr_t	dqrs_int_uc           : 1;
22290 		mmr_t	dqrs_int_cor          : 1;
22291 		mmr_t	dqrs_int_hw           : 1;
22292 		mmr_t	reserved_4            : 1;
22293 		mmr_t	pi_reply_overflow     : 1;
22294 		mmr_t	xn_reply_overflow     : 1;
22295 		mmr_t	pi_request_overflow   : 1;
22296 		mmr_t	xn_request_overflow   : 1;
22297 		mmr_t	red_black_err_timeout : 1;
22298 		mmr_t	pi_pkt_size           : 1;
22299 		mmr_t	xn_pkt_size           : 1;
22300 		mmr_t	reserved_5            : 29;
22305 	mmr_t	sh_mem_error_mask_regval;
22307 		mmr_t	reserved_5            : 29;
22308 		mmr_t	xn_pkt_size           : 1;
22309 		mmr_t	pi_pkt_size           : 1;
22310 		mmr_t	red_black_err_timeout : 1;
22311 		mmr_t	xn_request_overflow   : 1;
22312 		mmr_t	pi_request_overflow   : 1;
22313 		mmr_t	xn_reply_overflow     : 1;
22314 		mmr_t	pi_reply_overflow     : 1;
22315 		mmr_t	reserved_4            : 1;
22316 		mmr_t	dqrs_int_hw           : 1;
22317 		mmr_t	dqrs_int_cor          : 1;
22318 		mmr_t	dqrs_int_uc           : 1;
22319 		mmr_t	reserved_3            : 1;
22320 		mmr_t	dqrp_int_hw           : 1;
22321 		mmr_t	dqrp_int_cor          : 1;
22322 		mmr_t	dqrp_int_uc           : 1;
22323 		mmr_t	reserved_2            : 1;
22324 		mmr_t	dqls_int_hw           : 1;
22325 		mmr_t	dqls_int_cor          : 1;
22326 		mmr_t	dqls_int_uc           : 1;
22327 		mmr_t	reserved_1            : 1;
22328 		mmr_t	dqlp_int_hw           : 1;
22329 		mmr_t	dqlp_int_cor          : 1;
22330 		mmr_t	dqlp_int_uc           : 1;
22331 		mmr_t	reserved_0            : 1;
22332 		mmr_t	dir_acc               : 1;
22333 		mmr_t	acy_int_hw            : 1;
22334 		mmr_t	acx_int_hw            : 1;
22335 		mmr_t	dqrp_dir_cor          : 1;
22336 		mmr_t	dqrp_dir_uc           : 1;
22337 		mmr_t	dqlp_dir_cor          : 1;
22338 		mmr_t	dqlp_dir_uc           : 1;
22339 		mmr_t	dqrp_dir_perr         : 1;
22340 		mmr_t	dqlp_dir_perr         : 1;
22341 		mmr_t	nonexist_addr         : 1;
22342 		mmr_t	illegal_cmd           : 1;
22354 	mmr_t	sh_x_dimm_cfg_regval;
22356 		mmr_t	dimm0_size  : 3;
22357 		mmr_t	dimm0_2bk   : 1;
22358 		mmr_t	dimm0_rev   : 1;
22359 		mmr_t	dimm0_cs    : 2;
22360 		mmr_t	reserved_0  : 1;
22361 		mmr_t	dimm1_size  : 3;
22362 		mmr_t	dimm1_2bk   : 1;
22363 		mmr_t	dimm1_rev   : 1;
22364 		mmr_t	dimm1_cs    : 2;
22365 		mmr_t	reserved_1  : 1;
22366 		mmr_t	dimm2_size  : 3;
22367 		mmr_t	dimm2_2bk   : 1;
22368 		mmr_t	dimm2_rev   : 1;
22369 		mmr_t	dimm2_cs    : 2;
22370 		mmr_t	reserved_2  : 1;
22371 		mmr_t	dimm3_size  : 3;
22372 		mmr_t	dimm3_2bk   : 1;
22373 		mmr_t	dimm3_rev   : 1;
22374 		mmr_t	dimm3_cs    : 2;
22375 		mmr_t	reserved_3  : 1;
22376 		mmr_t	freq        : 4;
22377 		mmr_t	reserved_4  : 28;
22382 	mmr_t	sh_x_dimm_cfg_regval;
22384 		mmr_t	reserved_4  : 28;
22385 		mmr_t	freq        : 4;
22386 		mmr_t	reserved_3  : 1;
22387 		mmr_t	dimm3_cs    : 2;
22388 		mmr_t	dimm3_rev   : 1;
22389 		mmr_t	dimm3_2bk   : 1;
22390 		mmr_t	dimm3_size  : 3;
22391 		mmr_t	reserved_2  : 1;
22392 		mmr_t	dimm2_cs    : 2;
22393 		mmr_t	dimm2_rev   : 1;
22394 		mmr_t	dimm2_2bk   : 1;
22395 		mmr_t	dimm2_size  : 3;
22396 		mmr_t	reserved_1  : 1;
22397 		mmr_t	dimm1_cs    : 2;
22398 		mmr_t	dimm1_rev   : 1;
22399 		mmr_t	dimm1_2bk   : 1;
22400 		mmr_t	dimm1_size  : 3;
22401 		mmr_t	reserved_0  : 1;
22402 		mmr_t	dimm0_cs    : 2;
22403 		mmr_t	dimm0_rev   : 1;
22404 		mmr_t	dimm0_2bk   : 1;
22405 		mmr_t	dimm0_size  : 3;
22417 	mmr_t	sh_y_dimm_cfg_regval;
22419 		mmr_t	dimm0_size  : 3;
22420 		mmr_t	dimm0_2bk   : 1;
22421 		mmr_t	dimm0_rev   : 1;
22422 		mmr_t	dimm0_cs    : 2;
22423 		mmr_t	reserved_0  : 1;
22424 		mmr_t	dimm1_size  : 3;
22425 		mmr_t	dimm1_2bk   : 1;
22426 		mmr_t	dimm1_rev   : 1;
22427 		mmr_t	dimm1_cs    : 2;
22428 		mmr_t	reserved_1  : 1;
22429 		mmr_t	dimm2_size  : 3;
22430 		mmr_t	dimm2_2bk   : 1;
22431 		mmr_t	dimm2_rev   : 1;
22432 		mmr_t	dimm2_cs    : 2;
22433 		mmr_t	reserved_2  : 1;
22434 		mmr_t	dimm3_size  : 3;
22435 		mmr_t	dimm3_2bk   : 1;
22436 		mmr_t	dimm3_rev   : 1;
22437 		mmr_t	dimm3_cs    : 2;
22438 		mmr_t	reserved_3  : 1;
22439 		mmr_t	freq        : 4;
22440 		mmr_t	reserved_4  : 28;
22445 	mmr_t	sh_y_dimm_cfg_regval;
22447 		mmr_t	reserved_4  : 28;
22448 		mmr_t	freq        : 4;
22449 		mmr_t	reserved_3  : 1;
22450 		mmr_t	dimm3_cs    : 2;
22451 		mmr_t	dimm3_rev   : 1;
22452 		mmr_t	dimm3_2bk   : 1;
22453 		mmr_t	dimm3_size  : 3;
22454 		mmr_t	reserved_2  : 1;
22455 		mmr_t	dimm2_cs    : 2;
22456 		mmr_t	dimm2_rev   : 1;
22457 		mmr_t	dimm2_2bk   : 1;
22458 		mmr_t	dimm2_size  : 3;
22459 		mmr_t	reserved_1  : 1;
22460 		mmr_t	dimm1_cs    : 2;
22461 		mmr_t	dimm1_rev   : 1;
22462 		mmr_t	dimm1_2bk   : 1;
22463 		mmr_t	dimm1_size  : 3;
22464 		mmr_t	reserved_0  : 1;
22465 		mmr_t	dimm0_cs    : 2;
22466 		mmr_t	dimm0_rev   : 1;
22467 		mmr_t	dimm0_2bk   : 1;
22468 		mmr_t	dimm0_size  : 3;
22480 	mmr_t	sh_jnr_dimm_cfg_regval;
22482 		mmr_t	dimm0_size  : 3;
22483 		mmr_t	dimm0_2bk   : 1;
22484 		mmr_t	dimm0_rev   : 1;
22485 		mmr_t	dimm0_cs    : 2;
22486 		mmr_t	reserved_0  : 1;
22487 		mmr_t	dimm1_size  : 3;
22488 		mmr_t	dimm1_2bk   : 1;
22489 		mmr_t	dimm1_rev   : 1;
22490 		mmr_t	dimm1_cs    : 2;
22491 		mmr_t	reserved_1  : 1;
22492 		mmr_t	dimm2_size  : 3;
22493 		mmr_t	dimm2_2bk   : 1;
22494 		mmr_t	dimm2_rev   : 1;
22495 		mmr_t	dimm2_cs    : 2;
22496 		mmr_t	reserved_2  : 1;
22497 		mmr_t	dimm3_size  : 3;
22498 		mmr_t	dimm3_2bk   : 1;
22499 		mmr_t	dimm3_rev   : 1;
22500 		mmr_t	dimm3_cs    : 2;
22501 		mmr_t	reserved_3  : 1;
22502 		mmr_t	freq        : 4;
22503 		mmr_t	reserved_4  : 28;
22508 	mmr_t	sh_jnr_dimm_cfg_regval;
22510 		mmr_t	reserved_4  : 28;
22511 		mmr_t	freq        : 4;
22512 		mmr_t	reserved_3  : 1;
22513 		mmr_t	dimm3_cs    : 2;
22514 		mmr_t	dimm3_rev   : 1;
22515 		mmr_t	dimm3_2bk   : 1;
22516 		mmr_t	dimm3_size  : 3;
22517 		mmr_t	reserved_2  : 1;
22518 		mmr_t	dimm2_cs    : 2;
22519 		mmr_t	dimm2_rev   : 1;
22520 		mmr_t	dimm2_2bk   : 1;
22521 		mmr_t	dimm2_size  : 3;
22522 		mmr_t	reserved_1  : 1;
22523 		mmr_t	dimm1_cs    : 2;
22524 		mmr_t	dimm1_rev   : 1;
22525 		mmr_t	dimm1_2bk   : 1;
22526 		mmr_t	dimm1_size  : 3;
22527 		mmr_t	reserved_0  : 1;
22528 		mmr_t	dimm0_cs    : 2;
22529 		mmr_t	dimm0_rev   : 1;
22530 		mmr_t	dimm0_2bk   : 1;
22531 		mmr_t	dimm0_size  : 3;
22543 	mmr_t	sh_x_phase_cfg_regval;
22545 		mmr_t	ld_a        : 5;
22546 		mmr_t	ld_b        : 5;
22547 		mmr_t	dq_ld_a     : 5;
22548 		mmr_t	dq_ld_b     : 5;
22549 		mmr_t	hold        : 5;
22550 		mmr_t	hold_req    : 5;
22551 		mmr_t	add_cp      : 5;
22552 		mmr_t	bubble_en   : 5;
22553 		mmr_t	pha_bubble  : 3;
22554 		mmr_t	phb_bubble  : 3;
22555 		mmr_t	phc_bubble  : 3;
22556 		mmr_t	phd_bubble  : 3;
22557 		mmr_t	phe_bubble  : 3;
22558 		mmr_t	sel_a       : 4;
22559 		mmr_t	dq_sel_a    : 4;
22560 		mmr_t	reserved_0  : 1;
22565 	mmr_t	sh_x_phase_cfg_regval;
22567 		mmr_t	reserved_0  : 1;
22568 		mmr_t	dq_sel_a    : 4;
22569 		mmr_t	sel_a       : 4;
22570 		mmr_t	phe_bubble  : 3;
22571 		mmr_t	phd_bubble  : 3;
22572 		mmr_t	phc_bubble  : 3;
22573 		mmr_t	phb_bubble  : 3;
22574 		mmr_t	pha_bubble  : 3;
22575 		mmr_t	bubble_en   : 5;
22576 		mmr_t	add_cp      : 5;
22577 		mmr_t	hold_req    : 5;
22578 		mmr_t	hold        : 5;
22579 		mmr_t	dq_ld_b     : 5;
22580 		mmr_t	dq_ld_a     : 5;
22581 		mmr_t	ld_b        : 5;
22582 		mmr_t	ld_a        : 5;
22594 	mmr_t	sh_x_cfg_regval;
22596 		mmr_t	mode_serial             : 1;
22597 		mmr_t	dirc_random_replacement : 1;
22598 		mmr_t	dir_counter_init        : 6;
22599 		mmr_t	ta_dlys                 : 32;
22600 		mmr_t	da_bb_clr               : 4;
22601 		mmr_t	dc_bb_clr               : 4;
22602 		mmr_t	wt_bb_clr               : 4;
22603 		mmr_t	sso_wt_en               : 1;
22604 		mmr_t	trcd2_en                : 1;
22605 		mmr_t	trcd4_en                : 1;
22606 		mmr_t	req_cntr_dis            : 1;
22607 		mmr_t	req_cntr_val            : 6;
22608 		mmr_t	inv_cas_addr            : 1;
22609 		mmr_t	clr_dir_cache           : 1;
22614 	mmr_t	sh_x_cfg_regval;
22616 		mmr_t	clr_dir_cache           : 1;
22617 		mmr_t	inv_cas_addr            : 1;
22618 		mmr_t	req_cntr_val            : 6;
22619 		mmr_t	req_cntr_dis            : 1;
22620 		mmr_t	trcd4_en                : 1;
22621 		mmr_t	trcd2_en                : 1;
22622 		mmr_t	sso_wt_en               : 1;
22623 		mmr_t	wt_bb_clr               : 4;
22624 		mmr_t	dc_bb_clr               : 4;
22625 		mmr_t	da_bb_clr               : 4;
22626 		mmr_t	ta_dlys                 : 32;
22627 		mmr_t	dir_counter_init        : 6;
22628 		mmr_t	dirc_random_replacement : 1;
22629 		mmr_t	mode_serial             : 1;
22641 	mmr_t	sh_x_dqct_cfg_regval;
22643 		mmr_t	rd_sel      : 4;
22644 		mmr_t	wt_sel      : 4;
22645 		mmr_t	dta_rd_sel  : 4;
22646 		mmr_t	dta_wt_sel  : 4;
22647 		mmr_t	dir_rd_sel  : 4;
22648 		mmr_t	mdir_rd_sel : 4;
22649 		mmr_t	reserved_0  : 40;
22654 	mmr_t	sh_x_dqct_cfg_regval;
22656 		mmr_t	reserved_0  : 40;
22657 		mmr_t	mdir_rd_sel : 4;
22658 		mmr_t	dir_rd_sel  : 4;
22659 		mmr_t	dta_wt_sel  : 4;
22660 		mmr_t	dta_rd_sel  : 4;
22661 		mmr_t	wt_sel      : 4;
22662 		mmr_t	rd_sel      : 4;
22674 	mmr_t	sh_x_refresh_control_regval;
22676 		mmr_t	enable      : 8;
22677 		mmr_t	interval    : 9;
22678 		mmr_t	hold        : 6;
22679 		mmr_t	interleave  : 1;
22680 		mmr_t	half_rate   : 4;
22681 		mmr_t	reserved_0  : 36;
22686 	mmr_t	sh_x_refresh_control_regval;
22688 		mmr_t	reserved_0  : 36;
22689 		mmr_t	half_rate   : 4;
22690 		mmr_t	interleave  : 1;
22691 		mmr_t	hold        : 6;
22692 		mmr_t	interval    : 9;
22693 		mmr_t	enable      : 8;
22705 	mmr_t	sh_y_phase_cfg_regval;
22707 		mmr_t	ld_a        : 5;
22708 		mmr_t	ld_b        : 5;
22709 		mmr_t	dq_ld_a     : 5;
22710 		mmr_t	dq_ld_b     : 5;
22711 		mmr_t	hold        : 5;
22712 		mmr_t	hold_req    : 5;
22713 		mmr_t	add_cp      : 5;
22714 		mmr_t	bubble_en   : 5;
22715 		mmr_t	pha_bubble  : 3;
22716 		mmr_t	phb_bubble  : 3;
22717 		mmr_t	phc_bubble  : 3;
22718 		mmr_t	phd_bubble  : 3;
22719 		mmr_t	phe_bubble  : 3;
22720 		mmr_t	sel_a       : 4;
22721 		mmr_t	dq_sel_a    : 4;
22722 		mmr_t	reserved_0  : 1;
22727 	mmr_t	sh_y_phase_cfg_regval;
22729 		mmr_t	reserved_0  : 1;
22730 		mmr_t	dq_sel_a    : 4;
22731 		mmr_t	sel_a       : 4;
22732 		mmr_t	phe_bubble  : 3;
22733 		mmr_t	phd_bubble  : 3;
22734 		mmr_t	phc_bubble  : 3;
22735 		mmr_t	phb_bubble  : 3;
22736 		mmr_t	pha_bubble  : 3;
22737 		mmr_t	bubble_en   : 5;
22738 		mmr_t	add_cp      : 5;
22739 		mmr_t	hold_req    : 5;
22740 		mmr_t	hold        : 5;
22741 		mmr_t	dq_ld_b     : 5;
22742 		mmr_t	dq_ld_a     : 5;
22743 		mmr_t	ld_b        : 5;
22744 		mmr_t	ld_a        : 5;
22756 	mmr_t	sh_y_cfg_regval;
22758 		mmr_t	mode_serial             : 1;
22759 		mmr_t	dirc_random_replacement : 1;
22760 		mmr_t	dir_counter_init        : 6;
22761 		mmr_t	ta_dlys                 : 32;
22762 		mmr_t	da_bb_clr               : 4;
22763 		mmr_t	dc_bb_clr               : 4;
22764 		mmr_t	wt_bb_clr               : 4;
22765 		mmr_t	sso_wt_en               : 1;
22766 		mmr_t	trcd2_en                : 1;
22767 		mmr_t	trcd4_en                : 1;
22768 		mmr_t	req_cntr_dis            : 1;
22769 		mmr_t	req_cntr_val            : 6;
22770 		mmr_t	inv_cas_addr            : 1;
22771 		mmr_t	clr_dir_cache           : 1;
22776 	mmr_t	sh_y_cfg_regval;
22778 		mmr_t	clr_dir_cache           : 1;
22779 		mmr_t	inv_cas_addr            : 1;
22780 		mmr_t	req_cntr_val            : 6;
22781 		mmr_t	req_cntr_dis            : 1;
22782 		mmr_t	trcd4_en                : 1;
22783 		mmr_t	trcd2_en                : 1;
22784 		mmr_t	sso_wt_en               : 1;
22785 		mmr_t	wt_bb_clr               : 4;
22786 		mmr_t	dc_bb_clr               : 4;
22787 		mmr_t	da_bb_clr               : 4;
22788 		mmr_t	ta_dlys                 : 32;
22789 		mmr_t	dir_counter_init        : 6;
22790 		mmr_t	dirc_random_replacement : 1;
22791 		mmr_t	mode_serial             : 1;
22803 	mmr_t	sh_y_dqct_cfg_regval;
22805 		mmr_t	rd_sel      : 4;
22806 		mmr_t	wt_sel      : 4;
22807 		mmr_t	dta_rd_sel  : 4;
22808 		mmr_t	dta_wt_sel  : 4;
22809 		mmr_t	dir_rd_sel  : 4;
22810 		mmr_t	mdir_rd_sel : 4;
22811 		mmr_t	reserved_0  : 40;
22816 	mmr_t	sh_y_dqct_cfg_regval;
22818 		mmr_t	reserved_0  : 40;
22819 		mmr_t	mdir_rd_sel : 4;
22820 		mmr_t	dir_rd_sel  : 4;
22821 		mmr_t	dta_wt_sel  : 4;
22822 		mmr_t	dta_rd_sel  : 4;
22823 		mmr_t	wt_sel      : 4;
22824 		mmr_t	rd_sel      : 4;
22836 	mmr_t	sh_y_refresh_control_regval;
22838 		mmr_t	enable      : 8;
22839 		mmr_t	interval    : 9;
22840 		mmr_t	hold        : 6;
22841 		mmr_t	interleave  : 1;
22842 		mmr_t	half_rate   : 4;
22843 		mmr_t	reserved_0  : 36;
22848 	mmr_t	sh_y_refresh_control_regval;
22850 		mmr_t	reserved_0  : 36;
22851 		mmr_t	half_rate   : 4;
22852 		mmr_t	interleave  : 1;
22853 		mmr_t	hold        : 6;
22854 		mmr_t	interval    : 9;
22855 		mmr_t	enable      : 8;
22867 	mmr_t	sh_mem_red_black_regval;
22869 		mmr_t	time        : 16;
22870 		mmr_t	err_time    : 36;
22871 		mmr_t	reserved_0  : 12;
22876 	mmr_t	sh_mem_red_black_regval;
22878 		mmr_t	reserved_0  : 12;
22879 		mmr_t	err_time    : 36;
22880 		mmr_t	time        : 16;
22891 	mmr_t	sh_misc_mem_cfg_regval;
22893 		mmr_t	express_header_enable       : 1;
22894 		mmr_t	spec_header_enable          : 1;
22895 		mmr_t	jnr_bypass_enable           : 1;
22896 		mmr_t	xn_rd_same_as_pi            : 1;
22897 		mmr_t	low_write_buffer_threshold  : 6;
22898 		mmr_t	reserved_0                  : 2;
22899 		mmr_t	low_victim_buffer_threshold : 6;
22900 		mmr_t	reserved_1                  : 2;
22901 		mmr_t	throttle_cnt                : 8;
22902 		mmr_t	disabled_read_tnums         : 5;
22903 		mmr_t	reserved_2                  : 3;
22904 		mmr_t	disabled_write_tnums        : 5;
22905 		mmr_t	reserved_3                  : 3;
22906 		mmr_t	disabled_victims            : 6;
22907 		mmr_t	reserved_4                  : 2;
22908 		mmr_t	alternate_xn_rp_plane       : 1;
22909 		mmr_t	reserved_5                  : 11;
22914 	mmr_t	sh_misc_mem_cfg_regval;
22916 		mmr_t	reserved_5                  : 11;
22917 		mmr_t	alternate_xn_rp_plane       : 1;
22918 		mmr_t	reserved_4                  : 2;
22919 		mmr_t	disabled_victims            : 6;
22920 		mmr_t	reserved_3                  : 3;
22921 		mmr_t	disabled_write_tnums        : 5;
22922 		mmr_t	reserved_2                  : 3;
22923 		mmr_t	disabled_read_tnums         : 5;
22924 		mmr_t	throttle_cnt                : 8;
22925 		mmr_t	reserved_1                  : 2;
22926 		mmr_t	low_victim_buffer_threshold : 6;
22927 		mmr_t	reserved_0                  : 2;
22928 		mmr_t	low_write_buffer_threshold  : 6;
22929 		mmr_t	xn_rd_same_as_pi            : 1;
22930 		mmr_t	jnr_bypass_enable           : 1;
22931 		mmr_t	spec_header_enable          : 1;
22932 		mmr_t	express_header_enable       : 1;
22944 	mmr_t	sh_pio_rq_crd_ctl_regval;
22946 		mmr_t	depth       : 6;
22947 		mmr_t	reserved_0  : 58;
22952 	mmr_t	sh_pio_rq_crd_ctl_regval;
22954 		mmr_t	reserved_0  : 58;
22955 		mmr_t	depth       : 6;
22967 	mmr_t	sh_pi_md_rq_crd_ctl_regval;
22969 		mmr_t	depth       : 6;
22970 		mmr_t	reserved_0  : 58;
22975 	mmr_t	sh_pi_md_rq_crd_ctl_regval;
22977 		mmr_t	reserved_0  : 58;
22978 		mmr_t	depth       : 6;
22990 	mmr_t	sh_pi_md_rp_crd_ctl_regval;
22992 		mmr_t	depth       : 6;
22993 		mmr_t	reserved_0  : 58;
22998 	mmr_t	sh_pi_md_rp_crd_ctl_regval;
23000 		mmr_t	reserved_0  : 58;
23001 		mmr_t	depth       : 6;
23013 	mmr_t	sh_xn_md_rq_crd_ctl_regval;
23015 		mmr_t	depth       : 6;
23016 		mmr_t	reserved_0  : 58;
23021 	mmr_t	sh_xn_md_rq_crd_ctl_regval;
23023 		mmr_t	reserved_0  : 58;
23024 		mmr_t	depth       : 6;
23036 	mmr_t	sh_xn_md_rp_crd_ctl_regval;
23038 		mmr_t	depth       : 6;
23039 		mmr_t	reserved_0  : 58;
23044 	mmr_t	sh_xn_md_rp_crd_ctl_regval;
23046 		mmr_t	reserved_0  : 58;
23047 		mmr_t	depth       : 6;
23059 	mmr_t	sh_x_tag0_regval;
23061 		mmr_t	tag         : 20;
23062 		mmr_t	reserved_0  : 44;
23067 	mmr_t	sh_x_tag0_regval;
23069 		mmr_t	reserved_0  : 44;
23070 		mmr_t	tag         : 20;
23082 	mmr_t	sh_x_tag1_regval;
23084 		mmr_t	tag         : 20;
23085 		mmr_t	reserved_0  : 44;
23090 	mmr_t	sh_x_tag1_regval;
23092 		mmr_t	reserved_0  : 44;
23093 		mmr_t	tag         : 20;
23105 	mmr_t	sh_x_tag2_regval;
23107 		mmr_t	tag         : 20;
23108 		mmr_t	reserved_0  : 44;
23113 	mmr_t	sh_x_tag2_regval;
23115 		mmr_t	reserved_0  : 44;
23116 		mmr_t	tag         : 20;
23128 	mmr_t	sh_x_tag3_regval;
23130 		mmr_t	tag         : 20;
23131 		mmr_t	reserved_0  : 44;
23136 	mmr_t	sh_x_tag3_regval;
23138 		mmr_t	reserved_0  : 44;
23139 		mmr_t	tag         : 20;
23151 	mmr_t	sh_x_tag4_regval;
23153 		mmr_t	tag         : 20;
23154 		mmr_t	reserved_0  : 44;
23159 	mmr_t	sh_x_tag4_regval;
23161 		mmr_t	reserved_0  : 44;
23162 		mmr_t	tag         : 20;
23174 	mmr_t	sh_x_tag5_regval;
23176 		mmr_t	tag         : 20;
23177 		mmr_t	reserved_0  : 44;
23182 	mmr_t	sh_x_tag5_regval;
23184 		mmr_t	reserved_0  : 44;
23185 		mmr_t	tag         : 20;
23197 	mmr_t	sh_x_tag6_regval;
23199 		mmr_t	tag         : 20;
23200 		mmr_t	reserved_0  : 44;
23205 	mmr_t	sh_x_tag6_regval;
23207 		mmr_t	reserved_0  : 44;
23208 		mmr_t	tag         : 20;
23220 	mmr_t	sh_x_tag7_regval;
23222 		mmr_t	tag         : 20;
23223 		mmr_t	reserved_0  : 44;
23228 	mmr_t	sh_x_tag7_regval;
23230 		mmr_t	reserved_0  : 44;
23231 		mmr_t	tag         : 20;
23243 	mmr_t	sh_y_tag0_regval;
23245 		mmr_t	tag         : 20;
23246 		mmr_t	reserved_0  : 44;
23251 	mmr_t	sh_y_tag0_regval;
23253 		mmr_t	reserved_0  : 44;
23254 		mmr_t	tag         : 20;
23266 	mmr_t	sh_y_tag1_regval;
23268 		mmr_t	tag         : 20;
23269 		mmr_t	reserved_0  : 44;
23274 	mmr_t	sh_y_tag1_regval;
23276 		mmr_t	reserved_0  : 44;
23277 		mmr_t	tag         : 20;
23289 	mmr_t	sh_y_tag2_regval;
23291 		mmr_t	tag         : 20;
23292 		mmr_t	reserved_0  : 44;
23297 	mmr_t	sh_y_tag2_regval;
23299 		mmr_t	reserved_0  : 44;
23300 		mmr_t	tag         : 20;
23312 	mmr_t	sh_y_tag3_regval;
23314 		mmr_t	tag         : 20;
23315 		mmr_t	reserved_0  : 44;
23320 	mmr_t	sh_y_tag3_regval;
23322 		mmr_t	reserved_0  : 44;
23323 		mmr_t	tag         : 20;
23335 	mmr_t	sh_y_tag4_regval;
23337 		mmr_t	tag         : 20;
23338 		mmr_t	reserved_0  : 44;
23343 	mmr_t	sh_y_tag4_regval;
23345 		mmr_t	reserved_0  : 44;
23346 		mmr_t	tag         : 20;
23358 	mmr_t	sh_y_tag5_regval;
23360 		mmr_t	tag         : 20;
23361 		mmr_t	reserved_0  : 44;
23366 	mmr_t	sh_y_tag5_regval;
23368 		mmr_t	reserved_0  : 44;
23369 		mmr_t	tag         : 20;
23381 	mmr_t	sh_y_tag6_regval;
23383 		mmr_t	tag         : 20;
23384 		mmr_t	reserved_0  : 44;
23389 	mmr_t	sh_y_tag6_regval;
23391 		mmr_t	reserved_0  : 44;
23392 		mmr_t	tag         : 20;
23404 	mmr_t	sh_y_tag7_regval;
23406 		mmr_t	tag         : 20;
23407 		mmr_t	reserved_0  : 44;
23412 	mmr_t	sh_y_tag7_regval;
23414 		mmr_t	reserved_0  : 44;
23415 		mmr_t	tag         : 20;
23427 	mmr_t	sh_mmrbist_base_regval;
23429 		mmr_t	reserved_0  : 3;
23430 		mmr_t	dword_addr  : 47;
23431 		mmr_t	reserved_1  : 14;
23436 	mmr_t	sh_mmrbist_base_regval;
23438 		mmr_t	reserved_1  : 14;
23439 		mmr_t	dword_addr  : 47;
23440 		mmr_t	reserved_0  : 3;
23452 	mmr_t	sh_mmrbist_ctl_regval;
23454 		mmr_t	block_length : 31;
23455 		mmr_t	reserved_0   : 1;
23456 		mmr_t	cmd          : 7;
23457 		mmr_t	reserved_1   : 1;
23458 		mmr_t	in_progress  : 1;
23459 		mmr_t	fail         : 1;
23460 		mmr_t	mem_idle     : 1;
23461 		mmr_t	reserved_2   : 1;
23462 		mmr_t	reset_state  : 1;
23463 		mmr_t	reserved_3   : 19;
23468 	mmr_t	sh_mmrbist_ctl_regval;
23470 		mmr_t	reserved_3   : 19;
23471 		mmr_t	reset_state  : 1;
23472 		mmr_t	reserved_2   : 1;
23473 		mmr_t	mem_idle     : 1;
23474 		mmr_t	fail         : 1;
23475 		mmr_t	in_progress  : 1;
23476 		mmr_t	reserved_1   : 1;
23477 		mmr_t	cmd          : 7;
23478 		mmr_t	reserved_0   : 1;
23479 		mmr_t	block_length : 31;
23491 	mmr_t	sh_md_dbug_data_cfg_regval;
23493 		mmr_t	nibble0_chiplet : 3;
23494 		mmr_t	reserved_0      : 1;
23495 		mmr_t	nibble0_nibble  : 3;
23496 		mmr_t	reserved_1      : 1;
23497 		mmr_t	nibble1_chiplet : 3;
23498 		mmr_t	reserved_2      : 1;
23499 		mmr_t	nibble1_nibble  : 3;
23500 		mmr_t	reserved_3      : 1;
23501 		mmr_t	nibble2_chiplet : 3;
23502 		mmr_t	reserved_4      : 1;
23503 		mmr_t	nibble2_nibble  : 3;
23504 		mmr_t	reserved_5      : 1;
23505 		mmr_t	nibble3_chiplet : 3;
23506 		mmr_t	reserved_6      : 1;
23507 		mmr_t	nibble3_nibble  : 3;
23508 		mmr_t	reserved_7      : 1;
23509 		mmr_t	nibble4_chiplet : 3;
23510 		mmr_t	reserved_8      : 1;
23511 		mmr_t	nibble4_nibble  : 3;
23512 		mmr_t	reserved_9      : 1;
23513 		mmr_t	nibble5_chiplet : 3;
23514 		mmr_t	reserved_10     : 1;
23515 		mmr_t	nibble5_nibble  : 3;
23516 		mmr_t	reserved_11     : 1;
23517 		mmr_t	nibble6_chiplet : 3;
23518 		mmr_t	reserved_12     : 1;
23519 		mmr_t	nibble6_nibble  : 3;
23520 		mmr_t	reserved_13     : 1;
23521 		mmr_t	nibble7_chiplet : 3;
23522 		mmr_t	reserved_14     : 1;
23523 		mmr_t	nibble7_nibble  : 3;
23524 		mmr_t	reserved_15     : 1;
23529 	mmr_t	sh_md_dbug_data_cfg_regval;
23531 		mmr_t	reserved_15     : 1;
23532 		mmr_t	nibble7_nibble  : 3;
23533 		mmr_t	reserved_14     : 1;
23534 		mmr_t	nibble7_chiplet : 3;
23535 		mmr_t	reserved_13     : 1;
23536 		mmr_t	nibble6_nibble  : 3;
23537 		mmr_t	reserved_12     : 1;
23538 		mmr_t	nibble6_chiplet : 3;
23539 		mmr_t	reserved_11     : 1;
23540 		mmr_t	nibble5_nibble  : 3;
23541 		mmr_t	reserved_10     : 1;
23542 		mmr_t	nibble5_chiplet : 3;
23543 		mmr_t	reserved_9      : 1;
23544 		mmr_t	nibble4_nibble  : 3;
23545 		mmr_t	reserved_8      : 1;
23546 		mmr_t	nibble4_chiplet : 3;
23547 		mmr_t	reserved_7      : 1;
23548 		mmr_t	nibble3_nibble  : 3;
23549 		mmr_t	reserved_6      : 1;
23550 		mmr_t	nibble3_chiplet : 3;
23551 		mmr_t	reserved_5      : 1;
23552 		mmr_t	nibble2_nibble  : 3;
23553 		mmr_t	reserved_4      : 1;
23554 		mmr_t	nibble2_chiplet : 3;
23555 		mmr_t	reserved_3      : 1;
23556 		mmr_t	nibble1_nibble  : 3;
23557 		mmr_t	reserved_2      : 1;
23558 		mmr_t	nibble1_chiplet : 3;
23559 		mmr_t	reserved_1      : 1;
23560 		mmr_t	nibble0_nibble  : 3;
23561 		mmr_t	reserved_0      : 1;
23562 		mmr_t	nibble0_chiplet : 3;
23574 	mmr_t	sh_md_dbug_trigger_cfg_regval;
23576 		mmr_t	nibble0_chiplet : 3;
23577 		mmr_t	reserved_0      : 1;
23578 		mmr_t	nibble0_nibble  : 3;
23579 		mmr_t	reserved_1      : 1;
23580 		mmr_t	nibble1_chiplet : 3;
23581 		mmr_t	reserved_2      : 1;
23582 		mmr_t	nibble1_nibble  : 3;
23583 		mmr_t	reserved_3      : 1;
23584 		mmr_t	nibble2_chiplet : 3;
23585 		mmr_t	reserved_4      : 1;
23586 		mmr_t	nibble2_nibble  : 3;
23587 		mmr_t	reserved_5      : 1;
23588 		mmr_t	nibble3_chiplet : 3;
23589 		mmr_t	reserved_6      : 1;
23590 		mmr_t	nibble3_nibble  : 3;
23591 		mmr_t	reserved_7      : 1;
23592 		mmr_t	nibble4_chiplet : 3;
23593 		mmr_t	reserved_8      : 1;
23594 		mmr_t	nibble4_nibble  : 3;
23595 		mmr_t	reserved_9      : 1;
23596 		mmr_t	nibble5_chiplet : 3;
23597 		mmr_t	reserved_10     : 1;
23598 		mmr_t	nibble5_nibble  : 3;
23599 		mmr_t	reserved_11     : 1;
23600 		mmr_t	nibble6_chiplet : 3;
23601 		mmr_t	reserved_12     : 1;
23602 		mmr_t	nibble6_nibble  : 3;
23603 		mmr_t	reserved_13     : 1;
23604 		mmr_t	nibble7_chiplet : 3;
23605 		mmr_t	reserved_14     : 1;
23606 		mmr_t	nibble7_nibble  : 3;
23607 		mmr_t	enable          : 1;
23612 	mmr_t	sh_md_dbug_trigger_cfg_regval;
23614 		mmr_t	enable          : 1;
23615 		mmr_t	nibble7_nibble  : 3;
23616 		mmr_t	reserved_14     : 1;
23617 		mmr_t	nibble7_chiplet : 3;
23618 		mmr_t	reserved_13     : 1;
23619 		mmr_t	nibble6_nibble  : 3;
23620 		mmr_t	reserved_12     : 1;
23621 		mmr_t	nibble6_chiplet : 3;
23622 		mmr_t	reserved_11     : 1;
23623 		mmr_t	nibble5_nibble  : 3;
23624 		mmr_t	reserved_10     : 1;
23625 		mmr_t	nibble5_chiplet : 3;
23626 		mmr_t	reserved_9      : 1;
23627 		mmr_t	nibble4_nibble  : 3;
23628 		mmr_t	reserved_8      : 1;
23629 		mmr_t	nibble4_chiplet : 3;
23630 		mmr_t	reserved_7      : 1;
23631 		mmr_t	nibble3_nibble  : 3;
23632 		mmr_t	reserved_6      : 1;
23633 		mmr_t	nibble3_chiplet : 3;
23634 		mmr_t	reserved_5      : 1;
23635 		mmr_t	nibble2_nibble  : 3;
23636 		mmr_t	reserved_4      : 1;
23637 		mmr_t	nibble2_chiplet : 3;
23638 		mmr_t	reserved_3      : 1;
23639 		mmr_t	nibble1_nibble  : 3;
23640 		mmr_t	reserved_2      : 1;
23641 		mmr_t	nibble1_chiplet : 3;
23642 		mmr_t	reserved_1      : 1;
23643 		mmr_t	nibble0_nibble  : 3;
23644 		mmr_t	reserved_0      : 1;
23645 		mmr_t	nibble0_chiplet : 3;
23657 	mmr_t	sh_md_dbug_compare_regval;
23659 		mmr_t	pattern     : 32;
23660 		mmr_t	mask        : 32;
23665 	mmr_t	sh_md_dbug_compare_regval;
23667 		mmr_t	mask        : 32;
23668 		mmr_t	pattern     : 32;
23680 	mmr_t	sh_x_mod_dbug_sel_regval;
23682 		mmr_t	tag_sel     : 8;
23683 		mmr_t	wbq_sel     : 8;
23684 		mmr_t	arb_sel     : 8;
23685 		mmr_t	atl_sel     : 11;
23686 		mmr_t	atr_sel     : 11;
23687 		mmr_t	dql_sel     : 6;
23688 		mmr_t	dqr_sel     : 6;
23689 		mmr_t	reserved_0  : 6;
23694 	mmr_t	sh_x_mod_dbug_sel_regval;
23696 		mmr_t	reserved_0  : 6;
23697 		mmr_t	dqr_sel     : 6;
23698 		mmr_t	dql_sel     : 6;
23699 		mmr_t	atr_sel     : 11;
23700 		mmr_t	atl_sel     : 11;
23701 		mmr_t	arb_sel     : 8;
23702 		mmr_t	wbq_sel     : 8;
23703 		mmr_t	tag_sel     : 8;
23715 	mmr_t	sh_x_dbug_sel_regval;
23717 		mmr_t	dbg_sel     : 24;
23718 		mmr_t	reserved_0  : 40;
23723 	mmr_t	sh_x_dbug_sel_regval;
23725 		mmr_t	reserved_0  : 40;
23726 		mmr_t	dbg_sel     : 24;
23738 	mmr_t	sh_x_laddr_cmp_regval;
23740 		mmr_t	cmp_val     : 28;
23741 		mmr_t	reserved_0  : 4;
23742 		mmr_t	mask_val    : 28;
23743 		mmr_t	reserved_1  : 4;
23748 	mmr_t	sh_x_laddr_cmp_regval;
23750 		mmr_t	reserved_1  : 4;
23751 		mmr_t	mask_val    : 28;
23752 		mmr_t	reserved_0  : 4;
23753 		mmr_t	cmp_val     : 28;
23765 	mmr_t	sh_x_raddr_cmp_regval;
23767 		mmr_t	cmp_val     : 28;
23768 		mmr_t	reserved_0  : 4;
23769 		mmr_t	mask_val    : 28;
23770 		mmr_t	reserved_1  : 4;
23775 	mmr_t	sh_x_raddr_cmp_regval;
23777 		mmr_t	reserved_1  : 4;
23778 		mmr_t	mask_val    : 28;
23779 		mmr_t	reserved_0  : 4;
23780 		mmr_t	cmp_val     : 28;
23792 	mmr_t	sh_x_tag_cmp_regval;
23794 		mmr_t	cmd         : 8;
23795 		mmr_t	addr        : 33;
23796 		mmr_t	src         : 14;
23797 		mmr_t	reserved_0  : 9;
23802 	mmr_t	sh_x_tag_cmp_regval;
23804 		mmr_t	reserved_0  : 9;
23805 		mmr_t	src         : 14;
23806 		mmr_t	addr        : 33;
23807 		mmr_t	cmd         : 8;
23819 	mmr_t	sh_x_tag_mask_regval;
23821 		mmr_t	cmd         : 8;
23822 		mmr_t	addr        : 33;
23823 		mmr_t	src         : 14;
23824 		mmr_t	reserved_0  : 9;
23829 	mmr_t	sh_x_tag_mask_regval;
23831 		mmr_t	reserved_0  : 9;
23832 		mmr_t	src         : 14;
23833 		mmr_t	addr        : 33;
23834 		mmr_t	cmd         : 8;
23846 	mmr_t	sh_y_mod_dbug_sel_regval;
23848 		mmr_t	tag_sel     : 8;
23849 		mmr_t	wbq_sel     : 8;
23850 		mmr_t	arb_sel     : 8;
23851 		mmr_t	atl_sel     : 11;
23852 		mmr_t	atr_sel     : 11;
23853 		mmr_t	dql_sel     : 6;
23854 		mmr_t	dqr_sel     : 6;
23855 		mmr_t	reserved_0  : 6;
23860 	mmr_t	sh_y_mod_dbug_sel_regval;
23862 		mmr_t	reserved_0  : 6;
23863 		mmr_t	dqr_sel     : 6;
23864 		mmr_t	dql_sel     : 6;
23865 		mmr_t	atr_sel     : 11;
23866 		mmr_t	atl_sel     : 11;
23867 		mmr_t	arb_sel     : 8;
23868 		mmr_t	wbq_sel     : 8;
23869 		mmr_t	tag_sel     : 8;
23881 	mmr_t	sh_y_dbug_sel_regval;
23883 		mmr_t	dbg_sel     : 24;
23884 		mmr_t	reserved_0  : 40;
23889 	mmr_t	sh_y_dbug_sel_regval;
23891 		mmr_t	reserved_0  : 40;
23892 		mmr_t	dbg_sel     : 24;
23904 	mmr_t	sh_y_laddr_cmp_regval;
23906 		mmr_t	cmp_val     : 28;
23907 		mmr_t	reserved_0  : 4;
23908 		mmr_t	mask_val    : 28;
23909 		mmr_t	reserved_1  : 4;
23914 	mmr_t	sh_y_laddr_cmp_regval;
23916 		mmr_t	reserved_1  : 4;
23917 		mmr_t	mask_val    : 28;
23918 		mmr_t	reserved_0  : 4;
23919 		mmr_t	cmp_val     : 28;
23931 	mmr_t	sh_y_raddr_cmp_regval;
23933 		mmr_t	cmp_val     : 28;
23934 		mmr_t	reserved_0  : 4;
23935 		mmr_t	mask_val    : 28;
23936 		mmr_t	reserved_1  : 4;
23941 	mmr_t	sh_y_raddr_cmp_regval;
23943 		mmr_t	reserved_1  : 4;
23944 		mmr_t	mask_val    : 28;
23945 		mmr_t	reserved_0  : 4;
23946 		mmr_t	cmp_val     : 28;
23958 	mmr_t	sh_y_tag_cmp_regval;
23960 		mmr_t	cmd         : 8;
23961 		mmr_t	addr        : 33;
23962 		mmr_t	src         : 14;
23963 		mmr_t	reserved_0  : 9;
23968 	mmr_t	sh_y_tag_cmp_regval;
23970 		mmr_t	reserved_0  : 9;
23971 		mmr_t	src         : 14;
23972 		mmr_t	addr        : 33;
23973 		mmr_t	cmd         : 8;
23985 	mmr_t	sh_y_tag_mask_regval;
23987 		mmr_t	cmd         : 8;
23988 		mmr_t	addr        : 33;
23989 		mmr_t	src         : 14;
23990 		mmr_t	reserved_0  : 9;
23995 	mmr_t	sh_y_tag_mask_regval;
23997 		mmr_t	reserved_0  : 9;
23998 		mmr_t	src         : 14;
23999 		mmr_t	addr        : 33;
24000 		mmr_t	cmd         : 8;
24012 	mmr_t	sh_md_jnr_dbug_data_cfg_regval;
24014 		mmr_t	nibble0_sel : 3;
24015 		mmr_t	reserved_0  : 1;
24016 		mmr_t	nibble1_sel : 3;
24017 		mmr_t	reserved_1  : 1;
24018 		mmr_t	nibble2_sel : 3;
24019 		mmr_t	reserved_2  : 1;
24020 		mmr_t	nibble3_sel : 3;
24021 		mmr_t	reserved_3  : 1;
24022 		mmr_t	nibble4_sel : 3;
24023 		mmr_t	reserved_4  : 1;
24024 		mmr_t	nibble5_sel : 3;
24025 		mmr_t	reserved_5  : 1;
24026 		mmr_t	nibble6_sel : 3;
24027 		mmr_t	reserved_6  : 1;
24028 		mmr_t	nibble7_sel : 3;
24029 		mmr_t	reserved_7  : 33;
24034 	mmr_t	sh_md_jnr_dbug_data_cfg_regval;
24036 		mmr_t	reserved_7  : 33;
24037 		mmr_t	nibble7_sel : 3;
24038 		mmr_t	reserved_6  : 1;
24039 		mmr_t	nibble6_sel : 3;
24040 		mmr_t	reserved_5  : 1;
24041 		mmr_t	nibble5_sel : 3;
24042 		mmr_t	reserved_4  : 1;
24043 		mmr_t	nibble4_sel : 3;
24044 		mmr_t	reserved_3  : 1;
24045 		mmr_t	nibble3_sel : 3;
24046 		mmr_t	reserved_2  : 1;
24047 		mmr_t	nibble2_sel : 3;
24048 		mmr_t	reserved_1  : 1;
24049 		mmr_t	nibble1_sel : 3;
24050 		mmr_t	reserved_0  : 1;
24051 		mmr_t	nibble0_sel : 3;
24063 	mmr_t	sh_md_last_credit_regval;
24065 		mmr_t	rq_to_pi    : 6;
24066 		mmr_t	reserved_0  : 2;
24067 		mmr_t	rp_to_pi    : 6;
24068 		mmr_t	reserved_1  : 2;
24069 		mmr_t	rq_to_xn    : 6;
24070 		mmr_t	reserved_2  : 2;
24071 		mmr_t	rp_to_xn    : 6;
24072 		mmr_t	reserved_3  : 2;
24073 		mmr_t	to_lb       : 6;
24074 		mmr_t	reserved_4  : 26;
24079 	mmr_t	sh_md_last_credit_regval;
24081 		mmr_t	reserved_4  : 26;
24082 		mmr_t	to_lb       : 6;
24083 		mmr_t	reserved_3  : 2;
24084 		mmr_t	rp_to_xn    : 6;
24085 		mmr_t	reserved_2  : 2;
24086 		mmr_t	rq_to_xn    : 6;
24087 		mmr_t	reserved_1  : 2;
24088 		mmr_t	rp_to_pi    : 6;
24089 		mmr_t	reserved_0  : 2;
24090 		mmr_t	rq_to_pi    : 6;
24102 	mmr_t	sh_mem_capture_addr_regval;
24104 		mmr_t	reserved_0  : 3;
24105 		mmr_t	addr        : 33;
24106 		mmr_t	cmd         : 8;
24107 		mmr_t	reserved_1  : 20;
24112 	mmr_t	sh_mem_capture_addr_regval;
24114 		mmr_t	reserved_1  : 20;
24115 		mmr_t	cmd         : 8;
24116 		mmr_t	addr        : 33;
24117 		mmr_t	reserved_0  : 3;
24129 	mmr_t	sh_mem_capture_mask_regval;
24131 		mmr_t	reserved_0    : 3;
24132 		mmr_t	addr          : 33;
24133 		mmr_t	cmd           : 8;
24134 		mmr_t	enable_local  : 1;
24135 		mmr_t	enable_remote : 1;
24136 		mmr_t	reserved_1    : 18;
24141 	mmr_t	sh_mem_capture_mask_regval;
24143 		mmr_t	reserved_1    : 18;
24144 		mmr_t	enable_remote : 1;
24145 		mmr_t	enable_local  : 1;
24146 		mmr_t	cmd           : 8;
24147 		mmr_t	addr          : 33;
24148 		mmr_t	reserved_0    : 3;
24160 	mmr_t	sh_mem_capture_hdr_regval;
24162 		mmr_t	reserved_0  : 3;
24163 		mmr_t	addr        : 33;
24164 		mmr_t	cmd         : 8;
24165 		mmr_t	src         : 14;
24166 		mmr_t	cntr        : 6;
24171 	mmr_t	sh_mem_capture_hdr_regval;
24173 		mmr_t	cntr        : 6;
24174 		mmr_t	src         : 14;
24175 		mmr_t	cmd         : 8;
24176 		mmr_t	addr        : 33;
24177 		mmr_t	reserved_0  : 3;
24189 	mmr_t	sh_md_dqlp_mmr_dir_config_regval;
24191 		mmr_t	sys_size    : 3;
24192 		mmr_t	en_direcc   : 1;
24193 		mmr_t	en_dirpois  : 1;
24194 		mmr_t	reserved_0  : 59;
24199 	mmr_t	sh_md_dqlp_mmr_dir_config_regval;
24201 		mmr_t	reserved_0  : 59;
24202 		mmr_t	en_dirpois  : 1;
24203 		mmr_t	en_direcc   : 1;
24204 		mmr_t	sys_size    : 3;
24216 	mmr_t	sh_md_dqlp_mmr_dir_presvec0_regval;
24218 		mmr_t	vec         : 64;
24223 	mmr_t	sh_md_dqlp_mmr_dir_presvec0_regval;
24225 		mmr_t	vec         : 64;
24237 	mmr_t	sh_md_dqlp_mmr_dir_presvec1_regval;
24239 		mmr_t	vec         : 64;
24244 	mmr_t	sh_md_dqlp_mmr_dir_presvec1_regval;
24246 		mmr_t	vec         : 64;
24258 	mmr_t	sh_md_dqlp_mmr_dir_presvec2_regval;
24260 		mmr_t	vec         : 64;
24265 	mmr_t	sh_md_dqlp_mmr_dir_presvec2_regval;
24267 		mmr_t	vec         : 64;
24279 	mmr_t	sh_md_dqlp_mmr_dir_presvec3_regval;
24281 		mmr_t	vec         : 64;
24286 	mmr_t	sh_md_dqlp_mmr_dir_presvec3_regval;
24288 		mmr_t	vec         : 64;
24300 	mmr_t	sh_md_dqlp_mmr_dir_locvec0_regval;
24302 		mmr_t	vec         : 64;
24307 	mmr_t	sh_md_dqlp_mmr_dir_locvec0_regval;
24309 		mmr_t	vec         : 64;
24321 	mmr_t	sh_md_dqlp_mmr_dir_locvec1_regval;
24323 		mmr_t	vec         : 64;
24328 	mmr_t	sh_md_dqlp_mmr_dir_locvec1_regval;
24330 		mmr_t	vec         : 64;
24342 	mmr_t	sh_md_dqlp_mmr_dir_locvec2_regval;
24344 		mmr_t	vec         : 64;
24349 	mmr_t	sh_md_dqlp_mmr_dir_locvec2_regval;
24351 		mmr_t	vec         : 64;
24363 	mmr_t	sh_md_dqlp_mmr_dir_locvec3_regval;
24365 		mmr_t	vec         : 64;
24370 	mmr_t	sh_md_dqlp_mmr_dir_locvec3_regval;
24372 		mmr_t	vec         : 64;
24384 	mmr_t	sh_md_dqlp_mmr_dir_locvec4_regval;
24386 		mmr_t	vec         : 64;
24391 	mmr_t	sh_md_dqlp_mmr_dir_locvec4_regval;
24393 		mmr_t	vec         : 64;
24405 	mmr_t	sh_md_dqlp_mmr_dir_locvec5_regval;
24407 		mmr_t	vec         : 64;
24412 	mmr_t	sh_md_dqlp_mmr_dir_locvec5_regval;
24414 		mmr_t	vec         : 64;
24426 	mmr_t	sh_md_dqlp_mmr_dir_locvec6_regval;
24428 		mmr_t	vec         : 64;
24433 	mmr_t	sh_md_dqlp_mmr_dir_locvec6_regval;
24435 		mmr_t	vec         : 64;
24447 	mmr_t	sh_md_dqlp_mmr_dir_locvec7_regval;
24449 		mmr_t	vec         : 64;
24454 	mmr_t	sh_md_dqlp_mmr_dir_locvec7_regval;
24456 		mmr_t	vec         : 64;
24468 	mmr_t	sh_md_dqlp_mmr_dir_privec0_regval;
24470 		mmr_t	in          : 14;
24471 		mmr_t	out         : 14;
24472 		mmr_t	reserved_0  : 36;
24477 	mmr_t	sh_md_dqlp_mmr_dir_privec0_regval;
24479 		mmr_t	reserved_0  : 36;
24480 		mmr_t	out         : 14;
24481 		mmr_t	in          : 14;
24493 	mmr_t	sh_md_dqlp_mmr_dir_privec1_regval;
24495 		mmr_t	in          : 14;
24496 		mmr_t	out         : 14;
24497 		mmr_t	reserved_0  : 36;
24502 	mmr_t	sh_md_dqlp_mmr_dir_privec1_regval;
24504 		mmr_t	reserved_0  : 36;
24505 		mmr_t	out         : 14;
24506 		mmr_t	in          : 14;
24518 	mmr_t	sh_md_dqlp_mmr_dir_privec2_regval;
24520 		mmr_t	in          : 14;
24521 		mmr_t	out         : 14;
24522 		mmr_t	reserved_0  : 36;
24527 	mmr_t	sh_md_dqlp_mmr_dir_privec2_regval;
24529 		mmr_t	reserved_0  : 36;
24530 		mmr_t	out         : 14;
24531 		mmr_t	in          : 14;
24543 	mmr_t	sh_md_dqlp_mmr_dir_privec3_regval;
24545 		mmr_t	in          : 14;
24546 		mmr_t	out         : 14;
24547 		mmr_t	reserved_0  : 36;
24552 	mmr_t	sh_md_dqlp_mmr_dir_privec3_regval;
24554 		mmr_t	reserved_0  : 36;
24555 		mmr_t	out         : 14;
24556 		mmr_t	in          : 14;
24568 	mmr_t	sh_md_dqlp_mmr_dir_privec4_regval;
24570 		mmr_t	in          : 14;
24571 		mmr_t	out         : 14;
24572 		mmr_t	reserved_0  : 36;
24577 	mmr_t	sh_md_dqlp_mmr_dir_privec4_regval;
24579 		mmr_t	reserved_0  : 36;
24580 		mmr_t	out         : 14;
24581 		mmr_t	in          : 14;
24593 	mmr_t	sh_md_dqlp_mmr_dir_privec5_regval;
24595 		mmr_t	in          : 14;
24596 		mmr_t	out         : 14;
24597 		mmr_t	reserved_0  : 36;
24602 	mmr_t	sh_md_dqlp_mmr_dir_privec5_regval;
24604 		mmr_t	reserved_0  : 36;
24605 		mmr_t	out         : 14;
24606 		mmr_t	in          : 14;
24618 	mmr_t	sh_md_dqlp_mmr_dir_privec6_regval;
24620 		mmr_t	in          : 14;
24621 		mmr_t	out         : 14;
24622 		mmr_t	reserved_0  : 36;
24627 	mmr_t	sh_md_dqlp_mmr_dir_privec6_regval;
24629 		mmr_t	reserved_0  : 36;
24630 		mmr_t	out         : 14;
24631 		mmr_t	in          : 14;
24643 	mmr_t	sh_md_dqlp_mmr_dir_privec7_regval;
24645 		mmr_t	in          : 14;
24646 		mmr_t	out         : 14;
24647 		mmr_t	reserved_0  : 36;
24652 	mmr_t	sh_md_dqlp_mmr_dir_privec7_regval;
24654 		mmr_t	reserved_0  : 36;
24655 		mmr_t	out         : 14;
24656 		mmr_t	in          : 14;
24668 	mmr_t	sh_md_dqlp_mmr_dir_timer_regval;
24670 		mmr_t	timer_div   : 12;
24671 		mmr_t	timer_en    : 1;
24672 		mmr_t	timer_cur   : 9;
24673 		mmr_t	reserved_0  : 42;
24678 	mmr_t	sh_md_dqlp_mmr_dir_timer_regval;
24680 		mmr_t	reserved_0  : 42;
24681 		mmr_t	timer_cur   : 9;
24682 		mmr_t	timer_en    : 1;
24683 		mmr_t	timer_div   : 12;
24695 	mmr_t	sh_md_dqlp_mmr_piowd_dir_entry_regval;
24697 		mmr_t	dira        : 26;
24698 		mmr_t	dirb        : 26;
24699 		mmr_t	pri         : 3;
24700 		mmr_t	acc         : 3;
24701 		mmr_t	reserved_0  : 6;
24706 	mmr_t	sh_md_dqlp_mmr_piowd_dir_entry_regval;
24708 		mmr_t	reserved_0  : 6;
24709 		mmr_t	acc         : 3;
24710 		mmr_t	pri         : 3;
24711 		mmr_t	dirb        : 26;
24712 		mmr_t	dira        : 26;
24724 	mmr_t	sh_md_dqlp_mmr_piowd_dir_ecc_regval;
24726 		mmr_t	ecca        : 7;
24727 		mmr_t	eccb        : 7;
24728 		mmr_t	reserved_0  : 50;
24733 	mmr_t	sh_md_dqlp_mmr_piowd_dir_ecc_regval;
24735 		mmr_t	reserved_0  : 50;
24736 		mmr_t	eccb        : 7;
24737 		mmr_t	ecca        : 7;
24749 	mmr_t	sh_md_dqlp_mmr_xpiord_xdir_entry_regval;
24751 		mmr_t	dira        : 26;
24752 		mmr_t	dirb        : 26;
24753 		mmr_t	pri         : 3;
24754 		mmr_t	acc         : 3;
24755 		mmr_t	cor         : 1;
24756 		mmr_t	unc         : 1;
24757 		mmr_t	reserved_0  : 4;
24762 	mmr_t	sh_md_dqlp_mmr_xpiord_xdir_entry_regval;
24764 		mmr_t	reserved_0  : 4;
24765 		mmr_t	unc         : 1;
24766 		mmr_t	cor         : 1;
24767 		mmr_t	acc         : 3;
24768 		mmr_t	pri         : 3;
24769 		mmr_t	dirb        : 26;
24770 		mmr_t	dira        : 26;
24782 	mmr_t	sh_md_dqlp_mmr_xpiord_xdir_ecc_regval;
24784 		mmr_t	ecca        : 7;
24785 		mmr_t	eccb        : 7;
24786 		mmr_t	reserved_0  : 50;
24791 	mmr_t	sh_md_dqlp_mmr_xpiord_xdir_ecc_regval;
24793 		mmr_t	reserved_0  : 50;
24794 		mmr_t	eccb        : 7;
24795 		mmr_t	ecca        : 7;
24807 	mmr_t	sh_md_dqlp_mmr_ypiord_ydir_entry_regval;
24809 		mmr_t	dira        : 26;
24810 		mmr_t	dirb        : 26;
24811 		mmr_t	pri         : 3;
24812 		mmr_t	acc         : 3;
24813 		mmr_t	cor         : 1;
24814 		mmr_t	unc         : 1;
24815 		mmr_t	reserved_0  : 4;
24820 	mmr_t	sh_md_dqlp_mmr_ypiord_ydir_entry_regval;
24822 		mmr_t	reserved_0  : 4;
24823 		mmr_t	unc         : 1;
24824 		mmr_t	cor         : 1;
24825 		mmr_t	acc         : 3;
24826 		mmr_t	pri         : 3;
24827 		mmr_t	dirb        : 26;
24828 		mmr_t	dira        : 26;
24840 	mmr_t	sh_md_dqlp_mmr_ypiord_ydir_ecc_regval;
24842 		mmr_t	ecca        : 7;
24843 		mmr_t	eccb        : 7;
24844 		mmr_t	reserved_0  : 50;
24849 	mmr_t	sh_md_dqlp_mmr_ypiord_ydir_ecc_regval;
24851 		mmr_t	reserved_0  : 50;
24852 		mmr_t	eccb        : 7;
24853 		mmr_t	ecca        : 7;
24865 	mmr_t	sh_md_dqlp_mmr_xcerr1_regval;
24867 		mmr_t	grp1        : 36;
24868 		mmr_t	val         : 1;
24869 		mmr_t	more        : 1;
24870 		mmr_t	arm         : 1;
24871 		mmr_t	reserved_0  : 25;
24876 	mmr_t	sh_md_dqlp_mmr_xcerr1_regval;
24878 		mmr_t	reserved_0  : 25;
24879 		mmr_t	arm         : 1;
24880 		mmr_t	more        : 1;
24881 		mmr_t	val         : 1;
24882 		mmr_t	grp1        : 36;
24894 	mmr_t	sh_md_dqlp_mmr_xcerr2_regval;
24896 		mmr_t	grp2        : 36;
24897 		mmr_t	val         : 1;
24898 		mmr_t	more        : 1;
24899 		mmr_t	reserved_0  : 26;
24904 	mmr_t	sh_md_dqlp_mmr_xcerr2_regval;
24906 		mmr_t	reserved_0  : 26;
24907 		mmr_t	more        : 1;
24908 		mmr_t	val         : 1;
24909 		mmr_t	grp2        : 36;
24921 	mmr_t	sh_md_dqlp_mmr_xuerr1_regval;
24923 		mmr_t	grp1        : 36;
24924 		mmr_t	val         : 1;
24925 		mmr_t	more        : 1;
24926 		mmr_t	arm         : 1;
24927 		mmr_t	reserved_0  : 25;
24932 	mmr_t	sh_md_dqlp_mmr_xuerr1_regval;
24934 		mmr_t	reserved_0  : 25;
24935 		mmr_t	arm         : 1;
24936 		mmr_t	more        : 1;
24937 		mmr_t	val         : 1;
24938 		mmr_t	grp1        : 36;
24950 	mmr_t	sh_md_dqlp_mmr_xuerr2_regval;
24952 		mmr_t	grp2        : 36;
24953 		mmr_t	val         : 1;
24954 		mmr_t	more        : 1;
24955 		mmr_t	reserved_0  : 26;
24960 	mmr_t	sh_md_dqlp_mmr_xuerr2_regval;
24962 		mmr_t	reserved_0  : 26;
24963 		mmr_t	more        : 1;
24964 		mmr_t	val         : 1;
24965 		mmr_t	grp2        : 36;
24977 	mmr_t	sh_md_dqlp_mmr_xperr_regval;
24979 		mmr_t	dir         : 26;
24980 		mmr_t	cmd         : 8;
24981 		mmr_t	src         : 14;
24982 		mmr_t	prige       : 1;
24983 		mmr_t	priv        : 1;
24984 		mmr_t	cor         : 1;
24985 		mmr_t	unc         : 1;
24986 		mmr_t	mybit       : 8;
24987 		mmr_t	val         : 1;
24988 		mmr_t	more        : 1;
24989 		mmr_t	arm         : 1;
24990 		mmr_t	reserved_0  : 1;
24995 	mmr_t	sh_md_dqlp_mmr_xperr_regval;
24997 		mmr_t	reserved_0  : 1;
24998 		mmr_t	arm         : 1;
24999 		mmr_t	more        : 1;
25000 		mmr_t	val         : 1;
25001 		mmr_t	mybit       : 8;
25002 		mmr_t	unc         : 1;
25003 		mmr_t	cor         : 1;
25004 		mmr_t	priv        : 1;
25005 		mmr_t	prige       : 1;
25006 		mmr_t	src         : 14;
25007 		mmr_t	cmd         : 8;
25008 		mmr_t	dir         : 26;
25020 	mmr_t	sh_md_dqlp_mmr_ycerr1_regval;
25022 		mmr_t	grp1        : 36;
25023 		mmr_t	val         : 1;
25024 		mmr_t	more        : 1;
25025 		mmr_t	arm         : 1;
25026 		mmr_t	reserved_0  : 25;
25031 	mmr_t	sh_md_dqlp_mmr_ycerr1_regval;
25033 		mmr_t	reserved_0  : 25;
25034 		mmr_t	arm         : 1;
25035 		mmr_t	more        : 1;
25036 		mmr_t	val         : 1;
25037 		mmr_t	grp1        : 36;
25049 	mmr_t	sh_md_dqlp_mmr_ycerr2_regval;
25051 		mmr_t	grp2        : 36;
25052 		mmr_t	val         : 1;
25053 		mmr_t	more        : 1;
25054 		mmr_t	reserved_0  : 26;
25059 	mmr_t	sh_md_dqlp_mmr_ycerr2_regval;
25061 		mmr_t	reserved_0  : 26;
25062 		mmr_t	more        : 1;
25063 		mmr_t	val         : 1;
25064 		mmr_t	grp2        : 36;
25076 	mmr_t	sh_md_dqlp_mmr_yuerr1_regval;
25078 		mmr_t	grp1        : 36;
25079 		mmr_t	val         : 1;
25080 		mmr_t	more        : 1;
25081 		mmr_t	arm         : 1;
25082 		mmr_t	reserved_0  : 25;
25087 	mmr_t	sh_md_dqlp_mmr_yuerr1_regval;
25089 		mmr_t	reserved_0  : 25;
25090 		mmr_t	arm         : 1;
25091 		mmr_t	more        : 1;
25092 		mmr_t	val         : 1;
25093 		mmr_t	grp1        : 36;
25105 	mmr_t	sh_md_dqlp_mmr_yuerr2_regval;
25107 		mmr_t	grp2        : 36;
25108 		mmr_t	val         : 1;
25109 		mmr_t	more        : 1;
25110 		mmr_t	reserved_0  : 26;
25115 	mmr_t	sh_md_dqlp_mmr_yuerr2_regval;
25117 		mmr_t	reserved_0  : 26;
25118 		mmr_t	more        : 1;
25119 		mmr_t	val         : 1;
25120 		mmr_t	grp2        : 36;
25132 	mmr_t	sh_md_dqlp_mmr_yperr_regval;
25134 		mmr_t	dir         : 26;
25135 		mmr_t	cmd         : 8;
25136 		mmr_t	src         : 14;
25137 		mmr_t	prige       : 1;
25138 		mmr_t	priv        : 1;
25139 		mmr_t	cor         : 1;
25140 		mmr_t	unc         : 1;
25141 		mmr_t	mybit       : 8;
25142 		mmr_t	val         : 1;
25143 		mmr_t	more        : 1;
25144 		mmr_t	arm         : 1;
25145 		mmr_t	reserved_0  : 1;
25150 	mmr_t	sh_md_dqlp_mmr_yperr_regval;
25152 		mmr_t	reserved_0  : 1;
25153 		mmr_t	arm         : 1;
25154 		mmr_t	more        : 1;
25155 		mmr_t	val         : 1;
25156 		mmr_t	mybit       : 8;
25157 		mmr_t	unc         : 1;
25158 		mmr_t	cor         : 1;
25159 		mmr_t	priv        : 1;
25160 		mmr_t	prige       : 1;
25161 		mmr_t	src         : 14;
25162 		mmr_t	cmd         : 8;
25163 		mmr_t	dir         : 26;
25175 	mmr_t	sh_md_dqlp_mmr_dir_cmdtrig_regval;
25177 		mmr_t	cmd0        : 8;
25178 		mmr_t	cmd1        : 8;
25179 		mmr_t	cmd2        : 8;
25180 		mmr_t	cmd3        : 8;
25181 		mmr_t	reserved_0  : 32;
25186 	mmr_t	sh_md_dqlp_mmr_dir_cmdtrig_regval;
25188 		mmr_t	reserved_0  : 32;
25189 		mmr_t	cmd3        : 8;
25190 		mmr_t	cmd2        : 8;
25191 		mmr_t	cmd1        : 8;
25192 		mmr_t	cmd0        : 8;
25204 	mmr_t	sh_md_dqlp_mmr_dir_tbltrig_regval;
25206 		mmr_t	src         : 14;
25207 		mmr_t	cmd         : 8;
25208 		mmr_t	acc         : 2;
25209 		mmr_t	prige       : 1;
25210 		mmr_t	dirst       : 9;
25211 		mmr_t	mybit       : 8;
25212 		mmr_t	reserved_0  : 22;
25217 	mmr_t	sh_md_dqlp_mmr_dir_tbltrig_regval;
25219 		mmr_t	reserved_0  : 22;
25220 		mmr_t	mybit       : 8;
25221 		mmr_t	dirst       : 9;
25222 		mmr_t	prige       : 1;
25223 		mmr_t	acc         : 2;
25224 		mmr_t	cmd         : 8;
25225 		mmr_t	src         : 14;
25237 	mmr_t	sh_md_dqlp_mmr_dir_tblmask_regval;
25239 		mmr_t	src         : 14;
25240 		mmr_t	cmd         : 8;
25241 		mmr_t	acc         : 2;
25242 		mmr_t	prige       : 1;
25243 		mmr_t	dirst       : 9;
25244 		mmr_t	mybit       : 8;
25245 		mmr_t	reserved_0  : 22;
25250 	mmr_t	sh_md_dqlp_mmr_dir_tblmask_regval;
25252 		mmr_t	reserved_0  : 22;
25253 		mmr_t	mybit       : 8;
25254 		mmr_t	dirst       : 9;
25255 		mmr_t	prige       : 1;
25256 		mmr_t	acc         : 2;
25257 		mmr_t	cmd         : 8;
25258 		mmr_t	src         : 14;
25270 	mmr_t	sh_md_dqlp_mmr_xbist_h_regval;
25272 		mmr_t	pat         : 32;
25273 		mmr_t	reserved_0  : 8;
25274 		mmr_t	inv         : 1;
25275 		mmr_t	rot         : 1;
25276 		mmr_t	arm         : 1;
25277 		mmr_t	reserved_1  : 21;
25282 	mmr_t	sh_md_dqlp_mmr_xbist_h_regval;
25284 		mmr_t	reserved_1  : 21;
25285 		mmr_t	arm         : 1;
25286 		mmr_t	rot         : 1;
25287 		mmr_t	inv         : 1;
25288 		mmr_t	reserved_0  : 8;
25289 		mmr_t	pat         : 32;
25301 	mmr_t	sh_md_dqlp_mmr_xbist_l_regval;
25303 		mmr_t	pat         : 32;
25304 		mmr_t	reserved_0  : 8;
25305 		mmr_t	inv         : 1;
25306 		mmr_t	rot         : 1;
25307 		mmr_t	reserved_1  : 22;
25312 	mmr_t	sh_md_dqlp_mmr_xbist_l_regval;
25314 		mmr_t	reserved_1  : 22;
25315 		mmr_t	rot         : 1;
25316 		mmr_t	inv         : 1;
25317 		mmr_t	reserved_0  : 8;
25318 		mmr_t	pat         : 32;
25330 	mmr_t	sh_md_dqlp_mmr_xbist_err_h_regval;
25332 		mmr_t	pat         : 32;
25333 		mmr_t	reserved_0  : 8;
25334 		mmr_t	val         : 1;
25335 		mmr_t	more        : 1;
25336 		mmr_t	reserved_1  : 22;
25341 	mmr_t	sh_md_dqlp_mmr_xbist_err_h_regval;
25343 		mmr_t	reserved_1  : 22;
25344 		mmr_t	more        : 1;
25345 		mmr_t	val         : 1;
25346 		mmr_t	reserved_0  : 8;
25347 		mmr_t	pat         : 32;
25359 	mmr_t	sh_md_dqlp_mmr_xbist_err_l_regval;
25361 		mmr_t	pat         : 32;
25362 		mmr_t	reserved_0  : 8;
25363 		mmr_t	val         : 1;
25364 		mmr_t	more        : 1;
25365 		mmr_t	reserved_1  : 22;
25370 	mmr_t	sh_md_dqlp_mmr_xbist_err_l_regval;
25372 		mmr_t	reserved_1  : 22;
25373 		mmr_t	more        : 1;
25374 		mmr_t	val         : 1;
25375 		mmr_t	reserved_0  : 8;
25376 		mmr_t	pat         : 32;
25388 	mmr_t	sh_md_dqlp_mmr_ybist_h_regval;
25390 		mmr_t	pat         : 32;
25391 		mmr_t	reserved_0  : 8;
25392 		mmr_t	inv         : 1;
25393 		mmr_t	rot         : 1;
25394 		mmr_t	arm         : 1;
25395 		mmr_t	reserved_1  : 21;
25400 	mmr_t	sh_md_dqlp_mmr_ybist_h_regval;
25402 		mmr_t	reserved_1  : 21;
25403 		mmr_t	arm         : 1;
25404 		mmr_t	rot         : 1;
25405 		mmr_t	inv         : 1;
25406 		mmr_t	reserved_0  : 8;
25407 		mmr_t	pat         : 32;
25419 	mmr_t	sh_md_dqlp_mmr_ybist_l_regval;
25421 		mmr_t	pat         : 32;
25422 		mmr_t	reserved_0  : 8;
25423 		mmr_t	inv         : 1;
25424 		mmr_t	rot         : 1;
25425 		mmr_t	reserved_1  : 22;
25430 	mmr_t	sh_md_dqlp_mmr_ybist_l_regval;
25432 		mmr_t	reserved_1  : 22;
25433 		mmr_t	rot         : 1;
25434 		mmr_t	inv         : 1;
25435 		mmr_t	reserved_0  : 8;
25436 		mmr_t	pat         : 32;
25448 	mmr_t	sh_md_dqlp_mmr_ybist_err_h_regval;
25450 		mmr_t	pat         : 32;
25451 		mmr_t	reserved_0  : 8;
25452 		mmr_t	val         : 1;
25453 		mmr_t	more        : 1;
25454 		mmr_t	reserved_1  : 22;
25459 	mmr_t	sh_md_dqlp_mmr_ybist_err_h_regval;
25461 		mmr_t	reserved_1  : 22;
25462 		mmr_t	more        : 1;
25463 		mmr_t	val         : 1;
25464 		mmr_t	reserved_0  : 8;
25465 		mmr_t	pat         : 32;
25477 	mmr_t	sh_md_dqlp_mmr_ybist_err_l_regval;
25479 		mmr_t	pat         : 32;
25480 		mmr_t	reserved_0  : 8;
25481 		mmr_t	val         : 1;
25482 		mmr_t	more        : 1;
25483 		mmr_t	reserved_1  : 22;
25488 	mmr_t	sh_md_dqlp_mmr_ybist_err_l_regval;
25490 		mmr_t	reserved_1  : 22;
25491 		mmr_t	more        : 1;
25492 		mmr_t	val         : 1;
25493 		mmr_t	reserved_0  : 8;
25494 		mmr_t	pat         : 32;
25506 	mmr_t	sh_md_dqls_mmr_xbist_h_regval;
25508 		mmr_t	pat         : 40;
25509 		mmr_t	inv         : 1;
25510 		mmr_t	rot         : 1;
25511 		mmr_t	arm         : 1;
25512 		mmr_t	reserved_0  : 21;
25517 	mmr_t	sh_md_dqls_mmr_xbist_h_regval;
25519 		mmr_t	reserved_0  : 21;
25520 		mmr_t	arm         : 1;
25521 		mmr_t	rot         : 1;
25522 		mmr_t	inv         : 1;
25523 		mmr_t	pat         : 40;
25535 	mmr_t	sh_md_dqls_mmr_xbist_l_regval;
25537 		mmr_t	pat         : 40;
25538 		mmr_t	inv         : 1;
25539 		mmr_t	rot         : 1;
25540 		mmr_t	reserved_0  : 22;
25545 	mmr_t	sh_md_dqls_mmr_xbist_l_regval;
25547 		mmr_t	reserved_0  : 22;
25548 		mmr_t	rot         : 1;
25549 		mmr_t	inv         : 1;
25550 		mmr_t	pat         : 40;
25562 	mmr_t	sh_md_dqls_mmr_xbist_err_h_regval;
25564 		mmr_t	pat         : 40;
25565 		mmr_t	val         : 1;
25566 		mmr_t	more        : 1;
25567 		mmr_t	reserved_0  : 22;
25572 	mmr_t	sh_md_dqls_mmr_xbist_err_h_regval;
25574 		mmr_t	reserved_0  : 22;
25575 		mmr_t	more        : 1;
25576 		mmr_t	val         : 1;
25577 		mmr_t	pat         : 40;
25589 	mmr_t	sh_md_dqls_mmr_xbist_err_l_regval;
25591 		mmr_t	pat         : 40;
25592 		mmr_t	val         : 1;
25593 		mmr_t	more        : 1;
25594 		mmr_t	reserved_0  : 22;
25599 	mmr_t	sh_md_dqls_mmr_xbist_err_l_regval;
25601 		mmr_t	reserved_0  : 22;
25602 		mmr_t	more        : 1;
25603 		mmr_t	val         : 1;
25604 		mmr_t	pat         : 40;
25616 	mmr_t	sh_md_dqls_mmr_ybist_h_regval;
25618 		mmr_t	pat         : 40;
25619 		mmr_t	inv         : 1;
25620 		mmr_t	rot         : 1;
25621 		mmr_t	arm         : 1;
25622 		mmr_t	reserved_0  : 21;
25627 	mmr_t	sh_md_dqls_mmr_ybist_h_regval;
25629 		mmr_t	reserved_0  : 21;
25630 		mmr_t	arm         : 1;
25631 		mmr_t	rot         : 1;
25632 		mmr_t	inv         : 1;
25633 		mmr_t	pat         : 40;
25645 	mmr_t	sh_md_dqls_mmr_ybist_l_regval;
25647 		mmr_t	pat         : 40;
25648 		mmr_t	inv         : 1;
25649 		mmr_t	rot         : 1;
25650 		mmr_t	reserved_0  : 22;
25655 	mmr_t	sh_md_dqls_mmr_ybist_l_regval;
25657 		mmr_t	reserved_0  : 22;
25658 		mmr_t	rot         : 1;
25659 		mmr_t	inv         : 1;
25660 		mmr_t	pat         : 40;
25672 	mmr_t	sh_md_dqls_mmr_ybist_err_h_regval;
25674 		mmr_t	pat         : 40;
25675 		mmr_t	val         : 1;
25676 		mmr_t	more        : 1;
25677 		mmr_t	reserved_0  : 22;
25682 	mmr_t	sh_md_dqls_mmr_ybist_err_h_regval;
25684 		mmr_t	reserved_0  : 22;
25685 		mmr_t	more        : 1;
25686 		mmr_t	val         : 1;
25687 		mmr_t	pat         : 40;
25699 	mmr_t	sh_md_dqls_mmr_ybist_err_l_regval;
25701 		mmr_t	pat         : 40;
25702 		mmr_t	val         : 1;
25703 		mmr_t	more        : 1;
25704 		mmr_t	reserved_0  : 22;
25709 	mmr_t	sh_md_dqls_mmr_ybist_err_l_regval;
25711 		mmr_t	reserved_0  : 22;
25712 		mmr_t	more        : 1;
25713 		mmr_t	val         : 1;
25714 		mmr_t	pat         : 40;
25726 	mmr_t	sh_md_dqls_mmr_jnr_debug_regval;
25728 		mmr_t	px          : 1;
25729 		mmr_t	rw          : 1;
25730 		mmr_t	reserved_0  : 62;
25735 	mmr_t	sh_md_dqls_mmr_jnr_debug_regval;
25737 		mmr_t	reserved_0  : 62;
25738 		mmr_t	rw          : 1;
25739 		mmr_t	px          : 1;
25751 	mmr_t	sh_md_dqls_mmr_xamopw_err_regval;
25753 		mmr_t	ssyn        : 8;
25754 		mmr_t	scor        : 1;
25755 		mmr_t	sunc        : 1;
25756 		mmr_t	reserved_0  : 6;
25757 		mmr_t	rsyn        : 8;
25758 		mmr_t	rcor        : 1;
25759 		mmr_t	runc        : 1;
25760 		mmr_t	reserved_1  : 6;
25761 		mmr_t	arm         : 1;
25762 		mmr_t	reserved_2  : 31;
25767 	mmr_t	sh_md_dqls_mmr_xamopw_err_regval;
25769 		mmr_t	reserved_2  : 31;
25770 		mmr_t	arm         : 1;
25771 		mmr_t	reserved_1  : 6;
25772 		mmr_t	runc        : 1;
25773 		mmr_t	rcor        : 1;
25774 		mmr_t	rsyn        : 8;
25775 		mmr_t	reserved_0  : 6;
25776 		mmr_t	sunc        : 1;
25777 		mmr_t	scor        : 1;
25778 		mmr_t	ssyn        : 8;
25790 	mmr_t	sh_md_dqrp_mmr_dir_config_regval;
25792 		mmr_t	sys_size    : 3;
25793 		mmr_t	en_direcc   : 1;
25794 		mmr_t	en_dirpois  : 1;
25795 		mmr_t	reserved_0  : 59;
25800 	mmr_t	sh_md_dqrp_mmr_dir_config_regval;
25802 		mmr_t	reserved_0  : 59;
25803 		mmr_t	en_dirpois  : 1;
25804 		mmr_t	en_direcc   : 1;
25805 		mmr_t	sys_size    : 3;
25817 	mmr_t	sh_md_dqrp_mmr_dir_presvec0_regval;
25819 		mmr_t	vec         : 64;
25824 	mmr_t	sh_md_dqrp_mmr_dir_presvec0_regval;
25826 		mmr_t	vec         : 64;
25838 	mmr_t	sh_md_dqrp_mmr_dir_presvec1_regval;
25840 		mmr_t	vec         : 64;
25845 	mmr_t	sh_md_dqrp_mmr_dir_presvec1_regval;
25847 		mmr_t	vec         : 64;
25859 	mmr_t	sh_md_dqrp_mmr_dir_presvec2_regval;
25861 		mmr_t	vec         : 64;
25866 	mmr_t	sh_md_dqrp_mmr_dir_presvec2_regval;
25868 		mmr_t	vec         : 64;
25880 	mmr_t	sh_md_dqrp_mmr_dir_presvec3_regval;
25882 		mmr_t	vec         : 64;
25887 	mmr_t	sh_md_dqrp_mmr_dir_presvec3_regval;
25889 		mmr_t	vec         : 64;
25901 	mmr_t	sh_md_dqrp_mmr_dir_locvec0_regval;
25903 		mmr_t	vec         : 64;
25908 	mmr_t	sh_md_dqrp_mmr_dir_locvec0_regval;
25910 		mmr_t	vec         : 64;
25922 	mmr_t	sh_md_dqrp_mmr_dir_locvec1_regval;
25924 		mmr_t	vec         : 64;
25929 	mmr_t	sh_md_dqrp_mmr_dir_locvec1_regval;
25931 		mmr_t	vec         : 64;
25943 	mmr_t	sh_md_dqrp_mmr_dir_locvec2_regval;
25945 		mmr_t	vec         : 64;
25950 	mmr_t	sh_md_dqrp_mmr_dir_locvec2_regval;
25952 		mmr_t	vec         : 64;
25964 	mmr_t	sh_md_dqrp_mmr_dir_locvec3_regval;
25966 		mmr_t	vec         : 64;
25971 	mmr_t	sh_md_dqrp_mmr_dir_locvec3_regval;
25973 		mmr_t	vec         : 64;
25985 	mmr_t	sh_md_dqrp_mmr_dir_locvec4_regval;
25987 		mmr_t	vec         : 64;
25992 	mmr_t	sh_md_dqrp_mmr_dir_locvec4_regval;
25994 		mmr_t	vec         : 64;
26006 	mmr_t	sh_md_dqrp_mmr_dir_locvec5_regval;
26008 		mmr_t	vec         : 64;
26013 	mmr_t	sh_md_dqrp_mmr_dir_locvec5_regval;
26015 		mmr_t	vec         : 64;
26027 	mmr_t	sh_md_dqrp_mmr_dir_locvec6_regval;
26029 		mmr_t	vec         : 64;
26034 	mmr_t	sh_md_dqrp_mmr_dir_locvec6_regval;
26036 		mmr_t	vec         : 64;
26048 	mmr_t	sh_md_dqrp_mmr_dir_locvec7_regval;
26050 		mmr_t	vec         : 64;
26055 	mmr_t	sh_md_dqrp_mmr_dir_locvec7_regval;
26057 		mmr_t	vec         : 64;
26069 	mmr_t	sh_md_dqrp_mmr_dir_privec0_regval;
26071 		mmr_t	in          : 14;
26072 		mmr_t	out         : 14;
26073 		mmr_t	reserved_0  : 36;
26078 	mmr_t	sh_md_dqrp_mmr_dir_privec0_regval;
26080 		mmr_t	reserved_0  : 36;
26081 		mmr_t	out         : 14;
26082 		mmr_t	in          : 14;
26094 	mmr_t	sh_md_dqrp_mmr_dir_privec1_regval;
26096 		mmr_t	in          : 14;
26097 		mmr_t	out         : 14;
26098 		mmr_t	reserved_0  : 36;
26103 	mmr_t	sh_md_dqrp_mmr_dir_privec1_regval;
26105 		mmr_t	reserved_0  : 36;
26106 		mmr_t	out         : 14;
26107 		mmr_t	in          : 14;
26119 	mmr_t	sh_md_dqrp_mmr_dir_privec2_regval;
26121 		mmr_t	in          : 14;
26122 		mmr_t	out         : 14;
26123 		mmr_t	reserved_0  : 36;
26128 	mmr_t	sh_md_dqrp_mmr_dir_privec2_regval;
26130 		mmr_t	reserved_0  : 36;
26131 		mmr_t	out         : 14;
26132 		mmr_t	in          : 14;
26144 	mmr_t	sh_md_dqrp_mmr_dir_privec3_regval;
26146 		mmr_t	in          : 14;
26147 		mmr_t	out         : 14;
26148 		mmr_t	reserved_0  : 36;
26153 	mmr_t	sh_md_dqrp_mmr_dir_privec3_regval;
26155 		mmr_t	reserved_0  : 36;
26156 		mmr_t	out         : 14;
26157 		mmr_t	in          : 14;
26169 	mmr_t	sh_md_dqrp_mmr_dir_privec4_regval;
26171 		mmr_t	in          : 14;
26172 		mmr_t	out         : 14;
26173 		mmr_t	reserved_0  : 36;
26178 	mmr_t	sh_md_dqrp_mmr_dir_privec4_regval;
26180 		mmr_t	reserved_0  : 36;
26181 		mmr_t	out         : 14;
26182 		mmr_t	in          : 14;
26194 	mmr_t	sh_md_dqrp_mmr_dir_privec5_regval;
26196 		mmr_t	in          : 14;
26197 		mmr_t	out         : 14;
26198 		mmr_t	reserved_0  : 36;
26203 	mmr_t	sh_md_dqrp_mmr_dir_privec5_regval;
26205 		mmr_t	reserved_0  : 36;
26206 		mmr_t	out         : 14;
26207 		mmr_t	in          : 14;
26219 	mmr_t	sh_md_dqrp_mmr_dir_privec6_regval;
26221 		mmr_t	in          : 14;
26222 		mmr_t	out         : 14;
26223 		mmr_t	reserved_0  : 36;
26228 	mmr_t	sh_md_dqrp_mmr_dir_privec6_regval;
26230 		mmr_t	reserved_0  : 36;
26231 		mmr_t	out         : 14;
26232 		mmr_t	in          : 14;
26244 	mmr_t	sh_md_dqrp_mmr_dir_privec7_regval;
26246 		mmr_t	in          : 14;
26247 		mmr_t	out         : 14;
26248 		mmr_t	reserved_0  : 36;
26253 	mmr_t	sh_md_dqrp_mmr_dir_privec7_regval;
26255 		mmr_t	reserved_0  : 36;
26256 		mmr_t	out         : 14;
26257 		mmr_t	in          : 14;
26269 	mmr_t	sh_md_dqrp_mmr_dir_timer_regval;
26271 		mmr_t	timer_div   : 12;
26272 		mmr_t	timer_en    : 1;
26273 		mmr_t	timer_cur   : 9;
26274 		mmr_t	reserved_0  : 42;
26279 	mmr_t	sh_md_dqrp_mmr_dir_timer_regval;
26281 		mmr_t	reserved_0  : 42;
26282 		mmr_t	timer_cur   : 9;
26283 		mmr_t	timer_en    : 1;
26284 		mmr_t	timer_div   : 12;
26296 	mmr_t	sh_md_dqrp_mmr_piowd_dir_entry_regval;
26298 		mmr_t	dira        : 26;
26299 		mmr_t	dirb        : 26;
26300 		mmr_t	pri         : 3;
26301 		mmr_t	acc         : 3;
26302 		mmr_t	reserved_0  : 6;
26307 	mmr_t	sh_md_dqrp_mmr_piowd_dir_entry_regval;
26309 		mmr_t	reserved_0  : 6;
26310 		mmr_t	acc         : 3;
26311 		mmr_t	pri         : 3;
26312 		mmr_t	dirb        : 26;
26313 		mmr_t	dira        : 26;
26325 	mmr_t	sh_md_dqrp_mmr_piowd_dir_ecc_regval;
26327 		mmr_t	ecca        : 7;
26328 		mmr_t	eccb        : 7;
26329 		mmr_t	reserved_0  : 50;
26334 	mmr_t	sh_md_dqrp_mmr_piowd_dir_ecc_regval;
26336 		mmr_t	reserved_0  : 50;
26337 		mmr_t	eccb        : 7;
26338 		mmr_t	ecca        : 7;
26350 	mmr_t	sh_md_dqrp_mmr_xpiord_xdir_entry_regval;
26352 		mmr_t	dira        : 26;
26353 		mmr_t	dirb        : 26;
26354 		mmr_t	pri         : 3;
26355 		mmr_t	acc         : 3;
26356 		mmr_t	cor         : 1;
26357 		mmr_t	unc         : 1;
26358 		mmr_t	reserved_0  : 4;
26363 	mmr_t	sh_md_dqrp_mmr_xpiord_xdir_entry_regval;
26365 		mmr_t	reserved_0  : 4;
26366 		mmr_t	unc         : 1;
26367 		mmr_t	cor         : 1;
26368 		mmr_t	acc         : 3;
26369 		mmr_t	pri         : 3;
26370 		mmr_t	dirb        : 26;
26371 		mmr_t	dira        : 26;
26383 	mmr_t	sh_md_dqrp_mmr_xpiord_xdir_ecc_regval;
26385 		mmr_t	ecca        : 7;
26386 		mmr_t	eccb        : 7;
26387 		mmr_t	reserved_0  : 50;
26392 	mmr_t	sh_md_dqrp_mmr_xpiord_xdir_ecc_regval;
26394 		mmr_t	reserved_0  : 50;
26395 		mmr_t	eccb        : 7;
26396 		mmr_t	ecca        : 7;
26408 	mmr_t	sh_md_dqrp_mmr_ypiord_ydir_entry_regval;
26410 		mmr_t	dira        : 26;
26411 		mmr_t	dirb        : 26;
26412 		mmr_t	pri         : 3;
26413 		mmr_t	acc         : 3;
26414 		mmr_t	cor         : 1;
26415 		mmr_t	unc         : 1;
26416 		mmr_t	reserved_0  : 4;
26421 	mmr_t	sh_md_dqrp_mmr_ypiord_ydir_entry_regval;
26423 		mmr_t	reserved_0  : 4;
26424 		mmr_t	unc         : 1;
26425 		mmr_t	cor         : 1;
26426 		mmr_t	acc         : 3;
26427 		mmr_t	pri         : 3;
26428 		mmr_t	dirb        : 26;
26429 		mmr_t	dira        : 26;
26441 	mmr_t	sh_md_dqrp_mmr_ypiord_ydir_ecc_regval;
26443 		mmr_t	ecca        : 7;
26444 		mmr_t	eccb        : 7;
26445 		mmr_t	reserved_0  : 50;
26450 	mmr_t	sh_md_dqrp_mmr_ypiord_ydir_ecc_regval;
26452 		mmr_t	reserved_0  : 50;
26453 		mmr_t	eccb        : 7;
26454 		mmr_t	ecca        : 7;
26466 	mmr_t	sh_md_dqrp_mmr_xcerr1_regval;
26468 		mmr_t	grp1        : 36;
26469 		mmr_t	val         : 1;
26470 		mmr_t	more        : 1;
26471 		mmr_t	arm         : 1;
26472 		mmr_t	reserved_0  : 25;
26477 	mmr_t	sh_md_dqrp_mmr_xcerr1_regval;
26479 		mmr_t	reserved_0  : 25;
26480 		mmr_t	arm         : 1;
26481 		mmr_t	more        : 1;
26482 		mmr_t	val         : 1;
26483 		mmr_t	grp1        : 36;
26495 	mmr_t	sh_md_dqrp_mmr_xcerr2_regval;
26497 		mmr_t	grp2        : 36;
26498 		mmr_t	val         : 1;
26499 		mmr_t	more        : 1;
26500 		mmr_t	reserved_0  : 26;
26505 	mmr_t	sh_md_dqrp_mmr_xcerr2_regval;
26507 		mmr_t	reserved_0  : 26;
26508 		mmr_t	more        : 1;
26509 		mmr_t	val         : 1;
26510 		mmr_t	grp2        : 36;
26522 	mmr_t	sh_md_dqrp_mmr_xuerr1_regval;
26524 		mmr_t	grp1        : 36;
26525 		mmr_t	val         : 1;
26526 		mmr_t	more        : 1;
26527 		mmr_t	arm         : 1;
26528 		mmr_t	reserved_0  : 25;
26533 	mmr_t	sh_md_dqrp_mmr_xuerr1_regval;
26535 		mmr_t	reserved_0  : 25;
26536 		mmr_t	arm         : 1;
26537 		mmr_t	more        : 1;
26538 		mmr_t	val         : 1;
26539 		mmr_t	grp1        : 36;
26551 	mmr_t	sh_md_dqrp_mmr_xuerr2_regval;
26553 		mmr_t	grp2        : 36;
26554 		mmr_t	val         : 1;
26555 		mmr_t	more        : 1;
26556 		mmr_t	reserved_0  : 26;
26561 	mmr_t	sh_md_dqrp_mmr_xuerr2_regval;
26563 		mmr_t	reserved_0  : 26;
26564 		mmr_t	more        : 1;
26565 		mmr_t	val         : 1;
26566 		mmr_t	grp2        : 36;
26578 	mmr_t	sh_md_dqrp_mmr_xperr_regval;
26580 		mmr_t	dir         : 26;
26581 		mmr_t	cmd         : 8;
26582 		mmr_t	src         : 14;
26583 		mmr_t	prige       : 1;
26584 		mmr_t	priv        : 1;
26585 		mmr_t	cor         : 1;
26586 		mmr_t	unc         : 1;
26587 		mmr_t	mybit       : 8;
26588 		mmr_t	val         : 1;
26589 		mmr_t	more        : 1;
26590 		mmr_t	arm         : 1;
26591 		mmr_t	reserved_0  : 1;
26596 	mmr_t	sh_md_dqrp_mmr_xperr_regval;
26598 		mmr_t	reserved_0  : 1;
26599 		mmr_t	arm         : 1;
26600 		mmr_t	more        : 1;
26601 		mmr_t	val         : 1;
26602 		mmr_t	mybit       : 8;
26603 		mmr_t	unc         : 1;
26604 		mmr_t	cor         : 1;
26605 		mmr_t	priv        : 1;
26606 		mmr_t	prige       : 1;
26607 		mmr_t	src         : 14;
26608 		mmr_t	cmd         : 8;
26609 		mmr_t	dir         : 26;
26621 	mmr_t	sh_md_dqrp_mmr_ycerr1_regval;
26623 		mmr_t	grp1        : 36;
26624 		mmr_t	val         : 1;
26625 		mmr_t	more        : 1;
26626 		mmr_t	arm         : 1;
26627 		mmr_t	reserved_0  : 25;
26632 	mmr_t	sh_md_dqrp_mmr_ycerr1_regval;
26634 		mmr_t	reserved_0  : 25;
26635 		mmr_t	arm         : 1;
26636 		mmr_t	more        : 1;
26637 		mmr_t	val         : 1;
26638 		mmr_t	grp1        : 36;
26650 	mmr_t	sh_md_dqrp_mmr_ycerr2_regval;
26652 		mmr_t	grp2        : 36;
26653 		mmr_t	val         : 1;
26654 		mmr_t	more        : 1;
26655 		mmr_t	reserved_0  : 26;
26660 	mmr_t	sh_md_dqrp_mmr_ycerr2_regval;
26662 		mmr_t	reserved_0  : 26;
26663 		mmr_t	more        : 1;
26664 		mmr_t	val         : 1;
26665 		mmr_t	grp2        : 36;
26677 	mmr_t	sh_md_dqrp_mmr_yuerr1_regval;
26679 		mmr_t	grp1        : 36;
26680 		mmr_t	val         : 1;
26681 		mmr_t	more        : 1;
26682 		mmr_t	arm         : 1;
26683 		mmr_t	reserved_0  : 25;
26688 	mmr_t	sh_md_dqrp_mmr_yuerr1_regval;
26690 		mmr_t	reserved_0  : 25;
26691 		mmr_t	arm         : 1;
26692 		mmr_t	more        : 1;
26693 		mmr_t	val         : 1;
26694 		mmr_t	grp1        : 36;
26706 	mmr_t	sh_md_dqrp_mmr_yuerr2_regval;
26708 		mmr_t	grp2        : 36;
26709 		mmr_t	val         : 1;
26710 		mmr_t	more        : 1;
26711 		mmr_t	reserved_0  : 26;
26716 	mmr_t	sh_md_dqrp_mmr_yuerr2_regval;
26718 		mmr_t	reserved_0  : 26;
26719 		mmr_t	more        : 1;
26720 		mmr_t	val         : 1;
26721 		mmr_t	grp2        : 36;
26733 	mmr_t	sh_md_dqrp_mmr_yperr_regval;
26735 		mmr_t	dir         : 26;
26736 		mmr_t	cmd         : 8;
26737 		mmr_t	src         : 14;
26738 		mmr_t	prige       : 1;
26739 		mmr_t	priv        : 1;
26740 		mmr_t	cor         : 1;
26741 		mmr_t	unc         : 1;
26742 		mmr_t	mybit       : 8;
26743 		mmr_t	val         : 1;
26744 		mmr_t	more        : 1;
26745 		mmr_t	arm         : 1;
26746 		mmr_t	reserved_0  : 1;
26751 	mmr_t	sh_md_dqrp_mmr_yperr_regval;
26753 		mmr_t	reserved_0  : 1;
26754 		mmr_t	arm         : 1;
26755 		mmr_t	more        : 1;
26756 		mmr_t	val         : 1;
26757 		mmr_t	mybit       : 8;
26758 		mmr_t	unc         : 1;
26759 		mmr_t	cor         : 1;
26760 		mmr_t	priv        : 1;
26761 		mmr_t	prige       : 1;
26762 		mmr_t	src         : 14;
26763 		mmr_t	cmd         : 8;
26764 		mmr_t	dir         : 26;
26776 	mmr_t	sh_md_dqrp_mmr_dir_cmdtrig_regval;
26778 		mmr_t	cmd0        : 8;
26779 		mmr_t	cmd1        : 8;
26780 		mmr_t	cmd2        : 8;
26781 		mmr_t	cmd3        : 8;
26782 		mmr_t	reserved_0  : 32;
26787 	mmr_t	sh_md_dqrp_mmr_dir_cmdtrig_regval;
26789 		mmr_t	reserved_0  : 32;
26790 		mmr_t	cmd3        : 8;
26791 		mmr_t	cmd2        : 8;
26792 		mmr_t	cmd1        : 8;
26793 		mmr_t	cmd0        : 8;
26805 	mmr_t	sh_md_dqrp_mmr_dir_tbltrig_regval;
26807 		mmr_t	src         : 14;
26808 		mmr_t	cmd         : 8;
26809 		mmr_t	acc         : 2;
26810 		mmr_t	prige       : 1;
26811 		mmr_t	dirst       : 9;
26812 		mmr_t	mybit       : 8;
26813 		mmr_t	reserved_0  : 22;
26818 	mmr_t	sh_md_dqrp_mmr_dir_tbltrig_regval;
26820 		mmr_t	reserved_0  : 22;
26821 		mmr_t	mybit       : 8;
26822 		mmr_t	dirst       : 9;
26823 		mmr_t	prige       : 1;
26824 		mmr_t	acc         : 2;
26825 		mmr_t	cmd         : 8;
26826 		mmr_t	src         : 14;
26838 	mmr_t	sh_md_dqrp_mmr_dir_tblmask_regval;
26840 		mmr_t	src         : 14;
26841 		mmr_t	cmd         : 8;
26842 		mmr_t	acc         : 2;
26843 		mmr_t	prige       : 1;
26844 		mmr_t	dirst       : 9;
26845 		mmr_t	mybit       : 8;
26846 		mmr_t	reserved_0  : 22;
26851 	mmr_t	sh_md_dqrp_mmr_dir_tblmask_regval;
26853 		mmr_t	reserved_0  : 22;
26854 		mmr_t	mybit       : 8;
26855 		mmr_t	dirst       : 9;
26856 		mmr_t	prige       : 1;
26857 		mmr_t	acc         : 2;
26858 		mmr_t	cmd         : 8;
26859 		mmr_t	src         : 14;
26871 	mmr_t	sh_md_dqrp_mmr_xbist_h_regval;
26873 		mmr_t	pat         : 32;
26874 		mmr_t	reserved_0  : 8;
26875 		mmr_t	inv         : 1;
26876 		mmr_t	rot         : 1;
26877 		mmr_t	arm         : 1;
26878 		mmr_t	reserved_1  : 21;
26883 	mmr_t	sh_md_dqrp_mmr_xbist_h_regval;
26885 		mmr_t	reserved_1  : 21;
26886 		mmr_t	arm         : 1;
26887 		mmr_t	rot         : 1;
26888 		mmr_t	inv         : 1;
26889 		mmr_t	reserved_0  : 8;
26890 		mmr_t	pat         : 32;
26902 	mmr_t	sh_md_dqrp_mmr_xbist_l_regval;
26904 		mmr_t	pat         : 32;
26905 		mmr_t	reserved_0  : 8;
26906 		mmr_t	inv         : 1;
26907 		mmr_t	rot         : 1;
26908 		mmr_t	reserved_1  : 22;
26913 	mmr_t	sh_md_dqrp_mmr_xbist_l_regval;
26915 		mmr_t	reserved_1  : 22;
26916 		mmr_t	rot         : 1;
26917 		mmr_t	inv         : 1;
26918 		mmr_t	reserved_0  : 8;
26919 		mmr_t	pat         : 32;
26931 	mmr_t	sh_md_dqrp_mmr_xbist_err_h_regval;
26933 		mmr_t	pat         : 32;
26934 		mmr_t	reserved_0  : 8;
26935 		mmr_t	val         : 1;
26936 		mmr_t	more        : 1;
26937 		mmr_t	reserved_1  : 22;
26942 	mmr_t	sh_md_dqrp_mmr_xbist_err_h_regval;
26944 		mmr_t	reserved_1  : 22;
26945 		mmr_t	more        : 1;
26946 		mmr_t	val         : 1;
26947 		mmr_t	reserved_0  : 8;
26948 		mmr_t	pat         : 32;
26960 	mmr_t	sh_md_dqrp_mmr_xbist_err_l_regval;
26962 		mmr_t	pat         : 32;
26963 		mmr_t	reserved_0  : 8;
26964 		mmr_t	val         : 1;
26965 		mmr_t	more        : 1;
26966 		mmr_t	reserved_1  : 22;
26971 	mmr_t	sh_md_dqrp_mmr_xbist_err_l_regval;
26973 		mmr_t	reserved_1  : 22;
26974 		mmr_t	more        : 1;
26975 		mmr_t	val         : 1;
26976 		mmr_t	reserved_0  : 8;
26977 		mmr_t	pat         : 32;
26989 	mmr_t	sh_md_dqrp_mmr_ybist_h_regval;
26991 		mmr_t	pat         : 32;
26992 		mmr_t	reserved_0  : 8;
26993 		mmr_t	inv         : 1;
26994 		mmr_t	rot         : 1;
26995 		mmr_t	arm         : 1;
26996 		mmr_t	reserved_1  : 21;
27001 	mmr_t	sh_md_dqrp_mmr_ybist_h_regval;
27003 		mmr_t	reserved_1  : 21;
27004 		mmr_t	arm         : 1;
27005 		mmr_t	rot         : 1;
27006 		mmr_t	inv         : 1;
27007 		mmr_t	reserved_0  : 8;
27008 		mmr_t	pat         : 32;
27020 	mmr_t	sh_md_dqrp_mmr_ybist_l_regval;
27022 		mmr_t	pat         : 32;
27023 		mmr_t	reserved_0  : 8;
27024 		mmr_t	inv         : 1;
27025 		mmr_t	rot         : 1;
27026 		mmr_t	reserved_1  : 22;
27031 	mmr_t	sh_md_dqrp_mmr_ybist_l_regval;
27033 		mmr_t	reserved_1  : 22;
27034 		mmr_t	rot         : 1;
27035 		mmr_t	inv         : 1;
27036 		mmr_t	reserved_0  : 8;
27037 		mmr_t	pat         : 32;
27049 	mmr_t	sh_md_dqrp_mmr_ybist_err_h_regval;
27051 		mmr_t	pat         : 32;
27052 		mmr_t	reserved_0  : 8;
27053 		mmr_t	val         : 1;
27054 		mmr_t	more        : 1;
27055 		mmr_t	reserved_1  : 22;
27060 	mmr_t	sh_md_dqrp_mmr_ybist_err_h_regval;
27062 		mmr_t	reserved_1  : 22;
27063 		mmr_t	more        : 1;
27064 		mmr_t	val         : 1;
27065 		mmr_t	reserved_0  : 8;
27066 		mmr_t	pat         : 32;
27078 	mmr_t	sh_md_dqrp_mmr_ybist_err_l_regval;
27080 		mmr_t	pat         : 32;
27081 		mmr_t	reserved_0  : 8;
27082 		mmr_t	val         : 1;
27083 		mmr_t	more        : 1;
27084 		mmr_t	reserved_1  : 22;
27089 	mmr_t	sh_md_dqrp_mmr_ybist_err_l_regval;
27091 		mmr_t	reserved_1  : 22;
27092 		mmr_t	more        : 1;
27093 		mmr_t	val         : 1;
27094 		mmr_t	reserved_0  : 8;
27095 		mmr_t	pat         : 32;
27107 	mmr_t	sh_md_dqrs_mmr_xbist_h_regval;
27109 		mmr_t	pat         : 40;
27110 		mmr_t	inv         : 1;
27111 		mmr_t	rot         : 1;
27112 		mmr_t	arm         : 1;
27113 		mmr_t	reserved_0  : 21;
27118 	mmr_t	sh_md_dqrs_mmr_xbist_h_regval;
27120 		mmr_t	reserved_0  : 21;
27121 		mmr_t	arm         : 1;
27122 		mmr_t	rot         : 1;
27123 		mmr_t	inv         : 1;
27124 		mmr_t	pat         : 40;
27136 	mmr_t	sh_md_dqrs_mmr_xbist_l_regval;
27138 		mmr_t	pat         : 40;
27139 		mmr_t	inv         : 1;
27140 		mmr_t	rot         : 1;
27141 		mmr_t	reserved_0  : 22;
27146 	mmr_t	sh_md_dqrs_mmr_xbist_l_regval;
27148 		mmr_t	reserved_0  : 22;
27149 		mmr_t	rot         : 1;
27150 		mmr_t	inv         : 1;
27151 		mmr_t	pat         : 40;
27163 	mmr_t	sh_md_dqrs_mmr_xbist_err_h_regval;
27165 		mmr_t	pat         : 40;
27166 		mmr_t	val         : 1;
27167 		mmr_t	more        : 1;
27168 		mmr_t	reserved_0  : 22;
27173 	mmr_t	sh_md_dqrs_mmr_xbist_err_h_regval;
27175 		mmr_t	reserved_0  : 22;
27176 		mmr_t	more        : 1;
27177 		mmr_t	val         : 1;
27178 		mmr_t	pat         : 40;
27190 	mmr_t	sh_md_dqrs_mmr_xbist_err_l_regval;
27192 		mmr_t	pat         : 40;
27193 		mmr_t	val         : 1;
27194 		mmr_t	more        : 1;
27195 		mmr_t	reserved_0  : 22;
27200 	mmr_t	sh_md_dqrs_mmr_xbist_err_l_regval;
27202 		mmr_t	reserved_0  : 22;
27203 		mmr_t	more        : 1;
27204 		mmr_t	val         : 1;
27205 		mmr_t	pat         : 40;
27217 	mmr_t	sh_md_dqrs_mmr_ybist_h_regval;
27219 		mmr_t	pat         : 40;
27220 		mmr_t	inv         : 1;
27221 		mmr_t	rot         : 1;
27222 		mmr_t	arm         : 1;
27223 		mmr_t	reserved_0  : 21;
27228 	mmr_t	sh_md_dqrs_mmr_ybist_h_regval;
27230 		mmr_t	reserved_0  : 21;
27231 		mmr_t	arm         : 1;
27232 		mmr_t	rot         : 1;
27233 		mmr_t	inv         : 1;
27234 		mmr_t	pat         : 40;
27246 	mmr_t	sh_md_dqrs_mmr_ybist_l_regval;
27248 		mmr_t	pat         : 40;
27249 		mmr_t	inv         : 1;
27250 		mmr_t	rot         : 1;
27251 		mmr_t	reserved_0  : 22;
27256 	mmr_t	sh_md_dqrs_mmr_ybist_l_regval;
27258 		mmr_t	reserved_0  : 22;
27259 		mmr_t	rot         : 1;
27260 		mmr_t	inv         : 1;
27261 		mmr_t	pat         : 40;
27273 	mmr_t	sh_md_dqrs_mmr_ybist_err_h_regval;
27275 		mmr_t	pat         : 40;
27276 		mmr_t	val         : 1;
27277 		mmr_t	more        : 1;
27278 		mmr_t	reserved_0  : 22;
27283 	mmr_t	sh_md_dqrs_mmr_ybist_err_h_regval;
27285 		mmr_t	reserved_0  : 22;
27286 		mmr_t	more        : 1;
27287 		mmr_t	val         : 1;
27288 		mmr_t	pat         : 40;
27300 	mmr_t	sh_md_dqrs_mmr_ybist_err_l_regval;
27302 		mmr_t	pat         : 40;
27303 		mmr_t	val         : 1;
27304 		mmr_t	more        : 1;
27305 		mmr_t	reserved_0  : 22;
27310 	mmr_t	sh_md_dqrs_mmr_ybist_err_l_regval;
27312 		mmr_t	reserved_0  : 22;
27313 		mmr_t	more        : 1;
27314 		mmr_t	val         : 1;
27315 		mmr_t	pat         : 40;
27327 	mmr_t	sh_md_dqrs_mmr_jnr_debug_regval;
27329 		mmr_t	px          : 1;
27330 		mmr_t	rw          : 1;
27331 		mmr_t	reserved_0  : 62;
27336 	mmr_t	sh_md_dqrs_mmr_jnr_debug_regval;
27338 		mmr_t	reserved_0  : 62;
27339 		mmr_t	rw          : 1;
27340 		mmr_t	px          : 1;
27352 	mmr_t	sh_md_dqrs_mmr_yamopw_err_regval;
27354 		mmr_t	ssyn        : 8;
27355 		mmr_t	scor        : 1;
27356 		mmr_t	sunc        : 1;
27357 		mmr_t	reserved_0  : 6;
27358 		mmr_t	rsyn        : 8;
27359 		mmr_t	rcor        : 1;
27360 		mmr_t	runc        : 1;
27361 		mmr_t	reserved_1  : 6;
27362 		mmr_t	arm         : 1;
27363 		mmr_t	reserved_2  : 31;
27368 	mmr_t	sh_md_dqrs_mmr_yamopw_err_regval;
27370 		mmr_t	reserved_2  : 31;
27371 		mmr_t	arm         : 1;
27372 		mmr_t	reserved_1  : 6;
27373 		mmr_t	runc        : 1;
27374 		mmr_t	rcor        : 1;
27375 		mmr_t	rsyn        : 8;
27376 		mmr_t	reserved_0  : 6;
27377 		mmr_t	sunc        : 1;
27378 		mmr_t	scor        : 1;
27379 		mmr_t	ssyn        : 8;