Lines Matching refs:TGA_WRITE_REG
484 TGA_WRITE_REG(TGA_VALID_VIDEO | TGA_VALID_BLANK, TGA_VALID_REG); in tgafb_set_par()
491 TGA_WRITE_REG(deep_presets[fb_info.tga_type], TGA_DEEP_REG); in tgafb_set_par()
497 TGA_WRITE_REG(rasterop_presets[fb_info.tga_type], TGA_RASTEROP_REG); in tgafb_set_par()
498 TGA_WRITE_REG(mode_presets[fb_info.tga_type], TGA_MODE_REG); in tgafb_set_par()
499 TGA_WRITE_REG(base_addr_presets[fb_info.tga_type], TGA_BASE_ADDR_REG); in tgafb_set_par()
505 TGA_WRITE_REG(0xffffffff, TGA_PLANEMASK_REG); in tgafb_set_par()
506 TGA_WRITE_REG(0xffffffff, TGA_PIXELMASK_REG); in tgafb_set_par()
507 TGA_WRITE_REG(0x12345678, TGA_BLOCK_COLOR0_REG); in tgafb_set_par()
508 TGA_WRITE_REG(0x12345678, TGA_BLOCK_COLOR1_REG); in tgafb_set_par()
511 TGA_WRITE_REG(par->htimings, TGA_HORIZ_REG); in tgafb_set_par()
512 TGA_WRITE_REG(par->vtimings, TGA_VERT_REG); in tgafb_set_par()
527 TGA_WRITE_REG(BT485_DATA_PAL, TGA_RAMDAC_SETUP_REG); in tgafb_set_par()
531 TGA_WRITE_REG(default_red[j]|(BT485_DATA_PAL<<8), TGA_RAMDAC_REG); in tgafb_set_par()
532 TGA_WRITE_REG(default_grn[j]|(BT485_DATA_PAL<<8), TGA_RAMDAC_REG); in tgafb_set_par()
533 TGA_WRITE_REG(default_blu[j]|(BT485_DATA_PAL<<8), TGA_RAMDAC_REG); in tgafb_set_par()
539 TGA_WRITE_REG(0x55|(BT485_DATA_PAL<<8), TGA_RAMDAC_REG); in tgafb_set_par()
540 TGA_WRITE_REG(0x00|(BT485_DATA_PAL<<8), TGA_RAMDAC_REG); in tgafb_set_par()
541 TGA_WRITE_REG(0x00|(BT485_DATA_PAL<<8), TGA_RAMDAC_REG); in tgafb_set_par()
542 TGA_WRITE_REG(0x00|(BT485_DATA_PAL<<8), TGA_RAMDAC_REG); in tgafb_set_par()
565 TGA_WRITE_REG((BT463_PALETTE<<2), TGA_RAMDAC_REG); in tgafb_set_par()
569 TGA_WRITE_REG(default_red[j]|(BT463_PALETTE<<10), TGA_RAMDAC_REG); in tgafb_set_par()
570 TGA_WRITE_REG(default_grn[j]|(BT463_PALETTE<<10), TGA_RAMDAC_REG); in tgafb_set_par()
571 TGA_WRITE_REG(default_blu[j]|(BT463_PALETTE<<10), TGA_RAMDAC_REG); in tgafb_set_par()
574 TGA_WRITE_REG(0x55|(BT463_PALETTE<<10), TGA_RAMDAC_REG); in tgafb_set_par()
575 TGA_WRITE_REG(0x00|(BT463_PALETTE<<10), TGA_RAMDAC_REG); in tgafb_set_par()
576 TGA_WRITE_REG(0x00|(BT463_PALETTE<<10), TGA_RAMDAC_REG); in tgafb_set_par()
577 TGA_WRITE_REG(0x00|(BT463_PALETTE<<10), TGA_RAMDAC_REG); in tgafb_set_par()
583 TGA_WRITE_REG(0x01, TGA_INTR_STAT_REG); in tgafb_set_par()
587 TGA_WRITE_REG(0x01, TGA_INTR_STAT_REG); in tgafb_set_par()
590 TGA_WRITE_REG((BT463_REG_ACC<<2), TGA_RAMDAC_SETUP_REG); in tgafb_set_par()
593 TGA_WRITE_REG(0x00|(BT463_REG_ACC<<10), TGA_RAMDAC_REG); in tgafb_set_par()
594 TGA_WRITE_REG(0x01|(BT463_REG_ACC<<10), TGA_RAMDAC_REG); in tgafb_set_par()
595 TGA_WRITE_REG(0x80|(BT463_REG_ACC<<10), TGA_RAMDAC_REG); in tgafb_set_par()
602 TGA_WRITE_REG(TGA_VALID_VIDEO, TGA_VALID_REG); in tgafb_set_par()
617 TGA_WRITE_REG(!r, TGA_CLOCK_REG); in tgafb_set_pll()
629 TGA_WRITE_REG(shift & 1, TGA_CLOCK_REG); in tgafb_set_pll()
630 TGA_WRITE_REG(shift >> 1, TGA_CLOCK_REG); in tgafb_set_pll()
633 TGA_WRITE_REG(0, TGA_CLOCK_REG); in tgafb_set_pll()
637 TGA_WRITE_REG(0, TGA_CLOCK_REG); in tgafb_set_pll()
638 TGA_WRITE_REG(0, TGA_CLOCK_REG); in tgafb_set_pll()
641 TGA_WRITE_REG(1, TGA_CLOCK_REG); in tgafb_set_pll()
642 TGA_WRITE_REG(0, TGA_CLOCK_REG); in tgafb_set_pll()
645 TGA_WRITE_REG(0, TGA_CLOCK_REG); in tgafb_set_pll()
646 TGA_WRITE_REG(1, TGA_CLOCK_REG); in tgafb_set_pll()
649 TGA_WRITE_REG(1, TGA_CLOCK_REG); in tgafb_set_pll()
650 TGA_WRITE_REG(0, TGA_CLOCK_REG); in tgafb_set_pll()
651 TGA_WRITE_REG(0, TGA_CLOCK_REG); in tgafb_set_pll()
652 TGA_WRITE_REG(1, TGA_CLOCK_REG); in tgafb_set_pll()
653 TGA_WRITE_REG(0, TGA_CLOCK_REG); in tgafb_set_pll()
654 TGA_WRITE_REG(1, TGA_CLOCK_REG); in tgafb_set_pll()
682 TGA_WRITE_REG((vm >> r) & 1, TGA_CLOCK_REG); in tgafb_set_pll()
685 TGA_WRITE_REG((va >> r) & 1, TGA_CLOCK_REG); in tgafb_set_pll()
688 TGA_WRITE_REG((vr >> r) & 1, TGA_CLOCK_REG); in tgafb_set_pll()
690 TGA_WRITE_REG(((vr >> 7) & 1)|2, TGA_CLOCK_REG); in tgafb_set_pll()
726 TGA_WRITE_REG(BT485_DATA_PAL, TGA_RAMDAC_SETUP_REG); in tgafb_setcolreg()
727 TGA_WRITE_REG(red|(BT485_DATA_PAL<<8),TGA_RAMDAC_REG); in tgafb_setcolreg()
728 TGA_WRITE_REG(green|(BT485_DATA_PAL<<8),TGA_RAMDAC_REG); in tgafb_setcolreg()
729 TGA_WRITE_REG(blue|(BT485_DATA_PAL<<8),TGA_RAMDAC_REG); in tgafb_setcolreg()
768 TGA_WRITE_REG((BT463_PALETTE<<2), TGA_RAMDAC_REG); in tgafb_update_palette()
771 TGA_WRITE_REG(palette[i].red|(BT463_PALETTE<<10), TGA_RAMDAC_REG); in tgafb_update_palette()
772 TGA_WRITE_REG(palette[i].green|(BT463_PALETTE<<10), TGA_RAMDAC_REG); in tgafb_update_palette()
773 TGA_WRITE_REG(palette[i].blue|(BT463_PALETTE<<10), TGA_RAMDAC_REG); in tgafb_update_palette()
795 TGA_WRITE_REG(vhcr & 0xbfffffff, TGA_HORIZ_REG); in tgafb_blank()
796 TGA_WRITE_REG(vvcr & 0xbfffffff, TGA_VERT_REG); in tgafb_blank()
799 TGA_WRITE_REG(vvvr | TGA_VALID_VIDEO, TGA_VALID_REG); in tgafb_blank()
803 TGA_WRITE_REG(vvvr | TGA_VALID_VIDEO | TGA_VALID_BLANK, TGA_VALID_REG); in tgafb_blank()
807 TGA_WRITE_REG(vvcr | 0x40000000, TGA_VERT_REG); in tgafb_blank()
808 TGA_WRITE_REG(vvvr | TGA_VALID_BLANK, TGA_VALID_REG); in tgafb_blank()
813 TGA_WRITE_REG(vhcr | 0x40000000, TGA_HORIZ_REG); in tgafb_blank()
814 TGA_WRITE_REG(vvvr | TGA_VALID_BLANK, TGA_VALID_REG); in tgafb_blank()
819 TGA_WRITE_REG(vhcr | 0x40000000, TGA_HORIZ_REG); in tgafb_blank()
820 TGA_WRITE_REG(vvcr | 0x40000000, TGA_VERT_REG); in tgafb_blank()
821 TGA_WRITE_REG(vvvr | TGA_VALID_BLANK, TGA_VALID_REG); in tgafb_blank()