Lines Matching refs:OUTREG
576 #define OUTREG(addr,val) writel(val, (rinfo->mmio_base)+addr) macro
581 OUTREG(CLOCK_CNTL_DATA, val); \
597 OUTREG(addr, _tmp); \
772 OUTREG(RBBM_SOFT_RESET, (rbbm_soft_reset | in _radeon_engine_reset()
777 OUTREG(RBBM_SOFT_RESET, 0); in _radeon_engine_reset()
779 OUTREG(RB2D_DSTCACHE_MODE, tmp | (1 << 17)); /* FIXME */ in _radeon_engine_reset()
781 OUTREG(RBBM_SOFT_RESET, rbbm_soft_reset | in _radeon_engine_reset()
790 OUTREG(RBBM_SOFT_RESET, rbbm_soft_reset & (u32) in _radeon_engine_reset()
801 OUTREG(HOST_PATH_CNTL, host_path_cntl | HDP_SOFT_RESET); in _radeon_engine_reset()
803 OUTREG(HOST_PATH_CNTL, host_path_cntl); in _radeon_engine_reset()
806 OUTREG(RBBM_SOFT_RESET, rbbm_soft_reset); in _radeon_engine_reset()
808 OUTREG(CLOCK_CNTL_INDEX, clock_cntl_index); in _radeon_engine_reset()
1286 OUTREG(CRTC2_GEN_CNTL, save_crtc2_gen_cntl | CRTC2_DISP_REQ_EN_B); in radeon_fixup_apertures()
1291 OUTREG(CRTC_EXT_CNTL, save_crtc_ext_cntl | CRTC_DISPLAY_DIS); in radeon_fixup_apertures()
1292 OUTREG(CRTC_GEN_CNTL, save_crtc_gen_cntl | CRTC_DISP_REQ_EN_B); in radeon_fixup_apertures()
1300 OUTREG(MC_FB_LOCATION, in radeon_fixup_apertures()
1304 OUTREG(MC_FB_LOCATION, 0x7fff0000); in radeon_fixup_apertures()
1316 OUTREG(MC_AGP_LOCATION, 0xffff0000 | (agp_base >> 16)); in radeon_fixup_apertures()
1318 OUTREG(MC_AGP_LOCATION, 0xffffe000); in radeon_fixup_apertures()
1325 OUTREG(DISPLAY_BASE_ADDR, aper_base); in radeon_fixup_apertures()
1327 OUTREG(CRTC2_DISPLAY_BASE_ADDR, aper_base); in radeon_fixup_apertures()
1329 OUTREG(DISPLAY_BASE_ADDR, 0); in radeon_fixup_apertures()
1331 OUTREG(CRTC2_DISPLAY_BASE_ADDR, 0); in radeon_fixup_apertures()
1336 OUTREG(CRTC_GEN_CNTL, save_crtc_gen_cntl); in radeon_fixup_apertures()
1337 OUTREG(CRTC_EXT_CNTL, save_crtc_ext_cntl); in radeon_fixup_apertures()
1339 OUTREG(CRTC2_GEN_CNTL, save_crtc2_gen_cntl); in radeon_fixup_apertures()
1983 OUTREG(RB3D_CNTL, 0); in radeon_engine_init()
1989 OUTREG(RB2D_DSTCACHE_MODE, 0); in radeon_engine_init()
1997 OUTREG(DEFAULT_PITCH_OFFSET, (rinfo->pitch << 0x16) | in radeon_engine_init()
1999 OUTREG(DST_PITCH_OFFSET, (rinfo->pitch << 0x16) | (rinfo->fb_local_base >> 10)); in radeon_engine_init()
2000 OUTREG(SRC_PITCH_OFFSET, (rinfo->pitch << 0x16) | (rinfo->fb_local_base >> 10)); in radeon_engine_init()
2009 OUTREG(DEFAULT_SC_BOTTOM_RIGHT, (DEFAULT_SC_RIGHT_MAX | in radeon_engine_init()
2016 OUTREG(DP_GUI_MASTER_CNTL, (rinfo->dp_gui_master_cntl | in radeon_engine_init()
2023 OUTREG(DST_LINE_START, 0); in radeon_engine_init()
2024 OUTREG(DST_LINE_END, 0); in radeon_engine_init()
2027 OUTREG(DP_BRUSH_FRGD_CLR, 0xffffffff); in radeon_engine_init()
2028 OUTREG(DP_BRUSH_BKGD_CLR, 0x00000000); in radeon_engine_init()
2031 OUTREG(DP_SRC_FRGD_CLR, 0xffffffff); in radeon_engine_init()
2032 OUTREG(DP_SRC_BKGD_CLR, 0x00000000); in radeon_engine_init()
2035 OUTREG(DP_WRITE_MSK, 0xffffffff); in radeon_engine_init()
2583 OUTREG(CRTC_OFFSET, ((var->yoffset * var->xres_virtual + var->xoffset) in radeonfb_pan_display()
2627 OUTREG(LVDS_GEN_CNTL, tmp); in radeonfb_ioctl()
2641 OUTREG(CRTC_EXT_CNTL, tmp); in radeonfb_ioctl()
2774 OUTREG(LVDS_GEN_CNTL, val_lvds); in radeonfb_blank()
2777 OUTREG(FP_GEN_CNTL, val_dfp); in radeonfb_blank()
2781 OUTREG(CRTC_EXT_CNTL, val); in radeonfb_blank()
2852 OUTREG(DAC_CNTL2, dac_cntl2); in radeon_setcolreg()
2866 OUTREG(PALETTE_DATA, (rinfo->palette[regno>>1].red << 16) | in radeon_setcolreg()
2874 OUTREG(PALETTE_DATA, (red << 16) | (green << 8) | blue); in radeon_setcolreg()
3377 OUTREG(common_regs_m6[i].reg, common_regs_m6[i].val); in radeon_write_mode()
3380 OUTREG(common_regs[i].reg, common_regs[i].val); in radeon_write_mode()
3383 OUTREG(CRTC_GEN_CNTL, mode->crtc_gen_cntl); in radeon_write_mode()
3386 OUTREG(CRTC_MORE_CNTL, mode->crtc_more_cntl); in radeon_write_mode()
3388 OUTREG(CRTC_H_TOTAL_DISP, mode->crtc_h_total_disp); in radeon_write_mode()
3389 OUTREG(CRTC_H_SYNC_STRT_WID, mode->crtc_h_sync_strt_wid); in radeon_write_mode()
3390 OUTREG(CRTC_V_TOTAL_DISP, mode->crtc_v_total_disp); in radeon_write_mode()
3391 OUTREG(CRTC_V_SYNC_STRT_WID, mode->crtc_v_sync_strt_wid); in radeon_write_mode()
3392 OUTREG(CRTC_OFFSET, 0); in radeon_write_mode()
3393 OUTREG(CRTC_OFFSET_CNTL, 0); in radeon_write_mode()
3394 OUTREG(CRTC_PITCH, mode->crtc_pitch); in radeon_write_mode()
3395 OUTREG(SURFACE_CNTL, mode->surface_cntl); in radeon_write_mode()
3404 OUTREG(DDA_CONFIG, mode->dda_config); in radeon_write_mode()
3405 OUTREG(DDA_ON_OFF, mode->dda_on_off); in radeon_write_mode()
3409 OUTREG(FP_CRTC_H_TOTAL_DISP, mode->fp_crtc_h_total_disp); in radeon_write_mode()
3410 OUTREG(FP_CRTC_V_TOTAL_DISP, mode->fp_crtc_v_total_disp); in radeon_write_mode()
3411 OUTREG(FP_H_SYNC_STRT_WID, mode->fp_h_sync_strt_wid); in radeon_write_mode()
3412 OUTREG(FP_V_SYNC_STRT_WID, mode->fp_v_sync_strt_wid); in radeon_write_mode()
3413 OUTREG(FP_HORZ_STRETCH, mode->fp_horz_stretch); in radeon_write_mode()
3414 OUTREG(FP_VERT_STRETCH, mode->fp_vert_stretch); in radeon_write_mode()
3415 OUTREG(FP_GEN_CNTL, mode->fp_gen_cntl); in radeon_write_mode()
3416 OUTREG(TMDS_CRC, mode->tmds_crc); in radeon_write_mode()
3417 OUTREG(TMDS_TRANSMITTER_CNTL, mode->tmds_transmitter_cntl); in radeon_write_mode()
3427 OUTREG(LVDS_GEN_CNTL, mode->lvds_gen_cntl); in radeon_write_mode()
3431 OUTREG(LVDS_GEN_CNTL, mode->lvds_gen_cntl); in radeon_write_mode()
3433 OUTREG(LVDS_GEN_CNTL, mode->lvds_gen_cntl | in radeon_write_mode()
3436 OUTREG(LVDS_GEN_CNTL, mode->lvds_gen_cntl); in radeon_write_mode()
3492 OUTREG(LVDS_GEN_CNTL, lvds_gen_cntl); in radeon_set_backlight_enable()
3496 OUTREG(LVDS_GEN_CNTL, lvds_gen_cntl); in radeon_set_backlight_enable()
3508 OUTREG(LVDS_GEN_CNTL, lvds_gen_cntl); in radeon_set_backlight_enable()
3513 OUTREG(LVDS_GEN_CNTL, lvds_gen_cntl); in radeon_set_backlight_enable()
3541 OUTREG( MC_IND_INDEX, indx | MC_IND_INDEX__MC_IND_WR_EN); in OUTMC()
3542 OUTREG( MC_IND_DATA, value); in OUTMC()
3547 OUTREG( MC_IND_INDEX, indx); in INMC()
3604 OUTREG(SURFACE_CNTL, rinfo->save_regs[29]); in radeon_pm_restore_regs()
3605 OUTREG(MC_FB_LOCATION, rinfo->save_regs[30]); in radeon_pm_restore_regs()
3606 OUTREG(DISPLAY_BASE_ADDR, rinfo->save_regs[31]); in radeon_pm_restore_regs()
3607 OUTREG(MC_AGP_LOCATION, rinfo->save_regs[32]); in radeon_pm_restore_regs()
3608 OUTREG(CRTC2_DISPLAY_BASE_ADDR, rinfo->save_regs[33]); in radeon_pm_restore_regs()
3610 OUTREG(DISP_MISC_CNTL, rinfo->save_regs[9]); in radeon_pm_restore_regs()
3611 OUTREG(DISP_PWR_MAN, rinfo->save_regs[10]); in radeon_pm_restore_regs()
3612 OUTREG(LVDS_GEN_CNTL, rinfo->save_regs[11]); in radeon_pm_restore_regs()
3613 OUTREG(LVDS_PLL_CNTL,rinfo->save_regs[12]); in radeon_pm_restore_regs()
3614 OUTREG(TV_DAC_CNTL, rinfo->save_regs[13]); in radeon_pm_restore_regs()
3615 OUTREG(BUS_CNTL1, rinfo->save_regs[14]); in radeon_pm_restore_regs()
3616 OUTREG(CRTC_OFFSET_CNTL, rinfo->save_regs[15]); in radeon_pm_restore_regs()
3617 OUTREG(AGP_CNTL, rinfo->save_regs[16]); in radeon_pm_restore_regs()
3618 OUTREG(CRTC_GEN_CNTL, rinfo->save_regs[17]); in radeon_pm_restore_regs()
3619 OUTREG(CRTC2_GEN_CNTL, rinfo->save_regs[18]); in radeon_pm_restore_regs()
3624 OUTREG(GPIOPAD_A, rinfo->save_regs[19]); in radeon_pm_restore_regs()
3625 OUTREG(GPIOPAD_EN, rinfo->save_regs[20]); in radeon_pm_restore_regs()
3626 OUTREG(GPIOPAD_MASK, rinfo->save_regs[21]); in radeon_pm_restore_regs()
3627 OUTREG(ZV_LCDPAD_A, rinfo->save_regs[22]); in radeon_pm_restore_regs()
3628 OUTREG(ZV_LCDPAD_EN, rinfo->save_regs[23]); in radeon_pm_restore_regs()
3629 OUTREG(ZV_LCDPAD_MASK, rinfo->save_regs[24]); in radeon_pm_restore_regs()
3630 OUTREG(GPIO_VGA_DDC, rinfo->save_regs[25]); in radeon_pm_restore_regs()
3631 OUTREG(GPIO_DVI_DDC, rinfo->save_regs[26]); in radeon_pm_restore_regs()
3632 OUTREG(GPIO_MONID, rinfo->save_regs[27]); in radeon_pm_restore_regs()
3633 OUTREG(GPIO_CRT2_DDC, rinfo->save_regs[28]); in radeon_pm_restore_regs()
3638 OUTREG(GPIOPAD_MASK, 0x0001ffff); in radeon_pm_disable_iopad()
3639 OUTREG(GPIOPAD_EN, 0x00000400); in radeon_pm_disable_iopad()
3640 OUTREG(GPIOPAD_A, 0x00000000); in radeon_pm_disable_iopad()
3641 OUTREG(ZV_LCDPAD_MASK, 0x00000000); in radeon_pm_disable_iopad()
3642 OUTREG(ZV_LCDPAD_EN, 0x00000000); in radeon_pm_disable_iopad()
3643 OUTREG(ZV_LCDPAD_A, 0x00000000); in radeon_pm_disable_iopad()
3644 OUTREG(GPIO_VGA_DDC, 0x00030000); in radeon_pm_disable_iopad()
3645 OUTREG(GPIO_DVI_DDC, 0x00000000); in radeon_pm_disable_iopad()
3646 OUTREG(GPIO_MONID, 0x00030000); in radeon_pm_disable_iopad()
3647 OUTREG(GPIO_CRT2_DDC, 0x00000000); in radeon_pm_disable_iopad()
3679 OUTREG(BUS_CNTL1, reg); in radeon_pm_low_current()
3693 OUTREG(TV_DAC_CNTL, reg); in radeon_pm_low_current()
3697 OUTREG(TMDS_TRANSMITTER_CNTL, reg); in radeon_pm_low_current()
3701 OUTREG(DAC_CNTL, reg); in radeon_pm_low_current()
3705 OUTREG(DAC_CNTL2, reg); in radeon_pm_low_current()
3709 OUTREG(TV_DAC_CNTL, reg); in radeon_pm_low_current()
3832 OUTREG(BUS_CNTL1, INREG(BUS_CNTL1) | BUS_CNTL1__AGPCLK_VALID); in radeon_pm_setup_for_suspend()
3834 OUTREG(BUS_CNTL1, in radeon_pm_setup_for_suspend()
3837 OUTREG(CRTC_OFFSET_CNTL, (INREG(CRTC_OFFSET_CNTL) & ~CRTC_OFFSET_CNTL__CRTC_STEREO_SYNC_OUT_EN)); in radeon_pm_setup_for_suspend()
3844 OUTREG(AGP_CNTL, in radeon_pm_setup_for_suspend()
3867 OUTREG(DISP_MISC_CNTL, disp_mis_cntl); in radeon_pm_setup_for_suspend()
3889 OUTREG(DISP_PWR_MAN, disp_pwr_man); in radeon_pm_setup_for_suspend()
3907 OUTREG(DISP_PWR_MAN, disp_pwr_man); in radeon_pm_setup_for_suspend()
3910 …OUTREG( CRTC_GEN_CNTL, (INREG( CRTC_GEN_CNTL) & ~CRTC_GEN_CNTL__CRTC_EN) | CRTC_GEN_CNTL__CRTC_DIS… in radeon_pm_setup_for_suspend()
3911 …OUTREG( CRTC2_GEN_CNTL, (INREG( CRTC2_GEN_CNTL) & ~CRTC2_GEN_CNTL__CRTC2_EN) | CRTC2_GEN_CNTL__CRT… in radeon_pm_setup_for_suspend()
4111 OUTREG( MEM_SDRAM_MODE_REG, mem_sdram_mode); in radeon_pm_program_mode_reg()
4114 OUTREG( MEM_SDRAM_MODE_REG, mem_sdram_mode); in radeon_pm_program_mode_reg()
4117 OUTREG( MEM_SDRAM_MODE_REG, mem_sdram_mode); in radeon_pm_program_mode_reg()
4217 OUTREG( CRTC_MORE_CNTL, 0); in radeon_pm_full_reset_sdram()
4218 OUTREG( FP_GEN_CNTL, 0); in radeon_pm_full_reset_sdram()
4219 OUTREG( FP2_GEN_CNTL, 0); in radeon_pm_full_reset_sdram()
4221 OUTREG( CRTC_GEN_CNTL, (crtcGenCntl | CRTC_GEN_CNTL__CRTC_DISP_REQ_EN_B) ); in radeon_pm_full_reset_sdram()
4222 OUTREG( CRTC2_GEN_CNTL, (crtcGenCntl2 | CRTC2_GEN_CNTL__CRTC2_DISP_REQ_EN_B) ); in radeon_pm_full_reset_sdram()
4225 OUTREG( MEM_REFRESH_CNTL, memRefreshCntl | MEM_REFRESH_CNTL__MEM_REFRESH_DIS); in radeon_pm_full_reset_sdram()
4228 OUTREG( MEM_SDRAM_MODE_REG, in radeon_pm_full_reset_sdram()
4245 OUTREG( MEM_SDRAM_MODE_REG, in radeon_pm_full_reset_sdram()
4248 OUTREG( MEM_REFRESH_CNTL, memRefreshCntl); in radeon_pm_full_reset_sdram()
4250 OUTREG( CRTC_GEN_CNTL, crtcGenCntl); in radeon_pm_full_reset_sdram()
4251 OUTREG( CRTC2_GEN_CNTL, crtcGenCntl2); in radeon_pm_full_reset_sdram()
4252 OUTREG( FP_GEN_CNTL, fp_gen_cntl); in radeon_pm_full_reset_sdram()
4253 OUTREG( FP2_GEN_CNTL, fp2_gen_cntl); in radeon_pm_full_reset_sdram()
4255 OUTREG( CRTC_MORE_CNTL, crtc_more_cntl); in radeon_pm_full_reset_sdram()
4439 OUTREG(DP_GUI_MASTER_CNTL, (rinfo->dp_gui_master_cntl | in fbcon_radeon_bmove()
4444 OUTREG(DP_WRITE_MSK, 0xffffffff); in fbcon_radeon_bmove()
4445 OUTREG(DP_CNTL, dp_cntl); in fbcon_radeon_bmove()
4446 OUTREG(SRC_Y_X, (srcy << 16) | srcx); in fbcon_radeon_bmove()
4447 OUTREG(DST_Y_X, (dsty << 16) | dstx); in fbcon_radeon_bmove()
4448 OUTREG(DST_HEIGHT_WIDTH, (height << 16) | width); in fbcon_radeon_bmove()
4451 OUTREG(DP_CNTL, dp_cntl_save); in fbcon_radeon_bmove()
4464 OUTREG(DP_GUI_MASTER_CNTL, (rinfo->dp_gui_master_cntl | in radeon_rectfill()
4468 OUTREG(DP_BRUSH_FRGD_CLR, clr); in radeon_rectfill()
4469 OUTREG(DP_WRITE_MSK, 0xffffffff); in radeon_rectfill()
4470 OUTREG(DP_CNTL, (DST_X_LEFT_TO_RIGHT | DST_Y_TOP_TO_BOTTOM)); in radeon_rectfill()
4471 OUTREG(DST_Y_X, (dsty << 16) | dstx); in radeon_rectfill()
4472 OUTREG(DST_WIDTH_HEIGHT, (width << 16) | height); in radeon_rectfill()