578 #define OUTPLL(addr,val)						\  macro
589 		OUTPLL(addr, _tmp);					\
744 		OUTPLL(SCLK_CNTL, ((tmp & ~DYN_STOP_LAT_MASK) |  in _radeon_engine_reset()
751 			OUTPLL(SCLK_MORE_CNTL, tmp | SCLK_MORE_FORCEON);  in _radeon_engine_reset()
758 	OUTPLL(MCLK_CNTL, (mclk_cntl |  in _radeon_engine_reset()
809 	OUTPLL(MCLK_CNTL, mclk_cntl);  in _radeon_engine_reset()
2846 		OUTPLL(VCLK_ECP_CNTL, vclk_cntl & ~PIXCLK_DAC_ALWAYS_ONb);  in radeon_setcolreg()
2877 		OUTPLL(VCLK_ECP_CNTL, vclk_cntl);  in radeon_setcolreg()
3362 	OUTPLL(HTOTAL_CNTL, 0);  in radeon_write_pll_regs()
3444 	OUTPLL(VCLK_ECP_CNTL, mode->vclk_ecp_cntl);  in radeon_write_mode()
3593 	OUTPLL(P2PLL_CNTL, rinfo->save_regs[8] & 0xFFFFFFFE); /* First */  in radeon_pm_restore_regs()
3595 	OUTPLL(PLL_PWRMGT_CNTL, rinfo->save_regs[0]);  in radeon_pm_restore_regs()
3596 	OUTPLL(CLK_PWRMGT_CNTL, rinfo->save_regs[1]);  in radeon_pm_restore_regs()
3597 	OUTPLL(MCLK_CNTL, rinfo->save_regs[2]);  in radeon_pm_restore_regs()
3598 	OUTPLL(SCLK_CNTL, rinfo->save_regs[3]);  in radeon_pm_restore_regs()
3599 	OUTPLL(CLK_PIN_CNTL, rinfo->save_regs[4]);  in radeon_pm_restore_regs()
3600 	OUTPLL(VCLK_ECP_CNTL, rinfo->save_regs[5]);  in radeon_pm_restore_regs()
3601 	OUTPLL(PIXCLKS_CNTL, rinfo->save_regs[6]);  in radeon_pm_restore_regs()
3602 	OUTPLL(MCLK_MISC, rinfo->save_regs[7]);  in radeon_pm_restore_regs()
3622 	OUTPLL(P2PLL_CNTL, rinfo->save_regs[8]);  in radeon_pm_restore_regs()
3653   	OUTPLL(pllPIXCLKS_CNTL,  in radeon_pm_program_v2clk()
3656   	OUTPLL(pllP2PLL_REF_DIV, 0x0000000c);  in radeon_pm_program_v2clk()
3657 	OUTPLL(pllP2PLL_CNTL, 0x0000bf00);  in radeon_pm_program_v2clk()
3658 	OUTPLL(pllP2PLL_DIV_0, 0x00020074 | P2PLL_DIV_0__P2PLL_ATOMIC_UPDATE_W);  in radeon_pm_program_v2clk()
3660 	OUTPLL(pllP2PLL_CNTL, INPLL(pllP2PLL_CNTL) & ~P2PLL_CNTL__P2PLL_SLEEP);  in radeon_pm_program_v2clk()
3663 	OUTPLL(pllP2PLL_CNTL, INPLL(pllP2PLL_CNTL) & ~P2PLL_CNTL__P2PLL_RESET); 	  in radeon_pm_program_v2clk()
3666   	OUTPLL(pllPIXCLKS_CNTL,  in radeon_pm_program_v2clk()
3686 	OUTPLL(PLL_PWRMGT_CNTL, reg);  in radeon_pm_low_current()
3755 	OUTPLL( pllSCLK_CNTL_M6, sclk_cntl);  in radeon_pm_setup_for_suspend()
3762 	OUTPLL(pllSCLK_MORE_CNTL, sclk_more_cntl);		  in radeon_pm_setup_for_suspend()
3772     	OUTPLL( pllMCLK_CNTL_M6, mclk_cntl);  in radeon_pm_setup_for_suspend()
3778 	OUTPLL( pllVCLK_ECP_CNTL, vclk_ecp_cntl);  in radeon_pm_setup_for_suspend()
3790  	OUTPLL( pllPIXCLKS_CNTL, pixclks_cntl);  in radeon_pm_setup_for_suspend()
3803 	OUTPLL( pllPLL_PWRMGT_CNTL, pll_pwrmgt_cntl);  in radeon_pm_setup_for_suspend()
3824 	OUTPLL( pllCLK_PWRMGT_CNTL_M6, clk_pwrmgt_cntl);	  in radeon_pm_setup_for_suspend()
3829 	OUTPLL( pllMCLK_MISC, INPLL( pllMCLK_MISC) | MCLK_MISC__EN_MCLK_TRISTATE_IN_SUSPEND);	  in radeon_pm_setup_for_suspend()
3841 	OUTPLL( pllCLK_PIN_CNTL, clk_pin_cntl);  in radeon_pm_setup_for_suspend()
3849 	OUTPLL( pllPLL_PWRMGT_CNTL, INPLL( pllPLL_PWRMGT_CNTL) & ~PLL_PWRMGT_CNTL__PM_MODE_SEL);					  in radeon_pm_setup_for_suspend()
3904 	OUTPLL( pllCLK_PWRMGT_CNTL_M6, clk_pwrmgt_cntl);  in radeon_pm_setup_for_suspend()
3905 	OUTPLL( pllPLL_PWRMGT_CNTL, pll_pwrmgt_cntl);  in radeon_pm_setup_for_suspend()
3906 	OUTPLL( pllCLK_PIN_CNTL, clk_pin_cntl);  in radeon_pm_setup_for_suspend()
3950     	OUTPLL( pllSCLK_CNTL_M6, sclk_cntl);  in radeon_pm_disable_dynamic_mode()
3958 	OUTPLL(pllSCLK_MORE_CNTL, sclk_more_cntl);  in radeon_pm_disable_dynamic_mode()
3965 	OUTPLL( pllVCLK_ECP_CNTL, vclk_ecp_cntl);  in radeon_pm_disable_dynamic_mode()
3976  	OUTPLL( pllPIXCLKS_CNTL, pixclks_cntl);  in radeon_pm_disable_dynamic_mode()
3985     	OUTPLL( pllMCLK_CNTL_M6, mclk_cntl);  in radeon_pm_disable_dynamic_mode()
4017 	OUTPLL( pllCLK_PWRMGT_CNTL_M6, clk_pwrmgt_cntl);  in radeon_pm_enable_dynamic_mode()
4023 	OUTPLL( pllCLK_PIN_CNTL, clk_pin_cntl);  in radeon_pm_enable_dynamic_mode()
4031 	OUTPLL( pllSCLK_CNTL_M6, sclk_cntl);  in radeon_pm_enable_dynamic_mode()
4037 	OUTPLL(pllSCLK_MORE_CNTL, sclk_more_cntl);  in radeon_pm_enable_dynamic_mode()
4052 	OUTPLL( pllPIXCLKS_CNTL, pixclks_cntl);  in radeon_pm_enable_dynamic_mode()
4060 	OUTPLL( pllVCLK_ECP_CNTL, vclk_ecp_cntl);  in radeon_pm_enable_dynamic_mode()
4069     	OUTPLL( pllMCLK_CNTL_M6, mclk_cntl);  in radeon_pm_enable_dynamic_mode()
4077 	OUTPLL(pllMCLK_MISC, mclk_misc);  in radeon_pm_enable_dynamic_mode()
4135 	OUTPLL(pllMDLL_CKO,   	DLL_CKO_Value);  in radeon_pm_enable_dll()
4136 	OUTPLL(pllMDLL_RDCKA,  	DLL_CKA_Value);  in radeon_pm_enable_dll()
4137 	OUTPLL(pllMDLL_RDCKB,	DLL_CKB_Value);  in radeon_pm_enable_dll()
4145 	OUTPLL(pllMDLL_CKO,   	DLL_CKO_Value);  in radeon_pm_enable_dll()
4149 	OUTPLL(pllMDLL_CKO,	DLL_CKO_Value);  in radeon_pm_enable_dll()
4154 	OUTPLL(pllMDLL_RDCKA,  	DLL_CKA_Value);  in radeon_pm_enable_dll()
4158 	OUTPLL(pllMDLL_RDCKA,	DLL_CKA_Value);  in radeon_pm_enable_dll()
4163 	OUTPLL(pllMDLL_RDCKA,	DLL_CKA_Value);  in radeon_pm_enable_dll()
4167 	OUTPLL(pllMDLL_RDCKA,	DLL_CKA_Value);  in radeon_pm_enable_dll()
4175 	OUTPLL(pllMDLL_CKO,   	DLL_CKO_Value);  in radeon_pm_enable_dll()
4179 	OUTPLL(pllMDLL_CKO,   	DLL_CKO_Value);  in radeon_pm_enable_dll()
4184 	OUTPLL(pllMDLL_RDCKB,   DLL_CKB_Value);  in radeon_pm_enable_dll()
4188 	OUTPLL(pllMDLL_RDCKB,   DLL_CKB_Value);  in radeon_pm_enable_dll()
4193 	OUTPLL(pllMDLL_RDCKB,   DLL_CKB_Value);  in radeon_pm_enable_dll()
4197 	OUTPLL(pllMDLL_RDCKB,   DLL_CKB_Value);  in radeon_pm_enable_dll()
4296 			OUTPLL( pllMDLL_CKO, INPLL( pllMDLL_CKO) | MDLL_CKO__MCKOA_RESET | MDLL_CKO__MCKOB_RESET);  in radeon_set_suspend()