586 		unsigned int _tmp = INPLL(addr);			\
607 #define INPLL(addr)		_INPLL(rinfo, addr)  macro
743 		tmp = INPLL(SCLK_CNTL);  in _radeon_engine_reset()
750 			tmp = INPLL(SCLK_MORE_CNTL);  in _radeon_engine_reset()
756 	mclk_cntl = INPLL(MCLK_CNTL);  in _radeon_engine_reset()
1115 			tmp = INPLL(M_SPLL_REF_FB_DIV);  in radeon_get_pllinfo()
1116 			ref_div = INPLL(PPLL_REF_DIV) & 0x3ff;  in radeon_get_pllinfo()
2845 		vclk_cntl = INPLL(VCLK_ECP_CNTL);  in radeon_setcolreg()
2941 	save->vclk_ecp_cntl = INPLL(VCLK_ECP_CNTL);  in radeon_save_state()
3334 		if ((mode->ppll_ref_div == (INPLL(PPLL_REF_DIV) & PPLL_REF_DIV_MASK)) &&  in radeon_write_pll_regs()
3335 		    (mode->ppll_div_3 == (INPLL(PPLL_DIV_3) &  in radeon_write_pll_regs()
3347 	while ((INPLL(PPLL_REF_DIV) & PPLL_REF_DIV_MASK) !=  in radeon_write_pll_regs()
3352 	while ((INPLL(PPLL_DIV_3) & PPLL_FB3_DIV_MASK) !=  in radeon_write_pll_regs()
3357 	while ((INPLL(PPLL_DIV_3) & PPLL_POST3_DIV_MASK) !=  in radeon_write_pll_regs()
3553 	rinfo->save_regs[0] = INPLL(PLL_PWRMGT_CNTL);  in radeon_pm_save_regs()
3554 	rinfo->save_regs[1] = INPLL(CLK_PWRMGT_CNTL);  in radeon_pm_save_regs()
3555 	rinfo->save_regs[2] = INPLL(MCLK_CNTL);  in radeon_pm_save_regs()
3556 	rinfo->save_regs[3] = INPLL(SCLK_CNTL);  in radeon_pm_save_regs()
3557 	rinfo->save_regs[4] = INPLL(CLK_PIN_CNTL);  in radeon_pm_save_regs()
3558 	rinfo->save_regs[5] = INPLL(VCLK_ECP_CNTL);  in radeon_pm_save_regs()
3559 	rinfo->save_regs[6] = INPLL(PIXCLKS_CNTL);  in radeon_pm_save_regs()
3560 	rinfo->save_regs[7] = INPLL(MCLK_MISC);  in radeon_pm_save_regs()
3561 	rinfo->save_regs[8] = INPLL(P2PLL_CNTL);  in radeon_pm_save_regs()
3654   		INPLL(pllPIXCLKS_CNTL) & ~PIXCLKS_CNTL__PIX2CLK_SRC_SEL_MASK);  in radeon_pm_program_v2clk()
3660 	OUTPLL(pllP2PLL_CNTL, INPLL(pllP2PLL_CNTL) & ~P2PLL_CNTL__P2PLL_SLEEP);  in radeon_pm_program_v2clk()
3663 	OUTPLL(pllP2PLL_CNTL, INPLL(pllP2PLL_CNTL) & ~P2PLL_CNTL__P2PLL_RESET); 	  in radeon_pm_program_v2clk()
3667   		(INPLL(pllPIXCLKS_CNTL) & ~PIXCLKS_CNTL__PIX2CLK_SRC_SEL_MASK)  in radeon_pm_program_v2clk()
3681 	reg  = INPLL(PLL_PWRMGT_CNTL);  in radeon_pm_low_current()
3727 	sclk_cntl = INPLL( pllSCLK_CNTL_M6);  in radeon_pm_setup_for_suspend()
3757 	sclk_more_cntl = INPLL(pllSCLK_MORE_CNTL);  in radeon_pm_setup_for_suspend()
3765 	mclk_cntl = INPLL( pllMCLK_CNTL_M6);  in radeon_pm_setup_for_suspend()
3775 	vclk_ecp_cntl = INPLL( pllVCLK_ECP_CNTL);  in radeon_pm_setup_for_suspend()
3781 	pixclks_cntl = INPLL( pllPIXCLKS_CNTL);  in radeon_pm_setup_for_suspend()
3795 	pll_pwrmgt_cntl = INPLL( pllPLL_PWRMGT_CNTL);  in radeon_pm_setup_for_suspend()
3805 	clk_pwrmgt_cntl	 = INPLL( pllCLK_PWRMGT_CNTL_M6);  in radeon_pm_setup_for_suspend()
3826 	clk_pin_cntl = INPLL( pllCLK_PIN_CNTL);  in radeon_pm_setup_for_suspend()
3829 	OUTPLL( pllMCLK_MISC, INPLL( pllMCLK_MISC) | MCLK_MISC__EN_MCLK_TRISTATE_IN_SUSPEND);	  in radeon_pm_setup_for_suspend()
3849 	OUTPLL( pllPLL_PWRMGT_CNTL, INPLL( pllPLL_PWRMGT_CNTL) & ~PLL_PWRMGT_CNTL__PM_MODE_SEL);					  in radeon_pm_setup_for_suspend()
3891 	clk_pwrmgt_cntl = INPLL( pllCLK_PWRMGT_CNTL_M6);  in radeon_pm_setup_for_suspend()
3892 	pll_pwrmgt_cntl = INPLL( pllPLL_PWRMGT_CNTL) ;  in radeon_pm_setup_for_suspend()
3893 	clk_pin_cntl 	= INPLL( pllCLK_PIN_CNTL);  in radeon_pm_setup_for_suspend()
3932 	sclk_cntl = INPLL( pllSCLK_CNTL_M6);  in radeon_pm_disable_dynamic_mode()
3954 	sclk_more_cntl = INPLL(pllSCLK_MORE_CNTL);  in radeon_pm_disable_dynamic_mode()
3961 	vclk_ecp_cntl = INPLL( pllVCLK_ECP_CNTL);  in radeon_pm_disable_dynamic_mode()
3967 	pixclks_cntl = INPLL( pllPIXCLKS_CNTL);  in radeon_pm_disable_dynamic_mode()
3979 	mclk_cntl  = INPLL( pllMCLK_CNTL_M6);  in radeon_pm_disable_dynamic_mode()
4004 	clk_pwrmgt_cntl = INPLL( pllCLK_PWRMGT_CNTL_M6);  in radeon_pm_enable_dynamic_mode()
4020 	clk_pin_cntl = INPLL( pllCLK_PIN_CNTL);  in radeon_pm_enable_dynamic_mode()
4027 	sclk_cntl = INPLL( pllSCLK_CNTL_M6);	  in radeon_pm_enable_dynamic_mode()
4034 	sclk_more_cntl = INPLL(pllSCLK_MORE_CNTL);  in radeon_pm_enable_dynamic_mode()
4042 	pixclks_cntl = INPLL( pllPIXCLKS_CNTL);  in radeon_pm_enable_dynamic_mode()
4055 	vclk_ecp_cntl = INPLL( pllVCLK_ECP_CNTL);  in radeon_pm_enable_dynamic_mode()
4064 	mclk_cntl = INPLL( pllMCLK_CNTL_M6);  in radeon_pm_enable_dynamic_mode()
4071 	mclk_misc = INPLL(pllMCLK_MISC);  in radeon_pm_enable_dynamic_mode()
4130 	u32 DLL_CKO_Value = INPLL(pllMDLL_CKO)   | MDLL_CKO__MCKOA_SLEEP |  MDLL_CKO__MCKOA_RESET;  in radeon_pm_enable_dll()
4131 …u32 DLL_CKA_Value = INPLL(pllMDLL_RDCKA) | MDLL_RDCKA__MRDCKA0_SLEEP | MDLL_RDCKA__MRDCKA1_SLEEP |…  in radeon_pm_enable_dll()
4132 …u32 DLL_CKB_Value = INPLL(pllMDLL_RDCKB) | MDLL_RDCKB__MRDCKB0_SLEEP | MDLL_RDCKB__MRDCKB1_SLEEP |…  in radeon_pm_enable_dll()
4296 			OUTPLL( pllMDLL_CKO, INPLL( pllMDLL_CKO) | MDLL_CKO__MCKOA_RESET | MDLL_CKO__MCKOB_RESET);  in radeon_set_suspend()