214 static u32 itMmioAddr;  variable
324 	writeb(addr,itMmioAddr+0x3ce);  in itReadRegExtB()
325 	return readb(itMmioAddr+0x3cf);  in itReadRegExtB()
331 	writeb(addr,itMmioAddr+0x3ce);  in itWriteRegExtB()
332 	writeb(value,itMmioAddr+0x3cf);  in itWriteRegExtB()
352 	writeb(addr,itMmioAddr+0x3d6);  in itReadRegExtA()
353 	return readb(itMmioAddr+0x3d7);  in itReadRegExtA()
359 	writeb(addr,itMmioAddr+0x3d6);  in itWriteRegExtA()
360 	writeb(value,itMmioAddr+0x3d7);  in itWriteRegExtA()
376 	writeb(addr,itMmioAddr+VGA_CRT_IC);  in itReadRegCrtc()
377 	return readb(itMmioAddr+VGA_CRT_DC);  in itReadRegCrtc()
383 	writeb(addr,itMmioAddr+VGA_CRT_IC);  in itWriteRegCrtc()
384 	writeb(value,itMmioAddr+VGA_CRT_DC);  in itWriteRegCrtc()
390 	return readb(itMmioAddr+VGA_MIS_R);  in itReadRegMisc()
395 	writeb(value, itMmioAddr+VGA_MIS_W);		  in itWriteRegMisc()
400 	writeb(addr, itMmioAddr+VGA_SEQ_I);  in itReadRegSEQ()
401 	return readb(itMmioAddr+VGA_SEQ_D);  in itReadRegSEQ()
406 	writeb(addr, itMmioAddr+VGA_SEQ_I);  in itWriteRegSEQ()
407 	writeb(value, itMmioAddr+VGA_SEQ_D);  in itWriteRegSEQ()
1095 	writeb((u8)regno, itMmioAddr+VGA_PEL_IW);  in do_setpalentry()
1096 	writeb(r, itMmioAddr+VGA_PEL_D);  in do_setpalentry()
1097 	writeb(g, itMmioAddr+VGA_PEL_D);  in do_setpalentry()
1098 	writeb(b, itMmioAddr+VGA_PEL_D);	  in do_setpalentry()
1104 	writeb((u8)regno, itMmioAddr+VGA_PEL_IW);  in do_getpalentry()
1105 	*r = readb(itMmioAddr+VGA_PEL_D);  in do_getpalentry()
1106 	*g = readb(itMmioAddr+VGA_PEL_D);  in do_getpalentry()
1107 	*b = readb(itMmioAddr+VGA_PEL_D);	  in do_getpalentry()
1223 	p->itMmioAddrVirt = itMmioAddr = (u32) ioremap(p->itMmioAddrPhys +  in it8181fb_init()
1227 	info("Mmio at 0x%08x, Framebuffer at 0x%08x", itMmioAddr, p->itFbAddrVirt);  in it8181fb_init()
1272 	iounmap((void *)itMmioAddr);  in it8181fb_init()
1288 	iounmap((void*)itMmioAddr);  in cleanup_module()