292 	OUTREG(DSPABASE, offset);  in intelfbhw_pan_display()
312 	OUTREG(DSPACNTR, tmp);  in intelfbhw_do_blank()
315 	OUTREG(DSPABASE, tmp);  in intelfbhw_do_blank()
348 	OUTREG(ADPA, tmp);  in intelfbhw_do_blank()
367 	OUTREG(palette_reg + (regno << 2),   in intelfbhw_setcolreg()
1078 	OUTREG(VGACNTRL, tmp);  in intelfbhw_program_mode()
1139 	OUTREG(DSPACNTR, tmp);  in intelfbhw_program_mode()
1142 	OUTREG(DSPBCNTR, tmp);  in intelfbhw_program_mode()
1151 	OUTREG(ADPA, tmp);  in intelfbhw_program_mode()
1156 	OUTREG(pipe_conf_reg, tmp);  in intelfbhw_program_mode()
1161 	OUTREG(dpll_reg, tmp);  in intelfbhw_program_mode()
1164 	OUTREG(dpll_reg, *dpll & ~DPLL_VCO_ENABLE);  in intelfbhw_program_mode()
1165 	OUTREG(fp0_reg, *fp0);  in intelfbhw_program_mode()
1166 	OUTREG(fp1_reg, *fp1);  in intelfbhw_program_mode()
1169 	OUTREG(hsync_reg, *hs);  in intelfbhw_program_mode()
1170 	OUTREG(hblank_reg, *hb);  in intelfbhw_program_mode()
1171 	OUTREG(htotal_reg, *ht);  in intelfbhw_program_mode()
1172 	OUTREG(vsync_reg, *vs);  in intelfbhw_program_mode()
1173 	OUTREG(vblank_reg, *vb);  in intelfbhw_program_mode()
1174 	OUTREG(vtotal_reg, *vt);  in intelfbhw_program_mode()
1175 	OUTREG(src_size_reg, *ss);  in intelfbhw_program_mode()
1178 	OUTREG(ADPA, (hw->adpa & ~(ADPA_DPMS_CONTROL_MASK)) | ADPA_DPMS_D3);  in intelfbhw_program_mode()
1183 	OUTREG(dpll_reg, tmp);  in intelfbhw_program_mode()
1186 	OUTREG(pipe_conf_reg, *pipe_conf | PIPECONF_ENABLE);  in intelfbhw_program_mode()
1192 	OUTREG(ADPA, tmp);  in intelfbhw_program_mode()
1195 	OUTREG(DSPACNTR, hw->disp_a_ctrl & ~DISPPLANE_PLANE_ENABLE);  in intelfbhw_program_mode()
1196 	OUTREG(DSPASTRIDE, hw->disp_a_stride);  in intelfbhw_program_mode()
1197 	OUTREG(DSPABASE, hw->disp_a_base);  in intelfbhw_program_mode()
1203 		OUTREG(DSPACNTR, tmp);  in intelfbhw_program_mode()
1204 		OUTREG(DSPABASE, hw->disp_a_base);  in intelfbhw_program_mode()
1325 		OUTREG(FENCE + (i << 2), 0);  in reset_state()
1336 	OUTREG(PRI_RING_LENGTH, 0);  in reset_state()
1337 	OUTREG(PRI_RING_HEAD, 0);  in reset_state()
1338 	OUTREG(PRI_RING_TAIL, 0);  in reset_state()
1339 	OUTREG(PRI_RING_START, 0);  in reset_state()
1371 	OUTREG(PRI_RING_LENGTH, 0);  in intelfbhw_2d_start()
1372 	OUTREG(PRI_RING_TAIL, 0);  in intelfbhw_2d_start()
1373 	OUTREG(PRI_RING_HEAD, 0);  in intelfbhw_2d_start()
1375 	OUTREG(PRI_RING_START, dinfo->ring_base_phys & RING_START_MASK);  in intelfbhw_2d_start()
1376 	OUTREG(PRI_RING_LENGTH,  in intelfbhw_2d_start()
1384 	OUTREG(INSTPM, 0x1f << 16);  in intelfbhw_2d_start()
1385 	OUTREG(INSTPM, 0x1f << 16);  in intelfbhw_2d_start()
1624 		OUTREG(CURSOR_A_CONTROL, tmp);  in intelfbhw_cursor_init()
1625 		OUTREG(CURSOR_A_BASEADDR, dinfo->cursor_base_real);  in intelfbhw_cursor_init()
1633 		OUTREG(CURSOR_CONTROL, tmp);  in intelfbhw_cursor_init()
1634 		OUTREG(CURSOR_A_BASEADDR, dinfo->cursor_offset);  in intelfbhw_cursor_init()
1637 		OUTREG(CURSOR_SIZE, tmp);  in intelfbhw_cursor_init()
1661 		OUTREG(CURSOR_A_CONTROL, tmp);  in intelfbhw_cursor_hide()
1663 		OUTREG(CURSOR_A_BASEADDR, dinfo->cursor_base_real);  in intelfbhw_cursor_hide()
1667 		OUTREG(CURSOR_CONTROL, tmp);  in intelfbhw_cursor_hide()
1695 		OUTREG(CURSOR_A_CONTROL, tmp);  in intelfbhw_cursor_show()
1697 		OUTREG(CURSOR_A_BASEADDR, dinfo->cursor_base_real);  in intelfbhw_cursor_show()
1701 		OUTREG(CURSOR_CONTROL, tmp);  in intelfbhw_cursor_show()
1725 	OUTREG(CURSOR_A_POSITION, tmp);  in intelfbhw_cursor_setpos()
1738 	OUTREG(CURSOR_A_PALETTE0, bg & CURSOR_PALETTE_MASK);  in intelfbhw_cursor_setcolor()
1739 	OUTREG(CURSOR_A_PALETTE1, fg & CURSOR_PALETTE_MASK);  in intelfbhw_cursor_setcolor()
1740 	OUTREG(CURSOR_A_PALETTE2, fg & CURSOR_PALETTE_MASK);  in intelfbhw_cursor_setcolor()
1741 	OUTREG(CURSOR_A_PALETTE3, bg & CURSOR_PALETTE_MASK);  in intelfbhw_cursor_setcolor()