Lines Matching refs:aty_st_le32
515 #define aty_st_le32(regindex, val) _aty_st_le32(regindex, val, info) macro
541 aty_st_le32(CLOCK_CNTL_DATA, val); in _aty_st_pll()
590 aty_st_le32(BIOS_0_SCRATCH, 0x55555555); in register_test()
592 aty_st_le32(BIOS_0_SCRATCH, 0xAAAAAAAA); in register_test()
598 aty_st_le32(BIOS_0_SCRATCH, val); // restore value in register_test()
660 aty_st_le32(PC_NGUI_CTLSTAT, tmp); in aty128_flush_pixel_cache()
681 aty_st_le32(GEN_RESET_CNTL, gen_reset_cntl | SOFT_RESET_GUI); in aty128_reset_engine()
683 aty_st_le32(GEN_RESET_CNTL, gen_reset_cntl & ~(SOFT_RESET_GUI)); in aty128_reset_engine()
687 aty_st_le32(CLOCK_CNTL_INDEX, clock_cntl_index); in aty128_reset_engine()
688 aty_st_le32(GEN_RESET_CNTL, gen_reset_cntl); in aty128_reset_engine()
691 aty_st_le32(PM4_BUFFER_CNTL, PM4_BUFFER_CNTL_NONPM4); in aty128_reset_engine()
707 aty_st_le32(SCALE_3D_CNTL, 0x00000000); in aty128_init_engine()
718 aty_st_le32(DEFAULT_OFFSET, 0x00000000); in aty128_init_engine()
721 aty_st_le32(DEFAULT_PITCH, pitch_value); in aty128_init_engine()
724 aty_st_le32(DEFAULT_SC_BOTTOM_RIGHT, (0x1FFF << 16) | 0x1FFF); in aty128_init_engine()
727 aty_st_le32(DP_GUI_MASTER_CNTL, in aty128_init_engine()
746 aty_st_le32(DST_BRES_ERR, 0); in aty128_init_engine()
747 aty_st_le32(DST_BRES_INC, 0); in aty128_init_engine()
748 aty_st_le32(DST_BRES_DEC, 0); in aty128_init_engine()
751 aty_st_le32(DP_BRUSH_FRGD_CLR, 0xFFFFFFFF); /* white */ in aty128_init_engine()
752 aty_st_le32(DP_BRUSH_BKGD_CLR, 0x00000000); /* black */ in aty128_init_engine()
755 aty_st_le32(DP_SRC_FRGD_CLR, 0xFFFFFFFF); /* white */ in aty128_init_engine()
756 aty_st_le32(DP_SRC_BKGD_CLR, 0x00000000); /* black */ in aty128_init_engine()
759 aty_st_le32(DP_WRITE_MASK, 0xFFFFFFFF); in aty128_init_engine()
794 aty_st_le32(CRTC_GEN_CNTL, crtc->gen_cntl); in aty128_set_crtc()
795 aty_st_le32(CRTC_H_TOTAL_DISP, crtc->h_total); in aty128_set_crtc()
796 aty_st_le32(CRTC_H_SYNC_STRT_WID, crtc->h_sync_strt_wid); in aty128_set_crtc()
797 aty_st_le32(CRTC_V_TOTAL_DISP, crtc->v_total); in aty128_set_crtc()
798 aty_st_le32(CRTC_V_SYNC_STRT_WID, crtc->v_sync_strt_wid); in aty128_set_crtc()
799 aty_st_le32(CRTC_PITCH, crtc->pitch); in aty128_set_crtc()
800 aty_st_le32(CRTC_OFFSET, crtc->offset); in aty128_set_crtc()
801 aty_st_le32(CRTC_OFFSET_CNTL, crtc->offset_cntl); in aty128_set_crtc()
1068 aty_st_le32(CRTC_EXT_CNTL, aty_ld_le32(CRTC_EXT_CNTL) | CRT_CRTC_ON); in aty128_set_crt_enable()
1069 aty_st_le32(DAC_CNTL, (aty_ld_le32(DAC_CNTL) | DAC_PALETTE2_SNOOP_EN)); in aty128_set_crt_enable()
1071 aty_st_le32(CRTC_EXT_CNTL, aty_ld_le32(CRTC_EXT_CNTL) & ~CRT_CRTC_ON); in aty128_set_crt_enable()
1083 aty_st_le32(LVDS_GEN_CNTL, reg); in aty128_set_lcd_enable()
1093 aty_st_le32(LVDS_GEN_CNTL, reg); in aty128_set_lcd_enable()
1096 aty_st_le32(LVDS_GEN_CNTL, reg); in aty128_set_lcd_enable()
1109 aty_st_le32(CLOCK_CNTL_INDEX, aty_ld_le32(CLOCK_CNTL_INDEX) | (3 << 8)); in aty128_set_pll()
1214 aty_st_le32(DDA_CONFIG, dsp->dda_config); in aty128_set_fifo()
1215 aty_st_le32(DDA_ON_OFF, dsp->dda_on_off); in aty128_set_fifo()
1292 aty_st_le32(OVR_CLR, 0); in aty128_set_par()
1293 aty_st_le32(OVR_WID_LEFT_RIGHT, 0); in aty128_set_par()
1294 aty_st_le32(OVR_WID_TOP_BOTTOM, 0); in aty128_set_par()
1295 aty_st_le32(OV0_SCALE_CNTL, 0); in aty128_set_par()
1296 aty_st_le32(MPP_TB_CONFIG, 0); in aty128_set_par()
1297 aty_st_le32(MPP_GP_CONFIG, 0); in aty128_set_par()
1298 aty_st_le32(SUBPIC_CNTL, 0); in aty128_set_par()
1299 aty_st_le32(VIPH_CONTROL, 0); in aty128_set_par()
1300 aty_st_le32(I2C_CNTL_1, 0); /* turn off i2c */ in aty128_set_par()
1301 aty_st_le32(GEN_INT_CNTL, 0); /* turn off interrupts */ in aty128_set_par()
1302 aty_st_le32(CAP0_TRIG_CNTL, 0); in aty128_set_par()
1303 aty_st_le32(CAP1_TRIG_CNTL, 0); in aty128_set_par()
1320 aty_st_le32(CONFIG_CNTL, config); in aty128_set_par()
1651 aty_st_le32(CRTC_OFFSET, offset); in aty128fb_pan_display()
1726 aty_st_le32(DAC_CNTL, aty_ld_le32(DAC_CNTL) | DAC_PALETTE_ACCESS_CNTL); in aty128_st_pal()
1728 aty_st_le32(PALETTE_DATA, (red<<16)|(green<<8)|blue); in aty128_st_pal()
1730 aty_st_le32(DAC_CNTL, aty_ld_le32(DAC_CNTL) & ~DAC_PALETTE_ACCESS_CNTL); in aty128_st_pal()
1733 aty_st_le32(PALETTE_DATA, (red<<16)|(green<<8)|blue); in aty128_st_pal()
1931 aty_st_le32(DAC_CNTL, dac); in aty128_init()
1934 aty_st_le32(BUS_CNTL, aty_ld_le32(BUS_CNTL) | BUS_MASTER_DIS); in aty128_init()
2543 aty_st_le32(LVDS_GEN_CNTL, reg); in aty128_set_backlight_enable()
2547 aty_st_le32(LVDS_GEN_CNTL, reg); in aty128_set_backlight_enable()
2555 aty_st_le32(LVDS_GEN_CNTL, reg); in aty128_set_backlight_enable()
2557 aty_st_le32(DAC_CNTL, aty_ld_le32(DAC_CNTL) & (~DAC_PDWN)); in aty128_set_backlight_enable()
2564 aty_st_le32(LVDS_GEN_CNTL, reg); in aty128_set_backlight_enable()
2569 aty_st_le32(LVDS_GEN_CNTL, reg); in aty128_set_backlight_enable()
2571 aty_st_le32(DAC_CNTL, aty_ld_le32(DAC_CNTL) | DAC_PDWN); in aty128_set_backlight_enable()
2614 aty_st_le32(SRC_Y_X, (srcy << 16) | srcx); in aty128_rectcopy()
2615 aty_st_le32(DP_MIX, ROP3_SRCCOPY | DP_SRC_RECT); in aty128_rectcopy()
2616 aty_st_le32(DP_CNTL, DST_X_LEFT_TO_RIGHT | DST_Y_TOP_TO_BOTTOM); in aty128_rectcopy()
2617 aty_st_le32(DP_DATATYPE, save_dp_datatype | dstval | SRC_DSTCOLOR); in aty128_rectcopy()
2619 aty_st_le32(DST_Y_X, (dsty << 16) | dstx); in aty128_rectcopy()
2620 aty_st_le32(DST_HEIGHT_WIDTH, (height << 16) | width); in aty128_rectcopy()
2625 aty_st_le32(DP_DATATYPE, save_dp_datatype); in aty128_rectcopy()
2626 aty_st_le32(DP_CNTL, save_dp_cntl); in aty128_rectcopy()
2862 aty_st_le32(CRTC2_GEN_CNTL, aty_ld_le32(CRTC2_GEN_CNTL) & in aty128_set_suspend()
2875 aty_st_le32(BUS_CNTL1, 0x00000010); in aty128_set_suspend()
2876 aty_st_le32(MEM_POWER_MISC, 0x0c830000); in aty128_set_suspend()