Lines Matching refs:info
19 static void aty_st_pll(int offset, u8 val, const struct fb_info_aty *info) stdcall;
21 static int aty_valid_pll_ct(const struct fb_info_aty *info, u32 vclk_per,
23 static int aty_dsp_gt(const struct fb_info_aty *info, u8 bpp, u32 stretch,
25 static int aty_var_to_pll_ct(const struct fb_info_aty *info, u32 vclk_per,
27 static u32 aty_pll_ct_to_var(const struct fb_info_aty *info,
87 u8 stdcall aty_ld_pll(int offset, const struct fb_info_aty *info) in aty_ld_pll() argument
91 addr = info->ati_regbase + CLOCK_CNTL + 1; in aty_ld_pll()
99 static void stdcall aty_st_pll(int offset, u8 val, const struct fb_info_aty *info) in aty_st_pll() argument
102 addr = info->ati_regbase + CLOCK_CNTL + 1; in aty_st_pll()
132 static int aty_dsp_gt(const struct fb_info_aty *info, u8 bpp, in aty_dsp_gt() argument
140 multiplier = ((u32)info->mclk_fb_div)*pll->vclk_post_div_real; in aty_dsp_gt()
141 divider = ((u32)pll->vclk_fb_div)*info->xclk_post_div_real; in aty_dsp_gt()
143 ras_multiplier = info->xclkmaxrasdelay; in aty_dsp_gt()
156 multiplier = multiplier * info->lcd_width; in aty_dsp_gt()
159 ras_multiplier = ras_multiplier * info->lcd_width; in aty_dsp_gt()
172 tmp = ((multiplier * info->fifo_size) << vshift) / divider; in aty_dsp_gt()
184 dsp_off = ((multiplier * (info->fifo_size - 1)) << vshift) / divider - in aty_dsp_gt()
195 dsp_on = dsp_on + (tmp * 2) + (info->xclkpagefaultdelay << xshift); in aty_dsp_gt()
213 pll->dsp_config = (dsp_precision << 20) | (info->dsp_loop_latency << 16) | in aty_dsp_gt()
218 static int aty_valid_pll_ct(const struct fb_info_aty *info, u32 vclk_per, in aty_valid_pll_ct() argument
224 q = info->ref_clk_per*info->pll_ref_div*4/vclk_per; /* actually 8*q */ in aty_valid_pll_ct()
239 static int aty_var_to_pll_ct(const struct fb_info_aty *info, u32 vclk_per, in aty_var_to_pll_ct() argument
244 if ((err = aty_valid_pll_ct(info, vclk_per, &pll->ct))) in aty_var_to_pll_ct()
246 if (M64_HAS(GTB_DSP) && (err = aty_dsp_gt(info, bpp, width, &pll->ct))) in aty_var_to_pll_ct()
251 static u32 aty_pll_ct_to_var(const struct fb_info_aty *info, in aty_pll_ct_to_var() argument
254 u32 ref_clk_per = info->ref_clk_per; in aty_pll_ct_to_var()
255 u8 pll_ref_div = info->pll_ref_div; in aty_pll_ct_to_var()
262 void aty_set_pll_ct(const struct fb_info_aty *info, const union aty_pll *pll) in aty_set_pll_ct() argument
265 aty_st_pll(PLL_VCLK_CNTL, pll->ct.pll_vclk_cntl, info); in aty_set_pll_ct()
266 a = aty_ld_pll(VCLK_POST_DIV, info) & ~3; in aty_set_pll_ct()
267 aty_st_pll(VCLK_POST_DIV, a | pll->ct.vclk_post_div, info); in aty_set_pll_ct()
268 aty_st_pll(VCLK0_FB_DIV, pll->ct.vclk_fb_div, info); in aty_set_pll_ct()
271 aty_st_le32(DSP_CONFIG, pll->ct.dsp_config, info); in aty_set_pll_ct()
272 aty_st_le32(DSP_ON_OFF, pll->ct.dsp_on_off, info); in aty_set_pll_ct()
277 static void __init aty_init_pll_ct(struct fb_info_aty *info) { in aty_init_pll_ct() argument
284 mc = aty_ld_le32(MEM_CNTL, info); in aty_init_pll_ct()
288 info->xclkpagefaultdelay = trcd + tcrd + trp + 2; in aty_init_pll_ct()
289 info->xclkmaxrasdelay = tras + trp + 2; in aty_init_pll_ct()
292 info->fifo_size = 24; in aty_init_pll_ct()
293 info->xclkpagefaultdelay += 2; in aty_init_pll_ct()
294 info->xclkmaxrasdelay += 3; in aty_init_pll_ct()
296 info->fifo_size = 32; in aty_init_pll_ct()
299 switch (info->ram_type) { in aty_init_pll_ct()
301 if (info->total_vram<=1*1024*1024) { in aty_init_pll_ct()
302 info->dsp_loop_latency = 10; in aty_init_pll_ct()
304 info->dsp_loop_latency = 8; in aty_init_pll_ct()
305 info->xclkpagefaultdelay += 2; in aty_init_pll_ct()
310 if (info->total_vram<=1*1024*1024) { in aty_init_pll_ct()
311 info->dsp_loop_latency = 9; in aty_init_pll_ct()
313 info->dsp_loop_latency = 8; in aty_init_pll_ct()
314 info->xclkpagefaultdelay += 1; in aty_init_pll_ct()
318 if (info->total_vram<=1*1024*1024) { in aty_init_pll_ct()
319 info->dsp_loop_latency = 11; in aty_init_pll_ct()
321 info->dsp_loop_latency = 10; in aty_init_pll_ct()
322 info->xclkpagefaultdelay += 1; in aty_init_pll_ct()
326 info->dsp_loop_latency = 8; in aty_init_pll_ct()
327 info->xclkpagefaultdelay += 3; in aty_init_pll_ct()
330 info->dsp_loop_latency = 11; in aty_init_pll_ct()
331 info->xclkpagefaultdelay += 3; in aty_init_pll_ct()
335 if (info->xclkmaxrasdelay <= info->xclkpagefaultdelay) in aty_init_pll_ct()
336 info->xclkmaxrasdelay = info->xclkpagefaultdelay + 1; in aty_init_pll_ct()
340 if (info->mclk_per == 0) { in aty_init_pll_ct()
344 info->pll_ref_div = aty_ld_pll(PLL_REF_DIV, info); in aty_init_pll_ct()
345 pll_ext_cntl = aty_ld_pll(PLL_EXT_CNTL, info); in aty_init_pll_ct()
346 info->xclk_post_div_real = postdividers[pll_ext_cntl & 7]; in aty_init_pll_ct()
347 mclk_fb_div = aty_ld_pll(MCLK_FB_DIV, info); in aty_init_pll_ct()
350 info->mclk_fb_div = mclk_fb_div; in aty_init_pll_ct()
354 pll_ref_div = info->pll_per*2*255/info->ref_clk_per; in aty_init_pll_ct()
355 info->pll_ref_div = pll_ref_div; in aty_init_pll_ct()
358 q = info->ref_clk_per*pll_ref_div*4/info->xclk_per; /* actually 8*q */ in aty_init_pll_ct()
367 info->xclk_post_div_real = postdividers[xpost_div]; in aty_init_pll_ct()
368 info->mclk_fb_div = q*info->xclk_post_div_real/8; in aty_init_pll_ct()
370 if (M64_HAS(SDRAM_MAGIC_PLL) && (info->ram_type >= SDRAM)) in aty_init_pll_ct()
382 if (info->mclk_per == info->xclk_per) in aty_init_pll_ct()
391 q = info->ref_clk_per*pll_ref_div*4/info->mclk_per; /* actually 8*q */ in aty_init_pll_ct()
410 aty_st_pll(SCLK_FB_DIV, sclk_fb_div, info); in aty_init_pll_ct()
411 aty_st_pll(SPLL_CNTL2, spll_cntl2, info); in aty_init_pll_ct()
421 aty_st_pll(PLL_REF_DIV, pll_ref_div, info); in aty_init_pll_ct()
422 aty_st_pll(PLL_GEN_CNTL, pll_gen_cntl, info); in aty_init_pll_ct()
423 aty_st_pll(MCLK_FB_DIV, info->mclk_fb_div, info); in aty_init_pll_ct()
424 aty_st_pll(PLL_EXT_CNTL, pll_ext_cntl, info); in aty_init_pll_ct()
427 aty_st_pll(EXT_VPLL_CNTL, aty_ld_pll(EXT_VPLL_CNTL, info) & in aty_init_pll_ct()
429 EXT_VPLL_INSYNC), info); in aty_init_pll_ct()
435 aty_st_pll(DLL_CNTL, 0x80, info); in aty_init_pll_ct()
436 else if (info->ram_type >= SDRAM) in aty_init_pll_ct()
437 aty_st_pll(DLL_CNTL, 0xa6, info); in aty_init_pll_ct()
439 aty_st_pll(DLL_CNTL, 0xa0, info); in aty_init_pll_ct()
440 aty_st_pll(VFC_CNTL, 0x1b, info); in aty_init_pll_ct()