Lines Matching refs:NCR_write8
457 NCR_write8(ISTAT_REG, ISTAT_ABRT); in ncr_halt()
472 NCR_write8(ISTAT_REG, 0); in ncr_halt()
531 NCR_write8(SCNTL1_REG, SCNTL1_RST); /* Reset the bus */ in sim710_soft_reset()
533 NCR_write8(SCNTL1_REG, 0); in sim710_soft_reset()
537 NCR_write8(ISTAT_REG, ISTAT_10_SRST); /* Reset the chip */ in sim710_soft_reset()
539 NCR_write8(ISTAT_REG, 0); in sim710_soft_reset()
544 NCR_write8(DCNTL_REG, DCNTL_10_COM | DCNTL_700_CF_3); in sim710_soft_reset()
545 NCR_write8(CTEST7_REG, CTEST7_10_CDIS|CTEST7_STD); in sim710_soft_reset()
546 NCR_write8(DMODE_REG, DMODE_10_BL_8 | DMODE_10_FC2); in sim710_soft_reset()
547 NCR_write8(SCID_REG, 1 << host->this_id); in sim710_soft_reset()
548 NCR_write8(SBCL_REG, 0); in sim710_soft_reset()
549 NCR_write8(SXFER_REG, 0); in sim710_soft_reset()
550 NCR_write8(SCNTL1_REG, SCNTL1_ESR_700); in sim710_soft_reset()
551 NCR_write8(SCNTL0_REG, SCNTL0_EPC | SCNTL0_EPG_700 | SCNTL0_ARB1 | in sim710_soft_reset()
554 NCR_write8(DIEN_REG, DIEN_700_BF | in sim710_soft_reset()
557 NCR_write8(SIEN_REG_700, in sim710_soft_reset()
744 NCR_write8(SOCL_REG, 0); /* Negate ATN */ in handle_phase_mismatch()
838 NCR_write8 (CTEST8_REG, CTEST8_10_CLF); in handle_phase_mismatch()
1033 NCR_write8(ISTAT_REG, ISTAT_10_SIGP); in run_command()