Lines Matching refs:BIT
77 #define BIT(x) (1UL << (x)) macro
104 # define IRQSTATUS_LATCHED_MSG BIT(0)
105 # define IRQSTATUS_LATCHED_IO BIT(1)
106 # define IRQSTATUS_LATCHED_CD BIT(2)
107 # define IRQSTATUS_LATCHED_BUS_FREE BIT(3)
108 # define IRQSTATUS_RESELECT_OCCUER BIT(4)
109 # define IRQSTATUS_PHASE_CHANGE_IRQ BIT(5)
110 # define IRQSTATUS_SCSIRESET_IRQ BIT(6)
111 # define IRQSTATUS_TIMER_IRQ BIT(7)
112 # define IRQSTATUS_FIFO_SHLD_IRQ BIT(8)
113 # define IRQSTATUS_PCI_IRQ BIT(9)
114 # define IRQSTATUS_BMCNTERR_IRQ BIT(10)
115 # define IRQSTATUS_AUTOSCSI_IRQ BIT(11)
116 # define PCI_IRQ_MASK BIT(12)
117 # define TIMER_IRQ_MASK BIT(13)
118 # define FIFO_IRQ_MASK BIT(14)
119 # define SCSI_IRQ_MASK BIT(15)
135 # define CB_MMIO_MODE BIT(0)
136 # define CB_IO_MODE BIT(1)
137 # define BM_TEST BIT(2)
138 # define BM_TEST_DIR BIT(3)
139 # define DUAL_EDGE_ENABLE BIT(4)
140 # define NO_TRANSFER_TO_HOST BIT(5)
141 # define TRANSFER_GO BIT(7)
142 # define BLIEND_MODE BIT(8)
143 # define BM_START BIT(9)
144 # define ADVANCED_BM_WRITE BIT(10)
145 # define BM_SINGLE_MODE BIT(11)
146 # define FIFO_TRUE_FULL BIT(12)
147 # define FIFO_TRUE_EMPTY BIT(13)
148 # define ALL_COUNTER_CLR BIT(14)
149 # define FIFOTEST BIT(15)
155 # define TIMER_STOP BIT(8)
162 # define FIFO_EMPTY_SHLD_FLAG BIT(14)
163 # define FIFO_FULL_SHLD_FLAG BIT(15)
166 # define SREQSMPLRATE_RATE0 BIT(0)
167 # define SREQSMPLRATE_RATE1 BIT(1)
168 # define SAMPLING_ENABLE BIT(2)
174 # define BUSCTL_SEL BIT(0)
175 # define BUSCTL_RST BIT(1)
176 # define BUSCTL_DATAOUT_ENB BIT(2)
177 # define BUSCTL_ATN BIT(3)
178 # define BUSCTL_ACK BIT(4)
179 # define BUSCTL_BSY BIT(5)
180 # define AUTODIRECTION BIT(6)
181 # define ACKENB BIT(7)
184 # define ACK_COUNTER_CLR BIT(0)
185 # define SREQ_COUNTER_CLR BIT(1)
186 # define FIFO_HOST_POINTER_CLR BIT(2)
187 # define FIFO_REST_COUNT_CLR BIT(3)
188 # define BM_COUNTER_CLR BIT(4)
189 # define SAVED_ACK_CLR BIT(5)
198 # define BUSMON_MSG BIT(0)
199 # define BUSMON_IO BIT(1)
200 # define BUSMON_CD BIT(2)
201 # define BUSMON_BSY BIT(3)
202 # define BUSMON_ACK BIT(4)
203 # define BUSMON_REQ BIT(5)
204 # define BUSMON_SEL BIT(6)
205 # define BUSMON_ATN BIT(7)
210 # define PARITY_CHECK_ENABLE BIT(0)
211 # define PARITY_ERROR_CLEAR BIT(1)
214 # define PARITY_ERROR_NORMAL BIT(1)
215 # define PARITY_ERROR_LSB BIT(1)
216 # define PARITY_ERROR_MSB BIT(2)
221 # define CLEAR_CDB_FIFO_POINTER BIT(0)
222 # define AUTO_COMMAND_PHASE BIT(1)
223 # define AUTOSCSI_START BIT(2)
224 # define AUTOSCSI_RESTART BIT(3)
225 # define AUTO_PARAMETER BIT(4)
226 # define AUTO_ATN BIT(5)
227 # define AUTO_MSGIN_00_OR_04 BIT(6)
228 # define AUTO_MSGIN_02 BIT(7)
229 # define AUTO_MSGIN_03 BIT(8)
232 # define ARBIT_GO BIT(0)
233 # define ARBIT_CLEAR BIT(1)
237 # define ARBIT_WIN BIT(1)
238 # define ARBIT_FAIL BIT(2)
239 # define AUTO_PARAMETER_VALID BIT(3)
240 # define SGT_VALID BIT(4)
252 # define SCAM_MSG BIT(0)
253 # define SCAM_IO BIT(1)
254 # define SCAM_CD BIT(2)
255 # define SCAM_BSY BIT(3)
256 # define SCAM_SEL BIT(4)
257 # define SCAM_XFEROK BIT(5)
260 # define SD0 BIT(0)
261 # define SD1 BIT(1)
262 # define SD2 BIT(2)
263 # define SD3 BIT(3)
264 # define SD4 BIT(4)
265 # define SD5 BIT(5)
266 # define SD6 BIT(6)
267 # define SD7 BIT(7)
278 # define SGTEND BIT(31) /* Last SGT marker */
284 # define COMMAND_PHASE BIT(0)
285 # define DATA_IN_PHASE BIT(1)
286 # define DATA_OUT_PHASE BIT(2)
287 # define MSGOUT_PHASE BIT(3)
288 # define STATUS_PHASE BIT(4)
289 # define ILLEGAL_PHASE BIT(5)
290 # define BUS_FREE_OCCUER BIT(6)
291 # define MSG_IN_OCCUER BIT(7)
292 # define MSG_OUT_OCCUER BIT(8)
293 # define SELECTION_TIMEOUT BIT(9)
294 # define MSGIN_00_VALID BIT(10)
295 # define MSGIN_02_VALID BIT(11)
296 # define MSGIN_03_VALID BIT(12)
297 # define MSGIN_04_VALID BIT(13)
298 # define AUTOSCSI_BUSY BIT(15)
303 # define MSGOUT_COUNT_MASK (BIT(0)|BIT(1))
304 # define MSGOUT_VALID BIT(7)
320 # define CLOCK_2 BIT(0) /* MCLK/2 */
321 # define CLOCK_4 BIT(1) /* MCLK/4 */
322 # define PCICLK BIT(7) /* PCICLK (33MHz) */
325 # define BPWR BIT(0)
326 # define SENSE BIT(1) /* Read Only */
331 # define LED_OFF BIT(0)
334 # define IRQSELECT_RESELECT_IRQ BIT(0)
335 # define IRQSELECT_PHASE_CHANGE_IRQ BIT(1)
336 # define IRQSELECT_SCSIRESET_IRQ BIT(2)
337 # define IRQSELECT_TIMER_IRQ BIT(3)
338 # define IRQSELECT_FIFO_SHLD_IRQ BIT(4)
339 # define IRQSELECT_TARGET_ABORT_IRQ BIT(5)
340 # define IRQSELECT_MASTER_ABORT_IRQ BIT(6)
341 # define IRQSELECT_SERR_IRQ BIT(7)
342 # define IRQSELECT_PERR_IRQ BIT(8)
343 # define IRQSELECT_BMCNTERR_IRQ BIT(9)
344 # define IRQSELECT_AUTO_SCSI_SEQ_IRQ BIT(10)
347 # define OLD_MSG BIT(0)
348 # define OLD_IO BIT(1)
349 # define OLD_CD BIT(2)
350 # define OLD_BUSY BIT(3)
356 # define ROM_WRITE_ENB BIT(0)
357 # define IO_ACCESS_ENB BIT(1)
358 # define ROM_ADR_CLEAR BIT(2)
365 # define OEM0 BIT(1) /* OEM select */ /* 00=I-O DATA, 01=KME, 10=Workbit, 11=Ext ROM */
366 # define OEM1 BIT(2) /* OEM select */
367 # define OPTB BIT(3) /* KME mode select */
368 # define OPTC BIT(4) /* KME mode select */
369 # define OPTD BIT(5) /* KME mode select */
370 # define OPTE BIT(6) /* KME mode select */
371 # define OPTF BIT(7) /* Power management */
375 # define SCSI_DIRECTION_DETECTOR_SELECT BIT(0)
376 # define SCSI2_HOST_DIRECTION_VALID BIT(1) /* Read only */
377 # define HOST2_SCSI_DIRECTION_VALID BIT(2) /* Read only */
378 # define DELAYED_BMSTART BIT(3)
379 # define MASTER_TERMINATION_SELECT BIT(4)
380 # define BMREQ_NEGATE_TIMING_SEL BIT(5)
381 # define AUTOSEL_TIMING_SEL BIT(6)
382 # define MISC_MABORT_MASK BIT(7)
383 # define BMSTOP_CHANGE2_NONDATA_PHASE BIT(8)
386 # define BM_CYCLE0 BIT(0)
387 # define BM_CYCLE1 BIT(1)
388 # define BM_FRAME_ASSERT_TIMING BIT(2)
389 # define BM_IRDY_ASSERT_TIMING BIT(3)
390 # define BM_SINGLE_BUS_MASTER BIT(4)
391 # define MEMRD_CMD0 BIT(5)
392 # define SGT_AUTO_PARA_MEMED_CMD BIT(6)
393 # define MEMRD_CMD1 BIT(7)
397 # define SREQ_EDGH_SELECT BIT(0)
400 # define REQCNT_UP BIT(0)
401 # define ACKCNT_UP BIT(1)
402 # define BMADR_UP BIT(4)
403 # define BMCNT_UP BIT(5)
404 # define SGT_CNT_UP BIT(7)
413 # define SROM_CTL BIT(0)
414 # define SROM_ENABLE BIT(1)
415 # define SROM_DATA BIT(2)
495 #define NSP32_TRANSFER_BUSMASTER BIT(0)
496 #define NSP32_TRANSFER_MMIO BIT(1) /* Not supported yet */
497 #define NSP32_TRANSFER_PIO BIT(2) /* Not supported yet */
506 #define DISCPRIV_OK BIT(0) /* DISCPRIV Enable mode */
507 #define MSGIN03 BIT(1) /* Auto Msg In 03 Flag */
542 #define SDTR_INITIATOR BIT(0) /* sending SDTR from initiator */
543 #define SDTR_TARGET BIT(1) /* sending SDTR from target */
544 #define SDTR_DONE BIT(2) /* exchanging SDTR has been processed */