Lines Matching refs:DFCNTRL
724 mvi DFCNTRL, (PRELOADEN|SCSIEN|HDMAEN);
729 mvi DFCNTRL, SCSIEN;
732 test DFCNTRL, SCSIEN jnz .;
1313 test DFCNTRL, HDMAENACK jz return;
1345 or DFCNTRL, PRELOADEN|HDMAEN|SCSIENWRDIS;
1347 or DFCNTRL, PRELOADEN|HDMAEN;
1365 mvi DFCNTRL, (PRELOADEN|SCSIEN|HDMAEN);
1447 test DFCNTRL, SCSIEN jnz data_group_dma_loop;
1464 test DFCNTRL, DIRECTION jnz data_phase_finish;
1467 or DFCNTRL, FIFOFLUSH;
1511 test DFCNTRL, DIRECTION jz target_ITloop;
1620 * (DIRECTION set in DFCNTRL). The delay is performed by
1643 test DFCNTRL, DIRECTION jz interrupt_return;
1644 and DFCNTRL, ~SCSIEN;
1649 or DFCNTRL, SCSIEN;
1708 mvi DFCNTRL, PRELOADEN|SCSIEN|HDMAEN;
1730 mvi DFCNTRL, (PRELOADEN|SCSIEN|HDMAEN);
1789 or DFCNTRL, FIFOFLUSH;
1797 test DFCNTRL, DIRECTION jnz pkt_saveptrs_check_status;
1887 or DFCNTRL, FIFOFLUSH;
1994 mvi DFCNTRL, (HDMAEN|SCSIEN|PRELOADEN);
2000 or DFCNTRL, PRELOADEN;