87 #define SIFREADB(reg) (inb(dev->base_addr + ((reg<0x8)?reg:reg-0x8)))
88 #define SIFWRITEB(val, reg) (outb(val, dev->base_addr + ((reg<0x8)?reg:reg-0x8)))
89 #define SIFREADW(reg) (inw(dev->base_addr + ((reg<0x8)?reg:reg-0x8)))
90 #define SIFWRITEW(val, reg) (outw(val, dev->base_addr + ((reg<0x8)?reg:reg-0x8)))
216 		dev->base_addr = 0x0a20 +   in madgemc_probe()
236 		if (!request_region(dev->base_addr, MADGEMC_IO_EXTENT,   in madgemc_probe()
238 …ble to setup Smart MC in slot %d because of I/O base conflict at 0x%04lx\n", slot, dev->base_addr);  in madgemc_probe()
239 			dev->base_addr += MADGEMC_SIF_OFFSET;  in madgemc_probe()
242 		dev->base_addr += MADGEMC_SIF_OFFSET;  in madgemc_probe()
301 		       dev->base_addr, dev->irq);  in madgemc_probe()
334 		outb(0, dev->base_addr + MC_CONTROL_REG0); /* sanity */  in madgemc_probe()
358 			release_region(dev->base_addr-MADGEMC_SIF_OFFSET,   in madgemc_probe()
394 			release_region(dev->base_addr-MADGEMC_SIF_OFFSET,   in madgemc_probe()
409 		release_region(dev->base_addr-MADGEMC_SIF_OFFSET,   in madgemc_probe()
474 	pending = inb(dev->base_addr + MC_CONTROL_REG0);  in madgemc_interrupt()
489 			reg1 = inb(dev->base_addr + MC_CONTROL_REG1);  in madgemc_interrupt()
491 			     dev->base_addr + MC_CONTROL_REG1);  in madgemc_interrupt()
492 			outb(reg1, dev->base_addr + MC_CONTROL_REG1);  in madgemc_interrupt()
520 	reg1 = inb(dev->base_addr + MC_CONTROL_REG1);  in madgemc_setnselout_pins()
526 	outb(reg1, dev->base_addr + MC_CONTROL_REG1);  in madgemc_setnselout_pins()
546 	reg1 = inb(dev->base_addr + MC_CONTROL_REG1);  in madgemc_setregpage()
549 		     dev->base_addr + MC_CONTROL_REG1);  in madgemc_setregpage()
553 		     dev->base_addr + MC_CONTROL_REG1);  in madgemc_setregpage()
555 	reg1 = inb(dev->base_addr + MC_CONTROL_REG1);  in madgemc_setregpage()
569 	reg0 = inb(dev->base_addr + MC_CONTROL_REG0);  in madgemc_setsifsel()
572 		     dev->base_addr + MC_CONTROL_REG0);  in madgemc_setsifsel()
575 		     dev->base_addr + MC_CONTROL_REG0);  in madgemc_setsifsel()
577 	reg0 = inb(dev->base_addr + MC_CONTROL_REG0);  in madgemc_setsifsel()
593 	reg1 = inb(dev->base_addr + MC_CONTROL_REG1);  in madgemc_setint()
596 		     dev->base_addr + MC_CONTROL_REG1);  in madgemc_setint()
599 		     dev->base_addr + MC_CONTROL_REG1);  in madgemc_setint()
612 	     dev->base_addr + MC_CONTROL_REG7);  in madgemc_setcabletype()
621 	outb(0, dev->base_addr + MC_CONTROL_REG1); /* pull SRESET low */  in madgemc_chipset_init()
625 	outb(MC_CONTROL_REG1_NSRESET, dev->base_addr + MC_CONTROL_REG1);  in madgemc_chipset_init()
683 	ioaddr = card->dev->base_addr;  in madgemc_read_rom()
754 		len += sprintf(buf+len, "IO Port: 0x%04lx\n", dev->base_addr);  in madgemc_mcaproc()
797 		release_region(dev->base_addr-MADGEMC_SIF_OFFSET, MADGEMC_IO_EXTENT);  in cleanup_module()