Lines Matching refs:base_addr
588 dev->base_addr = pci_io_base; in TLan_probe1()
606 dev->base_addr = ioaddr; in TLan_probe1()
663 (int) dev->base_addr, in TLan_probe1()
694 release_region( dev->base_addr, 0x10); in TLan_Eisa_Cleanup()
926 priv->tlanRev = TLan_DioRead8( dev->base_addr, TLAN_DEF_REVISION ); in TLan_Open()
1103 outl( tail_list_phys, dev->base_addr + TLAN_CH_PARM ); in TLan_StartTx()
1104 outl( TLAN_HC_GO, dev->base_addr + TLAN_HOST_CMD ); in TLan_StartTx()
1163 host_int = inw( dev->base_addr + TLAN_HOST_INT ); in TLan_HandleInterrupt()
1164 outw( host_int, dev->base_addr + TLAN_HOST_INT ); in TLan_HandleInterrupt()
1172 outl( host_cmd, dev->base_addr + TLAN_HOST_CMD ); in TLan_HandleInterrupt()
1205 outl( TLAN_HC_AD_RST, dev->base_addr + TLAN_HOST_CMD ); in TLan_Close()
1248 TLan_PrintDio( dev->base_addr ); in TLan_GetStats()
1295 tmp = TLan_DioRead8( dev->base_addr, TLAN_NET_CMD ); in TLan_SetMulticastList()
1296 TLan_DioWrite8( dev->base_addr, TLAN_NET_CMD, tmp | TLAN_NET_CMD_CAF ); in TLan_SetMulticastList()
1298 tmp = TLan_DioRead8( dev->base_addr, TLAN_NET_CMD ); in TLan_SetMulticastList()
1299 TLan_DioWrite8( dev->base_addr, TLAN_NET_CMD, tmp & ~TLAN_NET_CMD_CAF ); in TLan_SetMulticastList()
1303 TLan_DioWrite32( dev->base_addr, TLAN_HASH_1, 0xFFFFFFFF ); in TLan_SetMulticastList()
1304 TLan_DioWrite32( dev->base_addr, TLAN_HASH_2, 0xFFFFFFFF ); in TLan_SetMulticastList()
1320 TLan_DioWrite32( dev->base_addr, TLAN_HASH_1, hash1 ); in TLan_SetMulticastList()
1321 TLan_DioWrite32( dev->base_addr, TLAN_HASH_2, hash2 ); in TLan_SetMulticastList()
1432 outl(head_list_phys, dev->base_addr + TLAN_CH_PARM ); in TLan_HandleTxEOF()
1440 TLan_DioWrite8( dev->base_addr, TLAN_LED_REG, TLAN_LED_LINK | TLAN_LED_ACT ); in TLan_HandleTxEOF()
1605 outl(head_list_phys, dev->base_addr + TLAN_CH_PARM ); in TLan_HandleRxEOF()
1611 TLan_DioWrite8( dev->base_addr, TLAN_LED_REG, TLAN_LED_LINK | TLAN_LED_ACT ); in TLan_HandleRxEOF()
1694 outl( head_list_phys, dev->base_addr + TLAN_CH_PARM ); in TLan_HandleTxEOC()
1741 error = inl( dev->base_addr + TLAN_CH_PARM ); in TLan_HandleStatusCheck()
1744 outl( TLAN_HC_AD_RST, dev->base_addr + TLAN_HOST_CMD ); in TLan_HandleStatusCheck()
1754 net_sts = TLan_DioRead8( dev->base_addr, TLAN_NET_STS ); in TLan_HandleStatusCheck()
1756 TLan_DioWrite8( dev->base_addr, TLAN_NET_STS, net_sts ); in TLan_HandleStatusCheck()
1812 outl( head_list_phys, dev->base_addr + TLAN_CH_PARM ); in TLan_HandleRxEOC()
1901 TLan_DioWrite8( dev->base_addr, TLAN_LED_REG, TLAN_LED_LINK ); in TLan_Timer()
2133 outw( TLAN_GOOD_TX_FRMS, dev->base_addr + TLAN_DIO_ADR ); in TLan_ReadAndClearStats()
2134 tx_good = inb( dev->base_addr + TLAN_DIO_DATA ); in TLan_ReadAndClearStats()
2135 tx_good += inb( dev->base_addr + TLAN_DIO_DATA + 1 ) << 8; in TLan_ReadAndClearStats()
2136 tx_good += inb( dev->base_addr + TLAN_DIO_DATA + 2 ) << 16; in TLan_ReadAndClearStats()
2137 tx_under = inb( dev->base_addr + TLAN_DIO_DATA + 3 ); in TLan_ReadAndClearStats()
2139 outw( TLAN_GOOD_RX_FRMS, dev->base_addr + TLAN_DIO_ADR ); in TLan_ReadAndClearStats()
2140 rx_good = inb( dev->base_addr + TLAN_DIO_DATA ); in TLan_ReadAndClearStats()
2141 rx_good += inb( dev->base_addr + TLAN_DIO_DATA + 1 ) << 8; in TLan_ReadAndClearStats()
2142 rx_good += inb( dev->base_addr + TLAN_DIO_DATA + 2 ) << 16; in TLan_ReadAndClearStats()
2143 rx_over = inb( dev->base_addr + TLAN_DIO_DATA + 3 ); in TLan_ReadAndClearStats()
2145 outw( TLAN_DEFERRED_TX, dev->base_addr + TLAN_DIO_ADR ); in TLan_ReadAndClearStats()
2146 def_tx = inb( dev->base_addr + TLAN_DIO_DATA ); in TLan_ReadAndClearStats()
2147 def_tx += inb( dev->base_addr + TLAN_DIO_DATA + 1 ) << 8; in TLan_ReadAndClearStats()
2148 crc = inb( dev->base_addr + TLAN_DIO_DATA + 2 ); in TLan_ReadAndClearStats()
2149 code = inb( dev->base_addr + TLAN_DIO_DATA + 3 ); in TLan_ReadAndClearStats()
2151 outw( TLAN_MULTICOL_FRMS, dev->base_addr + TLAN_DIO_ADR ); in TLan_ReadAndClearStats()
2152 multi_col = inb( dev->base_addr + TLAN_DIO_DATA ); in TLan_ReadAndClearStats()
2153 multi_col += inb( dev->base_addr + TLAN_DIO_DATA + 1 ) << 8; in TLan_ReadAndClearStats()
2154 single_col = inb( dev->base_addr + TLAN_DIO_DATA + 2 ); in TLan_ReadAndClearStats()
2155 single_col += inb( dev->base_addr + TLAN_DIO_DATA + 3 ) << 8; in TLan_ReadAndClearStats()
2157 outw( TLAN_EXCESSCOL_FRMS, dev->base_addr + TLAN_DIO_ADR ); in TLan_ReadAndClearStats()
2158 excess_col = inb( dev->base_addr + TLAN_DIO_DATA ); in TLan_ReadAndClearStats()
2159 late_col = inb( dev->base_addr + TLAN_DIO_DATA + 1 ); in TLan_ReadAndClearStats()
2160 loss = inb( dev->base_addr + TLAN_DIO_DATA + 2 ); in TLan_ReadAndClearStats()
2214 data = inl(dev->base_addr + TLAN_HOST_CMD); in TLan_ResetAdapter()
2216 outl(data, dev->base_addr + TLAN_HOST_CMD); in TLan_ResetAdapter()
2222 data = inl(dev->base_addr + TLAN_HOST_CMD); in TLan_ResetAdapter()
2224 outl(data, dev->base_addr + TLAN_HOST_CMD); in TLan_ResetAdapter()
2229 TLan_DioWrite32( dev->base_addr, (u16) i, 0 ); in TLan_ResetAdapter()
2235 TLan_DioWrite16( dev->base_addr, TLAN_NET_CONFIG, (u16) data ); in TLan_ResetAdapter()
2239 outl( TLAN_HC_LD_TMR | 0x3f, dev->base_addr + TLAN_HOST_CMD ); in TLan_ResetAdapter()
2240 outl( TLAN_HC_LD_THR | 0x9, dev->base_addr + TLAN_HOST_CMD ); in TLan_ResetAdapter()
2244 outw( TLAN_NET_SIO, dev->base_addr + TLAN_DIO_ADR ); in TLan_ResetAdapter()
2245 addr = dev->base_addr + TLAN_DIO_DATA + TLAN_NET_SIO; in TLan_ResetAdapter()
2252 TLan_DioWrite8( dev->base_addr, TLAN_INT_DIS, data8 ); in TLan_ResetAdapter()
2260 TLan_DioWrite8( dev->base_addr, TLAN_ACOMMIT, 0x0a ); in TLan_ResetAdapter()
2262 TLan_DioWrite8( dev->base_addr, TLAN_ACOMMIT, 0x00 ); in TLan_ResetAdapter()
2265 TLan_DioWrite8( dev->base_addr, TLAN_ACOMMIT, 0x08 ); in TLan_ResetAdapter()
2272 TLan_DioWrite16( dev->base_addr, TLAN_NET_CONFIG, (u16) data ); in TLan_ResetAdapter()
2305 TLan_DioWrite8( dev->base_addr, TLAN_NET_CMD, data ); in TLan_FinishReset()
2310 TLan_DioWrite8( dev->base_addr, TLAN_NET_MASK, data ); in TLan_FinishReset()
2311 TLan_DioWrite16( dev->base_addr, TLAN_MAX_RX, ((1536)+7)&~7 ); in TLan_FinishReset()
2344 TLan_DioWrite8( dev->base_addr, TLAN_LED_REG, TLAN_LED_LINK ); in TLan_FinishReset()
2353 TLan_DioWrite8( dev->base_addr, TLAN_LED_REG, TLAN_LED_LINK ); in TLan_FinishReset()
2361 sio = TLan_DioRead8( dev->base_addr, TLAN_NET_SIO ); in TLan_FinishReset()
2363 TLan_DioWrite8( dev->base_addr, TLAN_NET_SIO, sio ); in TLan_FinishReset()
2369 outb( ( TLAN_HC_INT_ON >> 8 ), dev->base_addr + TLAN_HOST_CMD + 1 ); in TLan_FinishReset()
2371 outb( ( TLAN_HC_REQ_INT >> 8 ), dev->base_addr + TLAN_HOST_CMD + 1 ); in TLan_FinishReset()
2373 outl( priv->rxListDMA, dev->base_addr + TLAN_CH_PARM ); in TLan_FinishReset()
2374 outl( TLAN_HC_GO | TLAN_HC_RT, dev->base_addr + TLAN_HOST_CMD ); in TLan_FinishReset()
2416 TLan_DioWrite8( dev->base_addr, TLAN_AREG_0 + areg + i, mac[i] ); in TLan_SetMac()
2419 TLan_DioWrite8( dev->base_addr, TLAN_AREG_0 + areg + i, 0 ); in TLan_SetMac()
2553 TLan_MiiSync( dev->base_addr ); in TLan_PhyPowerDown()
2556 TLan_MiiSync( dev->base_addr ); in TLan_PhyPowerDown()
2577 TLan_MiiSync( dev->base_addr ); in TLan_PhyPowerUp()
2580 TLan_MiiSync(dev->base_addr); in TLan_PhyPowerUp()
2601 TLan_MiiSync( dev->base_addr ); in TLan_PhyReset()
2675 TLan_DioWrite16( dev->base_addr, TLAN_NET_CONFIG, data ); in TLan_PhyStartLink()
2750 TLan_DioWrite16( dev->base_addr, TLAN_NET_CONFIG, data ); in TLan_PhyFinishAutoNeg()
2874 outw(TLAN_NET_SIO, dev->base_addr + TLAN_DIO_ADR); in TLan_MiiReadReg()
2875 sio = dev->base_addr + TLAN_DIO_DATA + TLAN_NET_SIO; in TLan_MiiReadReg()
2880 TLan_MiiSync(dev->base_addr); in TLan_MiiReadReg()
2886 TLan_MiiSendData( dev->base_addr, 0x1, 2 ); /* Start ( 01b ) */ in TLan_MiiReadReg()
2887 TLan_MiiSendData( dev->base_addr, 0x2, 2 ); /* Read ( 10b ) */ in TLan_MiiReadReg()
2888 TLan_MiiSendData( dev->base_addr, phy, 5 ); /* Device # */ in TLan_MiiReadReg()
2889 TLan_MiiSendData( dev->base_addr, reg, 5 ); /* Register # */ in TLan_MiiReadReg()
3041 outw(TLAN_NET_SIO, dev->base_addr + TLAN_DIO_ADR); in TLan_MiiWriteReg()
3042 sio = dev->base_addr + TLAN_DIO_DATA + TLAN_NET_SIO; in TLan_MiiWriteReg()
3047 TLan_MiiSync( dev->base_addr ); in TLan_MiiWriteReg()
3053 TLan_MiiSendData( dev->base_addr, 0x1, 2 ); /* Start ( 01b ) */ in TLan_MiiWriteReg()
3054 TLan_MiiSendData( dev->base_addr, 0x1, 2 ); /* Write ( 01b ) */ in TLan_MiiWriteReg()
3055 TLan_MiiSendData( dev->base_addr, phy, 5 ); /* Device # */ in TLan_MiiWriteReg()
3056 TLan_MiiSendData( dev->base_addr, reg, 5 ); /* Register # */ in TLan_MiiWriteReg()
3058 TLan_MiiSendData( dev->base_addr, 0x2, 2 ); /* Send ACK */ in TLan_MiiWriteReg()
3059 TLan_MiiSendData( dev->base_addr, val, 16 ); /* Send Data */ in TLan_MiiWriteReg()
3272 TLan_EeSendStart( dev->base_addr ); in TLan_EeReadByte()
3273 err = TLan_EeSendByte( dev->base_addr, 0xA0, TLAN_EEPROM_ACK ); in TLan_EeReadByte()
3279 err = TLan_EeSendByte( dev->base_addr, ee_addr, TLAN_EEPROM_ACK ); in TLan_EeReadByte()
3285 TLan_EeSendStart( dev->base_addr ); in TLan_EeReadByte()
3286 err = TLan_EeSendByte( dev->base_addr, 0xA1, TLAN_EEPROM_ACK ); in TLan_EeReadByte()
3292 TLan_EeReceiveByte( dev->base_addr, data, TLAN_EEPROM_STOP ); in TLan_EeReadByte()