Lines Matching refs:TITAN_GE_WRITE
208 TITAN_GE_WRITE((TITAN_GE_GMII_CONFIG_MODE + in titan_ge_gmii_config()
212 TITAN_GE_WRITE((TITAN_GE_GMII_CONFIG_MODE + in titan_ge_gmii_config()
219 TITAN_GE_WRITE((TITAN_GE_GMII_CONFIG_MODE + in titan_ge_gmii_config()
223 TITAN_GE_WRITE((TITAN_GE_GMII_CONFIG_MODE + in titan_ge_gmii_config()
230 TITAN_GE_WRITE((TITAN_GE_GMII_CONFIG_GENERAL + in titan_ge_gmii_config()
252 TITAN_GE_WRITE((TITAN_GE_TMAC_CONFIG_1 + in titan_ge_enable_tx()
284 TITAN_GE_WRITE((TITAN_GE_TMAC_STATION_HI + (port << 12)), in titan_ge_update_afx()
286 TITAN_GE_WRITE((TITAN_GE_TMAC_STATION_MID + (port << 12)), in titan_ge_update_afx()
288 TITAN_GE_WRITE((TITAN_GE_TMAC_STATION_LOW + (port << 12)), in titan_ge_update_afx()
291 TITAN_GE_WRITE((TITAN_GE_RMAC_STATION_HI + (port << 12)), in titan_ge_update_afx()
293 TITAN_GE_WRITE((TITAN_GE_RMAC_STATION_MID + (port << 12)), in titan_ge_update_afx()
295 TITAN_GE_WRITE((TITAN_GE_RMAC_STATION_LOW + (port << 12)), in titan_ge_update_afx()
298 TITAN_GE_WRITE((0x112c | (port << 12)), 0x1); in titan_ge_update_afx()
302 TITAN_GE_WRITE((TITAN_GE_AFX_ADDRS_FILTER_CTRL_2 + in titan_ge_update_afx()
307 TITAN_GE_WRITE((TITAN_GE_AFX_ADDRS_FILTER_CTRL_0 + in titan_ge_update_afx()
311 TITAN_GE_WRITE((TITAN_GE_AFX_EXACT_MATCH_LOW + (port << 12)), in titan_ge_update_afx()
313 TITAN_GE_WRITE((TITAN_GE_AFX_EXACT_MATCH_MID + (port << 12)), in titan_ge_update_afx()
315 TITAN_GE_WRITE((TITAN_GE_AFX_EXACT_MATCH_HIGH + (port << 12)), in titan_ge_update_afx()
319 TITAN_GE_WRITE((TITAN_GE_AFX_EXACT_MATCH_VID + in titan_ge_update_afx()
410 TITAN_GE_WRITE(TITAN_GE_XDMA_CONFIG, reg_data); in titan_ge_xdma_reset()
416 TITAN_GE_WRITE(TITAN_GE_XDMA_CONFIG, reg_data); in titan_ge_xdma_reset()
530 TITAN_GE_WRITE(TITAN_GE_INTR_XDMA_IE, ack);
559 TITAN_GE_WRITE((TITAN_GE_CHANNEL0_INTERRUPT +
624 TITAN_GE_WRITE((TITAN_GE_AFX_ADDRS_FILTER_CTRL_1 +
627 TITAN_GE_WRITE((TITAN_GE_AFX_MULTICAST_HASH_LOW +
629 TITAN_GE_WRITE((TITAN_GE_AFX_MULTICAST_HASH_MIDLOW +
631 TITAN_GE_WRITE((TITAN_GE_AFX_MULTICAST_HASH_MIDHI +
633 TITAN_GE_WRITE((TITAN_GE_AFX_MULTICAST_HASH_HI +
761 TITAN_GE_WRITE(TITAN_GE_CHANNEL0_CONFIG, reg_data);
767 TITAN_GE_WRITE(TITAN_GE_CHANNEL0_CONFIG, reg_data);
772 TITAN_GE_WRITE(TITAN_GE_CHANNEL0_CONFIG, reg_data);
778 TITAN_GE_WRITE(TITAN_GE_CHANNEL0_CONFIG, reg_data);
797 TITAN_GE_WRITE(0x0004, reg_data);
800 TITAN_GE_WRITE(0x0004, reg_data);
807 TITAN_GE_WRITE(0x000c, 0x00001100);
809 TITAN_GE_WRITE(0x000c, 0x00000100); /* No WCIMODE */
811 TITAN_GE_WRITE(TITAN_GE_TSB_CTRL_1, reg_data);
814 TITAN_GE_WRITE(0x00f8, 0x8);
817 TITAN_GE_WRITE(0x0068, 0x4);
826 TITAN_GE_WRITE((TITAN_GE_CHANNEL0_TX_DESC + (port_num << 8)),
828 TITAN_GE_WRITE((TITAN_GE_CHANNEL0_RX_DESC + (port_num << 8)),
839 TITAN_GE_WRITE(TITAN_GE_XDMA_CONFIG, reg_data);
845 TITAN_GE_WRITE((TITAN_GE_GDI_INTERRUPT_ENABLE + (port_num << 8)), reg_data);
863 TITAN_GE_WRITE((TITAN_GE_CHANNEL0_CONFIG + (port_num << 8)), reg_data);
867 TITAN_GE_WRITE((0x5048 + (port_num << 8)), count);
878 TITAN_GE_WRITE(TITAN_GE_SDQPF_RXFIFO_CTL, reg_data);
880 TITAN_GE_WRITE(TITAN_GE_SDQPF_RXFIFO_CTL, reg_data);
882 TITAN_GE_WRITE(TITAN_GE_SDQPF_RXFIFO_CTL, reg_data);
886 TITAN_GE_WRITE(TITAN_GE_SDQPF_TXFIFO_CTL, reg_data);
888 TITAN_GE_WRITE(TITAN_GE_SDQPF_TXFIFO_CTL, reg_data);
890 TITAN_GE_WRITE(TITAN_GE_SDQPF_TXFIFO_CTL, reg_data);
901 TITAN_GE_WRITE(TITAN_GE_SDQPF_RXFIFO_0, reg_data);
907 TITAN_GE_WRITE(0x4844, reg_data1);
912 TITAN_GE_WRITE(TITAN_GE_SDQPF_RXFIFO_0, reg_data);
917 TITAN_GE_WRITE(TITAN_GE_SDQPF_TXFIFO_0, reg_data);
921 TITAN_GE_WRITE(TITAN_GE_SDQPF_TXFIFO_0, reg_data);
929 TITAN_GE_WRITE(0x4944, reg_data1);
934 TITAN_GE_WRITE(TITAN_GE_SDQPF_TXFIFO_0, reg_data);
944 TITAN_GE_WRITE(0x4870, reg_data);
950 TITAN_GE_WRITE(0x4874, reg_data1);
955 TITAN_GE_WRITE(0x4870, reg_data);
960 TITAN_GE_WRITE(0x494c, reg_data);
962 TITAN_GE_WRITE(0x494c, reg_data);
970 TITAN_GE_WRITE(0x4950, reg_data1);
975 TITAN_GE_WRITE(0x494c, reg_data);
990 TITAN_GE_WRITE(0x48a0, reg_data);
996 TITAN_GE_WRITE(0x48a4, reg_data1);
1001 TITAN_GE_WRITE(0x48a0, reg_data);
1006 TITAN_GE_WRITE(0x4958, reg_data);
1008 TITAN_GE_WRITE(0x4958, reg_data);
1016 TITAN_GE_WRITE(0x495c, reg_data1);
1021 TITAN_GE_WRITE(0x4958, reg_data);
1030 TITAN_GE_WRITE(0x48a0, reg_data);
1036 TITAN_GE_WRITE(0x48a4, reg_data1);
1041 TITAN_GE_WRITE(0x48a0, reg_data);
1046 TITAN_GE_WRITE(0x4958, reg_data);
1048 TITAN_GE_WRITE(0x4958, reg_data);
1056 TITAN_GE_WRITE(0x495c, reg_data1);
1061 TITAN_GE_WRITE(0x4958, reg_data);
1077 TITAN_GE_WRITE((0x103c + (port_num << 12)), reg_data_1);
1080 TITAN_GE_WRITE((0x103c + (port_num << 12)), reg_data_1);
1085 TITAN_GE_WRITE((0x103c + (port_num << 12)), reg_data_1);
1090 TITAN_GE_WRITE((TITAN_GE_TRTG_CONFIG + (port_num << 12)), reg_data);
1095 TITAN_GE_WRITE((TITAN_GE_TMAC_CONFIG_2 + (port_num << 12)), 0xe197);
1097 TITAN_GE_WRITE((0x1258 + (port_num << 12)), 0x4000);
1103 TITAN_GE_WRITE((TITAN_GE_TMAC_CONFIG_1 + (port_num << 12)), reg_data);
1110 TITAN_GE_WRITE((TITAN_GE_RMAC_CONFIG_2 + (port_num << 12)), reg_data);
1112 TITAN_GE_WRITE((0x1218 + (port_num << 12)), 0x3);
1115 TITAN_GE_WRITE((0x1208 + (port_num << 12)), 0x4000);
1124 TITAN_GE_WRITE((TITAN_GE_RMAC_CONFIG_1 + (port_num << 12)), reg_data);
1136 TITAN_GE_WRITE(0x0038, 0x003);
1138 TITAN_GE_WRITE(0x0038, 0x303);
1149 TITAN_GE_WRITE(TITAN_GE_INTR_XDMA_IE, reg_data1);
1150 TITAN_GE_WRITE(0x003c, 0x300);
1153 TITAN_GE_WRITE(0x0024, 0x04000024); /* IRQ vector */
1154 TITAN_GE_WRITE(0x0020, 0x000fb000); /* INTMSG base */
1160 TITAN_GE_WRITE((0x1038 + (port_num << 12)), reg_data);
1166 TITAN_GE_WRITE(0x1a80, 0);
1196 TITAN_GE_WRITE((0x5044 + (port_num << 8)), 0x1);
1225 TITAN_GE_WRITE((TITAN_GE_RMAC_CONFIG_1 +
1229 TITAN_GE_WRITE((TITAN_GE_CHANNEL0_INTERRUPT +
1233 TITAN_GE_WRITE(TITAN_GE_INTR_XDMA_CORE_A, 0);
1234 TITAN_GE_WRITE(TITAN_GE_INTR_XDMA_CORE_B, 0);
1663 TITAN_GE_WRITE((0x5048 + (port_num << 8)), ack);
1669 TITAN_GE_WRITE((0x5048 + (port_num << 8)), ack);
1706 TITAN_GE_WRITE(TITAN_GE_INTR_XDMA_IE, reg_data);
1731 TITAN_GE_WRITE(TITAN_GE_INTR_XDMA_CORE_A, 0x3);
1733 TITAN_GE_WRITE(TITAN_GE_INTR_XDMA_CORE_A, 0x300);
1735 TITAN_GE_WRITE(TITAN_GE_INTR_XDMA_CORE_A, 0x30000);
1835 TITAN_GE_WRITE((TITAN_GE_CHANNEL0_CONFIG +
1842 TITAN_GE_WRITE((TITAN_GE_TMAC_CONFIG_1 +
1881 TITAN_GE_WRITE((TITAN_GE_CHANNEL0_CONFIG +
1888 TITAN_GE_WRITE((TITAN_GE_RMAC_CONFIG_1 +
1930 TITAN_GE_WRITE(TITAN_GE_INTR_XDMA_IE, 0x0);
1957 TITAN_GE_WRITE((TITAN_GE_TMAC_STATION_HI + (port_num << 12)),
1959 TITAN_GE_WRITE((TITAN_GE_TMAC_STATION_MID + (port_num << 12)),
1961 TITAN_GE_WRITE((TITAN_GE_TMAC_STATION_LOW + (port_num << 12)),
1964 TITAN_GE_WRITE((TITAN_GE_RMAC_STATION_HI + (port_num << 12)),
1966 TITAN_GE_WRITE((TITAN_GE_RMAC_STATION_MID + (port_num << 12)),
1968 TITAN_GE_WRITE((TITAN_GE_RMAC_STATION_LOW + (port_num << 12)),
2242 TITAN_GE_WRITE((TITAN_GE_TMAC_CONFIG_1 +
2249 TITAN_GE_WRITE((TITAN_GE_RMAC_CONFIG_1 +
2287 TITAN_GE_WRITE(TITAN_GE_INT_COALESCING, delay);
2288 TITAN_GE_WRITE(0x5038, delay);
2304 TITAN_GE_WRITE(TITAN_GE_INT_COALESCING, delay);
2305 TITAN_GE_WRITE(0x5038, delay);