Lines Matching refs:TITAN_GE_READ
227 reg_data = TITAN_GE_READ(TITAN_GE_GMII_CONFIG_GENERAL + in titan_ge_gmii_config()
241 reg_data = TITAN_GE_READ(TITAN_GE_TMAC_CONFIG_1 + in titan_ge_enable_tx()
336 (unsigned long)TITAN_GE_READ(0x100c + (port << 12))); in titan_ge_tx_timeout_task()
340 (unsigned long)TITAN_GE_READ(0x482c)); in titan_ge_tx_timeout_task()
342 (unsigned long)TITAN_GE_READ(0x0040)); in titan_ge_tx_timeout_task()
344 (unsigned long)TITAN_GE_READ(0x5008 + (port << 8))); in titan_ge_tx_timeout_task()
346 (unsigned long)TITAN_GE_READ(TITAN_GE_CHANNEL0_INTERRUPT in titan_ge_tx_timeout_task()
408 reg_data = TITAN_GE_READ(TITAN_GE_XDMA_CONFIG); in titan_ge_xdma_reset()
414 reg_data = TITAN_GE_READ(TITAN_GE_XDMA_CONFIG); in titan_ge_xdma_reset()
481 eth_int_cause1 = TITAN_GE_READ(TITAN_GE_INTR_XDMA_CORE_A);
483 eth_int_cause2 = TITAN_GE_READ(TITAN_GE_INTR_XDMA_CORE_B);
492 eth_int_cause_error = TITAN_GE_READ(TITAN_GE_CHANNEL0_INTERRUPT +
519 ack = TITAN_GE_READ(TITAN_GE_INTR_XDMA_IE);
549 TITAN_GE_READ(0x5008 + (port_num << 8)), port_num);
553 TITAN_GE_READ(0x5048 + (port_num << 8)));
557 TITAN_GE_READ(0x505c + (port_num << 8)));
610 reg_data = TITAN_GE_READ(TITAN_GE_AFX_ADDRS_FILTER_CTRL_1 +
759 reg_data = TITAN_GE_READ(TITAN_GE_CHANNEL0_CONFIG);
765 reg_data = TITAN_GE_READ(TITAN_GE_CHANNEL0_CONFIG);
770 reg_data = TITAN_GE_READ(TITAN_GE_CHANNEL0_CONFIG);
776 reg_data = TITAN_GE_READ(TITAN_GE_CHANNEL0_CONFIG);
795 reg_data = TITAN_GE_READ(0x0004);
803 reg_data = TITAN_GE_READ(TITAN_GE_TSB_CTRL_1);
833 reg_data = TITAN_GE_READ(TITAN_GE_XDMA_CONFIG);
843 reg_data = TITAN_GE_READ(TITAN_GE_GDI_INTERRUPT_ENABLE + (port_num << 8));
848 reg_data = TITAN_GE_READ(TITAN_GE_CHANNEL0_CONFIG + (port_num << 8));
868 count = TITAN_GE_READ(0x5048 + (port_num << 8));
876 reg_data = TITAN_GE_READ(TITAN_GE_SDQPF_RXFIFO_CTL);
881 reg_data = TITAN_GE_READ(TITAN_GE_SDQPF_RXFIFO_CTL);
884 reg_data = TITAN_GE_READ(TITAN_GE_SDQPF_TXFIFO_CTL);
889 reg_data = TITAN_GE_READ(TITAN_GE_SDQPF_TXFIFO_CTL);
896 reg_data = TITAN_GE_READ(TITAN_GE_SDQPF_RXFIFO_0);
905 reg_data1 = TITAN_GE_READ(0x4844);
914 reg_data = TITAN_GE_READ(TITAN_GE_SDQPF_TXFIFO_0);
926 reg_data1 = TITAN_GE_READ(0x4944);
939 reg_data = TITAN_GE_READ(0x4870);
948 reg_data1 = TITAN_GE_READ(0x4874);
957 reg_data = TITAN_GE_READ(0x494c);
967 reg_data1 = TITAN_GE_READ(0x4950);
985 reg_data = TITAN_GE_READ(0x48a0);
994 reg_data1 = TITAN_GE_READ(0x48a4);
1003 reg_data = TITAN_GE_READ(0x4958);
1013 reg_data1 = TITAN_GE_READ(0x495c);
1025 reg_data = TITAN_GE_READ(0x48a0);
1034 reg_data1 = TITAN_GE_READ(0x48a4);
1043 reg_data = TITAN_GE_READ(0x4958);
1053 reg_data1 = TITAN_GE_READ(0x495c);
1067 reg_data = TITAN_GE_READ(TITAN_GE_TRTG_CONFIG + (port_num << 12));
1075 reg_data_1 = TITAN_GE_READ(0x103c + (port_num << 12));
1099 reg_data = TITAN_GE_READ(TITAN_GE_TMAC_CONFIG_1 + (port_num << 12));
1108 reg_data = TITAN_GE_READ(TITAN_GE_RMAC_CONFIG_2 + (port_num << 12));
1118 reg_data = TITAN_GE_READ(TITAN_GE_RMAC_CONFIG_1 + (port_num << 12));
1131 reg_data1 = TITAN_GE_READ(TITAN_GE_INTR_XDMA_IE);
1158 reg_data = TITAN_GE_READ(0x1038 + (port_num << 12));
1222 reg_data = TITAN_GE_READ(TITAN_GE_RMAC_CONFIG_1 +
1696 TITAN_GE_READ(TITAN_GE_INTR_XDMA_IE);
1749 status = TITAN_GE_READ(TITAN_GE_INTR_XDMA_CORE_A);
1832 reg_data = TITAN_GE_READ(TITAN_GE_CHANNEL0_CONFIG +
1839 reg_data = TITAN_GE_READ(TITAN_GE_TMAC_CONFIG_1 +
1878 reg_data = TITAN_GE_READ(TITAN_GE_CHANNEL0_CONFIG +
1885 reg_data = TITAN_GE_READ(TITAN_GE_RMAC_CONFIG_1 +
2012 device = TITAN_GE_READ(TITAN_GE_DEVICE_ID);
2239 reg_data = TITAN_GE_READ(TITAN_GE_TMAC_CONFIG_1 +
2246 reg_data = TITAN_GE_READ(TITAN_GE_RMAC_CONFIG_1 +
2301 rx_delay = TITAN_GE_READ(TITAN_GE_INT_COALESCING);