322 #undef writew
328 #define writew outw  macro
715 	writew(0x007f, ioaddr + ASICCtrl + 2);  in sundance_probe1()
755 	writew(0x0200 | (location & 0xff), ioaddr + EECtrl);  in eeprom_read()
878 	writew(dev->mtu + 18, ioaddr + MaxFrameSize);  in netdev_open()
880 	writew(dev->mtu + 14, ioaddr + MaxFrameSize);  in netdev_open()
893 	writew(0, ioaddr + IntrEnable);  in netdev_open()
894 	writew(0, ioaddr + DownCounter);  in netdev_open()
903 	writew (StatsEnable | RxEnable | TxEnable, ioaddr + MACCtrl1);  in netdev_open()
920 	writew(DEFAULT_INTR, ioaddr + IntrEnable);  in netdev_open()
936 			writew (readw (ioaddr + MACCtrl0) | EnbFullDuplex,  in check_duplex()
949 		writew(readw(ioaddr + MACCtrl0) | duplex ? 0x20 : 0, ioaddr + MACCtrl0);  in check_duplex()
979 	writew(0, ioaddr + IntrEnable);  in tx_timeout()
1018 	writew(DEFAULT_INTR, ioaddr + IntrEnable);  in tx_timeout()
1145 	writew (TxDisable, ioaddr + MACCtrl1);  in reset_tx()
1146 	writew (TxReset | DMAReset | FIFOReset | NetworkReset,  in reset_tx()
1170 	writew (StatsEnable | RxEnable | TxEnable, ioaddr + MACCtrl1);  in reset_tx()
1190 		writew(intr_status, ioaddr + IntrStatus);  in intr_handler()
1200 			writew(DEFAULT_INTR & ~(IntrRxDone|IntrRxDMADone),  in intr_handler()
1229 						writew (TxEnable,  in intr_handler()
1233 				writew (0, ioaddr + TxStatus);  in intr_handler()
1383 	writew(DEFAULT_INTR, ioaddr + IntrEnable);  in rx_poll()
1467 			writew(readw(ioaddr + MulticastFilter1+2) | 0x0200,  in netdev_error()
1469 			writew(readw(ioaddr + MACCtrl0) | EnbFlowCtrl,  in netdev_error()
1551 		writew(mc_filter[i], ioaddr + MulticastFilter0 + i*2);  in set_rx_mode()
1560 	writew(addr16, dev->base_addr + StationAddr);  in __set_mac_addr()
1562 	writew(addr16, dev->base_addr + StationAddr+2);  in __set_mac_addr()
1564 	writew(addr16, dev->base_addr + StationAddr+4);  in __set_mac_addr()
1715 	writew(0x0000, ioaddr + IntrEnable);  in netdev_close()
1718 	writew(TxDisable | RxDisable | StatsDisable, ioaddr + MACCtrl1);  in netdev_close()