Lines Matching refs:BIT_5S
75 #define BIT_5S (1 << 5) macro
180 #define PCI_VGA_SNOOP BIT_5S /* VGA palette snoop */
203 #define PCI_66MHZCAP BIT_5S /* 66 MHz PCI bus clock capable */
313 #define PCI_PM_DSI BIT_5S /* Device Specific Initialization */
813 #define CS_STOP_DONE BIT_5S /* Stop Master is finished */
967 #define TST_FRC_DPERR_TR BIT_5S /* force DATAPERR on TRG RD */
1086 #define MA_ENA_REC_TX1 BIT_5S /* Enable Recovery Timer TX1 */
1104 #define PA_ENA_TO_RX2 BIT_5S /* Enable Timeout Timer RX2 */
1129 #define RX2_T_OFF BIT_5S /* RX2 Timeout/Recv Timer Tst Off */
1148 #define TXA_ENA_ALLOC BIT_5S /* Enable alloc of free bandwidth */
1157 #define TXA_INT_T_ON BIT_5S /* Tx Arb Interval Timer Test On */
1285 #define RB_WP_T_OFF BIT_5S /* Write Pointer Test Off */
1294 #define RB_ENA_STFWD BIT_5S /* Enable Store & Forward */
1328 #define MFF_ENA_FLUSH BIT_5S /* Enable Frame Flushing */
1361 #define MFF_WSP_T_OFF BIT_5S /* Tx: Write Shadow Ptr TstOff */
1372 #define MFF_WP_T_OFF BIT_5S /* Write Pointer Test Off */
1409 #define LED_BLK_ON BIT_5S /* Link LED Blinking On */
1571 #define WOL_CTL_ENA_LINK_CHG_UNIT BIT_5S