Lines Matching refs:BIT_3S
77 #define BIT_3S (1 << 3) macro
182 #define PCI_SCYCEN BIT_3S /* Special Cycle enable */
205 #define PCI_INT_STAT BIT_3S /* Interrupt INTx# Status (PCI 2.3) */
315 #define PCI_PME_CLOCK BIT_3S /* PM Event Clock */
815 #define CS_MRST_CLR BIT_3S /* Clear Master reset */
928 #define LD_T_ON BIT_3S /* Loader Test mode on */
969 #define TST_FRC_APERR_M BIT_3S /* force ADDRPERR on MST */
977 #define TST_FRC_DPERR_MR64 BIT_3S /* DataPERR RD 64 */
1069 #define RI_T_EV BIT_3S /* Timeout Event occured */
1077 #define MA_FOE_ON BIT_3S /* XMAC Fast Output Enable ON */
1088 #define MA_ENA_REC_RX2 BIT_3S /* Enable Recovery Timer RX2 */
1106 #define PA_ENA_TO_RX1 BIT_3S /* Enable Timeout Timer RX1 */
1131 #define RX1_T_EV BIT_3S /* RX1 Timeout/Recv Event occured */
1150 #define TXA_START_RC BIT_3S /* Start sync Rate Control */
1159 #define TXA_INT_T_STEP BIT_3S /* Tx Arb Interval Timer Step */
1238 #define SM_LOAD BIT_3S /* Load the SM with SM_STATE */
1277 #define RB_PC_DEC BIT_3S /* Packet Counter Decrem */
1296 #define RB_ENA_OP_MD BIT_3S /* Enable Operation Mode */
1330 #define MFF_ENA_TIST BIT_3S /* Enable Time Stamp Gener */
1350 #define MFF_ENA_LOOPB BIT_3S /* Enable Loopback */
1363 #define MFF_PC_DEC BIT_3S /* Packet Counter Decrement */
1382 #define MFF_ENA_OP_MD BIT_3S /* Enable Operation Mode */
1411 #define LED_SYNC_ON BIT_3S /* Use Sync Wire to switch LED */
1573 #define WOL_CTL_ENA_MAGIC_PKT_UNIT BIT_3S